DE102011054372B4 - Method for producing a semiconductor transistor structure - Google Patents

Abstract

A method of fabricating a semiconductor transistor structure (100), comprising: providing a semiconductor body (40) having a horizontal main surface (15); Forming a vertical trench (19a) extending from the main horizontal surface (15) into the semiconductor body (40); Forming a first dielectric layer (7) in the vertical trench (19a, 19); Forming a first conductive region (13a) on the first dielectric layer (7) in the vertical trench (19a) such that the first conductive region (13a) is retracted from the main horizontal surface (15); Filling the vertical trench (19a, 14) with a second dielectric layer (8) covering the first conductive region (13a); and removing the first dielectric layer (7) and the second dielectric layer (8) from an upper portion of the vertical trench (19a) to expose the semiconductor body at a sidewall of the vertical trench (19a), the first conductive region (13a) being from the second Dielectric layer (8) remains covered.

Description

FIELD OF THE INVENTION

The present invention relates to a method for producing a semiconductor transistor structure, in particular to a method for producing a field effect transistor structure having a buried insulated field plate.

BACKGROUND

Many functions of modem devices in automotive, consumer, and industrial applications, such as converting electrical energy, driving an electric motor or electric machine, and modulating signals, for example in hi-fi audio amplifier circuits, are based on semiconductor transistors, particularly field effect transistors (FET) such as MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistor) and IGBTs (Insulated Gate Bipolar Transistors). As a control electrode of the transistor used in these components, a respect to the semiconductor body insulated gate electrode, which is also referred to below as the gate electrode.

In addition to the capacitances between the gate electrode and the other two terminals of the transistor, source electrode and drain electrode for a MOSFET or emitter electrode and collector electrode for an IGBT, the blocking capability of the transistor is an important operating parameter. Buried isolated field plates can be used to increase the blocking capability with the same on-resistance Ron. Such power semiconductor devices are known from DE 11 2009 003 514 T5 known. By buried insulated field plates also the gate-drain capacitance of the transistor can be reduced. On the other hand, an additional capacitance forms between the gate electrode and field plate, which forms part of the capacitance between gate and source terminal, since the field plate is typically also supplied with the source potential. The dielectric constant and the integrated thickness of the insulating layer between the gate electrode and the field plate influence this additional capacitance and thus the capacitance between the gate and source terminals.

The switching behavior of the transistor is essentially determined by the gate-drain capacitance and the gate-source capacitance. In particular, the gate-drain capacitance influences the switching speed of the component, and thus the steepness of switching edges of a current flowing through the component or a voltage drop across the component. The gate-drain capacitance of the transistor device depends, for example, on the area at which the gate electrode and a drain region of the device overlap one another, and on the dielectric constant and the thickness of the gate oxide between the gate electrode and the drift region.

Typically, the gate oxide and the oxide are generated between the gate electrode and the field plate in a common oxidation process. In particular, in the case of thin gate oxides, the additional capacitance between the insulated gate electrode and the field plate can become relatively large. For fast switching operations, this additional capacitance may result in undesirable turn-on of the MOSFET by positively charging the field plate through the drain potential and then positively charging the gate electrode through the additional capacitance. The reconnection associated with this leads to power losses and reduces the efficiency of the gate-source capacitance.

In view of the above, the present invention proposes a method of manufacturing a semiconductor transistor structure according to claim 1 and a method of manufacturing a semiconductor transistor structure according to claim 18.

BRIEF SUMMARY OF THE INVENTION

According to one embodiment, a method of manufacturing a semiconductor transistor structure is provided. The method includes providing a semiconductor body having a horizontal major surface. A vertical trench extending from the horizontal main surface into the semiconductor body is formed. A first dielectric layer is formed in the vertical trench. On the first dielectric layer in the vertical trench, a first conductive region is formed such that the first conductive region is withdrawn from the horizontal main surface. The vertical trench is filled with a second dielectric layer covering the first conductive region. The first dielectric layer and the second dielectric layer are removed from an upper portion of the vertical trench to expose the semiconductor body at a sidewall of the vertical trench, leaving the first conductive region covered by the second dielectric layer.

In accordance with another embodiment, a method of fabricating a semiconductor transistor structure is provided. The method includes providing a semiconductor body having a horizontal major surface. A vertical trench is formed which extends from the horizontal main surface into the semiconductor body. In a lower portion of the vertical trench, a field oxide and a field plate are formed. The vertical trench is filled with a HDP oxide. Plasma etching removes the HDP oxide from an upper portion of the vertical trench. An insulated gate electrode is formed in the upper portion of the vertical trench. Prior to plasma etching, typically the field oxide and the HDP oxide are removed from the horizontal major surface by planarization. Additionally, plasma etching typically also removes the field oxide from the upper portion of the vertical trench to expose the semiconductor body to a sidewall of the vertical trench in the upper portion for gate oxide formation.

Further advantageous embodiments, details, aspects and features of the present invention will become apparent from the dependent claims, the description and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. The drawings are not scaled and are for illustrative purposes. The elements of the drawings are not necessarily to scale relative to one another. For the sake of clarity, the same elements or manufacturing steps in the various drawings have been given the same reference numerals, unless otherwise specified.

The 1 to 8th illustrate in schematic vertical cross-sections through the semiconductor body process steps for the production of a vertical semiconductor device according to one or more embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, terms from the directional terminology such as "top", "bottom", "front", "back", "front", "back", etc. are used with reference to the orientation of the described figure (s). Because components of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is therefore not to be understood in a limiting sense.

Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is illustrative and is not intended to be limiting of the invention. For example, features illustrated or described as part of one embodiment can be used with or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention include such modifications and variations. The examples are described using a specific language which should not be construed as limiting the scope of the appended claims.

The term "horizontal" as used herein is intended to describe an orientation substantially parallel to a first or horizontal major surface of a semiconductor substrate or body. This may be, for example, the surface of a wafer or a chip.

The term "vertical," as used herein, is intended to describe an orientation that is substantially perpendicular to the horizontal major surface, i. H. parallel to the normal direction of the horizontal main surface of the semiconductor substrate or body.

In the following, n-doped is referred to as a first conductivity type, while p-doped is referred to as a second conductivity type. The majority carriers of an n-type doped region and a p-type doped region are electrons and holes, respectively. In this specification, a negative charge type is referred to as a first charge type, while a positive charge type is referred to as a second charge type. Of course, the semiconductor devices may also be formed with opposite dopants so that the first conductivity type may be p-doped and the second conductivity type may be n-doped. Accordingly, the first charge type may also designate the charge type of holes. Further, some figures illustrate relative doping concentrations by symbols "-" or "+" attached to the doping type. For example, "n" means a doping concentration smaller than the doping concentration of an "n" -doping region, while an "n ⁺ " -doping region has a larger doping concentration than the "n" -doping region. However, indicating the relative doping concentration does not mean that doping regions having the same relative doping concentration must have the same absolute doping concentration, unless otherwise specified. For example, two different n ⁺ - Areas have different absolute doping concentrations. The same applies, for example, to an n ⁺ and a p ^{+ region} .

The embodiments described herein relate to buried insulated field plate field effect transistors, in particular field effect transistors having a field plate arranged in a vertical trench and a gate electrode disposed above it. The term "field effect" as used herein is intended to mean the electrically-field forming of a conductive "channel" of a first conductivity type and / or a control of the conductivity and / or a shape of the channel in a semiconductor region of a second conductivity type , typically a body region of the second conductivity type. Due to the field effect, by the electric field in a MOSFET, a unipolar current path is formed and / or controlled by the channel region between a first conductivity type source region in ohmic contact with a source electrode and a first conductivity type drift region. The drift region is in ohmic contact with a drain region of the first conductivity type which is in ohmic contact with a drain electrode. Without application of an external voltage between the gate electrode and the source electrode, the current path between the source electrode and the drain electrode is interrupted by the semiconductor device with normally-off field-effect devices or has at least a high resistance. In an IGBT, an emitter region corresponds to the source region of the MOSFET. In addition, in an IGBT, between the drift region and a collector electrode, instead of the drain electrode, there is another pn junction which may be formed between a collector region of the second conductivity type instead of the drain region and the drift region.

The term "field effect structure" as used herein is intended to describe a structure formed in a semiconductor substrate or a semiconductor device with a gate electrode for forming and / or forming a conductive inversion channel, hereinafter also referred to as a channel, in the channel region. The gate electrode is isolated by a dielectric region or a dielectric layer at least from the channel region. In the present case, this dielectric region is also referred to as gate oxide for simplification, even if it is not an oxide such as silicon oxide (SiO ₂ ) but another dielectric such as silicon nitride (Si ₃ N ₄ ).

The term "field plate" as used herein is intended to describe an electrode disposed adjacent to a semiconductor region, typically a drift region, that is isolated from the semiconductor region and configured to have a space charge region in the semiconductor region, ie, an evacuated portion in the semiconductor region, by applying a corresponding voltage, typically a positive voltage for an n-type drift region. The terms "cleared" and "completely cleared" are intended to describe that a semiconductor region does not substantially comprise any free charge carriers. Typically, isolated field plates are located close to pn junctions, e.g. B. formed between a drift area and a body area. Accordingly, the reverse voltage of the pn junction and the semiconductor device can be increased. The dielectric layer or the dielectric region which isolates the field plate from the drift region is also referred to below as a field dielectric layer, a field dielectric field or, more simply, as a field oxide, even if it is not an oxide but another dielectric. Examples of dielectric materials for forming a dielectric region or a dielectric layer between the gate electrode or a field plate and the semiconductor body and between the gate electrode and the field plate include SiO ₂ , Si ₃ N ₄ , SiO _x N _v , Al ₂ O ₃ , ZrO, among others ₂ , Ta ₂ O ₅ , TiO ₂ and HfO ₂ . The gate electrode and the field plate may be subjected to the same electrical potential during operation of the device. However, during operation, the field plate is typically supplied with the same potential as the source region or the emitter region, in order to keep the gate-drain capacitance as small as possible.

The term "power field effect transistor" as used herein is intended to describe a field effect transistor on a single chip with high voltage and / or high current switching capabilities. In other words, high power power field effect transistors are typically in the ampere range and / or high voltages typically above 20V, especially over 400V.

Related to the 1 to 8th Now be process steps for the production of a vertical semiconductor device 100 explained. In a first step, a semiconductor body 40 with a horizontal main surface 15 and one opposite the horizontal main surface 15 arranged second surface 16 or back 16 provided. 1 shows the semiconductor body 40 in a schematic vertical cross-section. The normal direction e _{n of} the horizontal main surface 15 is substantially parallel to the vertical direction, ie defines it.

Hereinafter, embodiments of the manufacturing method are mainly under Reference to semiconductor devices 100 made of silicon (Si). Accordingly, a monocrystalline semiconductor region or a monocrystalline semiconductor layer is typically a monocrystalline Si region or a monocrystalline Si layer. It is understood, however, that the semiconductor body 40 may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge) and their mixed forms (Si _x Ge _v ), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe). binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP) or indium gallium arsenide phosphide (InGaAsP) and binary or ternary II VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name but a few. The above-mentioned semiconductor materials are also referred to as homojunction semiconductor materials. When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, among others, aluminum gallium nitride (AlGaN) and gallium nitride (GaN) or silicon silicon carbide (Si _x C _1-x ) and SiGe heterojunction semiconductor material. For power semiconductor applications, the materials Si, SiC and GaN are currently mainly used. If the semiconductor body comprises a large bandgap material such as SiC or GaN having a high breakdown electric field strength from which avalanche multiplication starts, the doping of the respective semiconductor regions may be made higher, reducing the _on- resistance R _on .

The semiconductor body 40 is typically a wafer 40 or a chip 40 , Typically, the semiconductor body contains 40 a semiconductor substrate 20 and one or more epitaxial layers grown thereon 30 , The semiconductor body 40 but may also have been produced by wafer bonding. In the in 1 illustrated exemplary embodiment forms the semiconductor substrate 20 a first semiconductor region 1 of the n-type, which later became a drainage area 1 can form a MOSFET structure. On top is as an epitaxial layer 20 a weaker doped second semiconductor region 2 arranged of n-type, that differs from the first semiconductor region 1 up to the horizontal main surface 15 extends. In other embodiments, the first semiconductor region is 1 p-type, e.g. B. p ⁺ doped. The semiconductor area 1 or parts of it can later form a collector area of an IGBT. 1 shows the semiconductor body 40 after being on the horizontal main surface 15 a structured mask 6 typically formed of silicon oxide or silicon nitride.

Below are through the mask 6 vertical trenches 19 . 19a from the horizontal main surface 15 in the semiconductor body 40 etched. The vertical trenches 19 . 19a can partially extend into the first semiconductor region 1 extend. At least on the floor and on the side walls of the vertical trenches 19 . 19a becomes a first dielectric layer 7 educated. Typically, the first dielectric layer is 7 around a silicon oxide layer, when using a silicon semiconductor body 40 can be generated by thermal oxidation. In other embodiments, the first dielectric layer becomes 7 generated by a deposition process.

Subsequently, on the first dielectric layer 7 in the vertical trenches 19 . 19a a respective first conductive area 13 . 13a generated. Typically, the first conductive regions exist 13 . 13a made of sufficiently highly doped poly-silicon. For generating the first conductive regions 13 . 13a For this purpose, first poly-silicon can be deposited. In the trenches 19a For example, the deposited poly-silicon is then partially removed to a first vertical depth d ₁ , typically by a plasma etching process preceded by a CMP process. As a result, the first conductive areas 13a in the vertical trenches 19a arranged only in a respective lower trench portion, ie from the horizontal main surface 15 spaced. The vertical ditch 19 may during etch back through another mask 17 be covered, so that the conductive area 13 not etched back there. 2 shows the resulting semiconductor structure 100 in a schematic vertical cross-section.

The first vertical depth d ₁ is selected to be somewhat larger than the channel length, ie the length of the channel in the later formed body region along the gate oxide also formed later. Depending on the component characteristic, the first vertical depth d ₁ can be precisely determined via the parameters of the plasma etching process. For example, for a device having a nominal voltage of 100 V, the first vertical depth d _{1 is} typically about 1 μm.

In the in 2 Illustrated exemplary embodiment will be three vertical trenches 19 . 19a shown. It is characterized by the isolated first conductive region 13 in the left ditch 19 for the later completed semiconductor device, an edge termination structure is provided to increase the breakdown voltage in the case of blocking. This can be the left trench 19 deeper into the semiconductor body 40 or the semiconductor substrate 20 extend as the adjacent vertical trenches 19 , Besides, the ditch is 19 typically running around the edge of the edge, leaving the trenches 19a completely surrounds a component in horizontal cross-sections. Corresponds accordingly 2 typically only a left-hand section of a complete vertical section through the semiconductor body 40 , In this context, it should be mentioned that it is the semiconductor body 40 typically is a wafer on which a plurality of semiconductor devices 100 each with surrounding deep trenches 19 can be made in parallel. In a further embodiment with lower requirements for the blocking capability of the device is based on generation of the optional vertical trench 19 dispensed with, which can save wafer or chip area.

In the in 2 Illustrated exemplary embodiment, two vertical trenches 19a shown in which later gate electrodes are formed. In other embodiments, only a vertical trench 19a generated for a gate electrode. It is understood that in further embodiments, a plurality of vertical trenches 19a for gate electrodes per semiconductor device can be generated, for example, when a power semiconductor device is manufactured.

In the 1 shown mask 6 is in 2 not shown. For example, it may be prior to forming the first dielectric layer 7 have been removed. In other embodiments, the mask remains 6 however, on the horizontal main surface 15 , If so, the first dielectric layer 7 was created by deposition, so is the mask 6 between the horizontal main surface 15 and the first dielectric layer 7 , If the first dielectric layer 7 with on the horizontal main surface 15 remaining mask 6 , z. As a silicon nitride mask, is generated by thermal oxidation, so is the first dielectric layer 7 only on the side walls and on the bottom of the vertical trenches 19 . 19a generated.

The mask 17 can now be removed. According to a development, the first dielectric layer 7 selectively, ie selectively to the material of the first conductive regions 13 . 13 , etched back to the trenches 19 expand in a respective upper section. This allows the aspect ratio, ie the ratio of trench depth to trench width, of the vertical trenches 19 to a value of z. B. about 2: 1 to about 3: 1 can be reduced, which may favorably influence the subsequent dielectric deposition. Accordingly, that too becomes on the horizontal main surface 15 existing material of the dielectric layer 7 thinned. 3 shows the resulting semiconductor structure 100 in a schematic cross section. For this purpose, an isotropic etching process is typically used.

Typically, the first dielectric layer 7 in the vertical trenches 19 so far etched back that the first conductive areas 13a partially exposed in a respective upper section. The etching back takes place up to a second vertical depth d ₂ which is slightly larger than the first vertical depth d ₁ , z. B. about 10 nm to about 400 nm, preferably about 20 nm to about 200 nm.

Subsequently, the vertical trenches 19a with a second dielectric layer 8th refilled. At the dielectric layer 8th This can be especially the case with low aspect ratios of the vertical trenches 19a from Z. B. less than 1: 1 to a TEOS layer (tetraethyl orthosilicate) act.

Typically, the vertical trenches 19a but by a nonconforming deposition with the dielectric layer 8th refilled. The dielectric layer 8th grows from bottom to top. This causes the vertical height of the dielectric layer 8th over the first conductive areas 13a typically at least 1.5 times the horizontal layer thickness on the sidewalls of the vertical trenches 19a , The resulting semiconductor structure 100 is in 4 shown in a schematic vertical cross-section.

According to a development, the non-conformal deposition of the dielectric layer takes place 8th by means of an HDP process (high-density plasma), in which the dielectric layer 8th in a special HDP-CVD (chemical vapor deposition) method as so-called HDP-oxides, typically as HDP-silica.

In a subsequent step, planarizing the second dielectric layer 8th and optionally on the horizontal surface 15 existing first dielectric layer 7 from the horizontal surface 17 typically removed again to the semiconductor body 40 at or at the horizontal main surface 15 expose. The planarization typically involves an oxide CMP process (chemical mechanical polishing), but may also include a mechanical polishing process and / or another chemical mechanical polishing process. 5 shows the resulting semiconductor structure 100 in a schematic vertical cross-section.

If the mask 6 , as in 5 shown in dashed lines, still on the horizontal main surface 15 is present, it can serve as a stop layer during planarization and then removed. This is due to the low removal rate in oxide-CMP processes in particular a silicon nitride 6 , This allows the vertical position of the resulting horizontal main surface 15 be set very precisely.

According to a development, after planarization, a first sacrificial layer is formed on the semiconductor body 40 applied and removed. This can cause any planarization damage on the horizontal main surface 15 of the semiconductor body 40 be removed again. For example, the first sacrificial layer is formed as a thermal oxide, which is removed again by wet chemical etching.

Subsequently, the first dielectric layer 7 and the second dielectric layer 8th from respective upper sections of the trenches 19a removed to the semiconductor body 40 there on the side walls of the trenches 19 expose, wherein the respective first conductive area 13a from the second dielectric layer 8th remains covered. In addition, the optional vertical trench 19 thereby of another mask 18 whose horizontal layout is the in 2 shown mask can be protected.

Typically, the removal of the first dielectric layer then takes place 7 and the second dielectric layer 8th from the upper trench sections to expose the sidewalls for gate oxide generation. 6 shows the resulting semiconductor structure 100 in a schematic, vertical cross section.

The removal of the first dielectric layer 7 and the second dielectric layer 8th typically occurs by a plasma etching process. This allows a third vertical depth d ₃ , ie the vertical distance between the horizontal main surface 15 and in the vertical trenches 19a remaining parts of the second dielectric layer 8th very accurate and with little variation between the vertical trenches 19a to adjust. This allows an accurate and only slightly fluctuating adjustment of the capacitance between the field plates acting as field plates in the manufactured semiconductor device 13a and on the remaining portions of the second dielectric layer 8th formed gate electrodes.

As the first and the second dielectric layer 7 . 8th typically of the same material, e.g. As silicon oxide, may be, the removal of the first dielectric layer 7 and the second dielectric layer 8th from the upper section of the trenches 19a also be done in a common etching process. As a result, the process complexity and thus the manufacturing costs can be reduced.

For any plasma damage from the sidewalls of the vertical trenches 19 and / or the horizontal main surface 15 may remove a second sacrificial layer on the exposed sidewalls and / or the horizontal major surface 15 be generated and removed again. This is typically done again by thermal oxidation and subsequent wet chemical etching.

Subsequently, a thin dielectric layer 9 at least on the side walls of the vertical trenches 19a be formed. This is done with a silicon semiconductor body 40 typically again by thermal oxidation.

Now, typically, respective second conductive regions will become 14 in the upper sections of the vertical trenches 19a educated. This can be done for example by a polysilicon deposition and subsequent partial etching back and / or planarization. 7 shows the resulting semiconductor structure 100 in a schematic vertical cross-section.

Subsequently, by forming further semiconductor regions 4 . 5 in the on the vertical trenches 19a adjacent parts of the second semiconductor regions 2 Transistor structures in the semiconductor body 40 be formed. For this purpose, by appropriate doping processes, for. B. by implantation and subsequent thermal processes, body areas 4 of the second conductivity type and source regions 5 of the first conductivity type in respective upper portions of the second semiconductor regions 2 generated, so the body areas 4 between the source areas and the drift area 2 acting remaining parts of the second semiconductor regions 2 are arranged. In this case, respective pn junctions between the source regions 5 and the body areas 4 as well as between the body areas 4 and the drift areas 2 formed so that it on at least one thin dielectric layer 9 on one of the side walls of the vertical trenches 19a adjoin there a gate oxide to the gate electrode 14 operable second conductive areas 14 form. The vertical distance of the pn junction between the drift regions 2 and the adjacent body area 4 from the horizontal main surface 15 and the vertical distance of the pn junction between adjacent body regions 4 and source regions from the horizontal main surface 15 can be precisely adjusted by implantation or diffusion processes. 8th shows the resulting semiconductor structure 100 in a schematic vertical cross-section.

Subsequently, an insulating intermediate oxide, a gate metallization G and a source metallization S isolated therefrom, as well as corresponding contact structures on the horizontal main surface 15 be generated. This will be the source areas 5 , the body areas 4 , the field plates 13a and the optional edge termination electrode typically having the source metallization S and the gate electrodes 14 connected to the gate metallization G. On the back side 16 In addition, a drain metallization D, z. B. over the entire surface generated.

The switching behavior of the MOSFET structure 100 or an analogously manufacturable IGBT structure in which the first semiconductor region is p ⁺ -doped, is substantially replaced by the gate-drain capacitance C _GD between the gate metallization G and the drain metallization D and the gate-source capacitance C _GS between the Gatemetallisierung G and Sourcemetallisierung S determined. At this time, the gate-drain capacitance C _GD becomes essential by the capacitance between the gate electrodes 14 and the drift area 2 certainly. The gate-source capacitance C _GS is essentially due to the two capacitances C _gs between the gate electrodes 14 and adjacent body and source regions 5 . 4 and C _gf between the gate electrodes 14 and the respective underlying field plate 13a certainly.

By the explained manufacturing process, the formation of the gate oxide 9 on the side walls of the vertical trenches 19a and the dielectric 8th between the gate electrodes 14 and the respective underlying field plates 13a decoupled in a simple way. Thus, in a device very high breakdown voltages of the dielectric 8th and very small gate field plate capacitances C _gf can be realized. The low C _gf values can prevent unintentional reconnection of the MOSFET and the associated power losses.

Thus, the method presented here differs from conventional manufacturing methods in which the gate oxide and the insulation between gate electrode and field plate are generated together.

Due to the previous coupling of the oxidation process for the gate oxide with the oxidation process of the field plate, the thicknesses of the oxides between the gate electrode and the field plate on the one hand and the gate electrode and the source region and body region could not be set independently. With the new method, the gate oxide thickness can be set independently and flexibly, which precisely adjusts the switching behavior of the component and makes it easy to adapt the component for different threshold voltage classes, which usually differ in gate oxide thickness.

In addition, the conventional method results in relatively high accumulated process fluctuations for the so-called base point of the gate electrodes 14 ie for the maximum vertical spacing of the gate electrodes given by the third vertical depth d ₃ 14 from the horizontal main surface 15 , This leads to corresponding variations in the values of the gate-drain capacitance.

This is different with the method presented here. The location of the base of the gate electrodes 14 can be accurately set by a few precisely controllable processes. The variation of the gate base point in the present method is determined exclusively by the very small variation of the plasma etching back of the first and second dielectric layer. Thus, both the absolute value and the fluctuation of the gate-drain capacitance can be reduced and thus the switching characteristics of the transistor can be improved.

In addition, the minimum distance between the gate electrodes 14 and the respective underlying field plates 13a by the plasma etchback of the second dielectric layer 8th set well. This enables independent adjustment of the gate-drain capacitance C _GD and the gate-source capacitance C _GS or the capacitances Cgs and Cgf, so that the semiconductor component 100 can be adapted well to desired performance characteristics.

In addition, the variation of the capacities C _GD , Cgs and Cgf of different vertical trenches 19a be reduced compared to conventional manufacturing processes.

The above with reference to the 1 to 8th Illustrated manufacturing method for producing a semiconductor transistor structure can also be described as follows. A semiconductor body having a horizontal main surface is provided. From the horizontal main surface, a vertical trench extending into the semiconductor body is formed. In a lower portion of the vertical trench, a field oxide and a field plate are formed. Thereafter, the vertical trench is filled with an HDP oxide. By planarizing and plasma etching, the HDP oxide is removed from an upper portion of the vertical trench and an insulated gate electrode is formed in the upper portion of the trench.

To do this, typically the field oxide is removed after filling from the upper portion of the vertical trench to expose the semiconductor body to a sidewall of the vertical trench in the upper portion. This is typically done in a common plasma etching process, which is also used to remove the HDP oxide from the upper section. Thereafter, the gate oxide may be formed on the sidewall of the vertical trench. Subsequently, the upper portion of the vertical trench with a conductive material, for. As poly-Si, are filled to produce the gate electrode. This process control again ensures easy decoupling of the generation of gate oxide and HDP oxide between the field plate and the gate electrode.

In addition, the HDP oxide and optionally existing on the horizontal main surface field oxide before plasma etching by planarizing, z. By an oxide CMP process, typically removed. This, together with the plasma etching, makes it possible to precisely set the base point of the gate electrode even over a whole wafer as a semiconductor body. Thus, the target depth of the gate foot point can be reduced, since now only much less fluctuation are to be maintained. Therefore, the absolute value of the gate-drain capacitance and thus the switching losses of the device during operation can also be reduced.

Claims (20)

Method for producing a semiconductor transistor structure ( 100 ), comprising: providing a semiconductor body ( 40 ) with a horizontal main surface ( 15 ); Forming a vertical trench ( 19a ) extending from the horizontal main surface ( 15 ) in the semiconductor body ( 40 ) extends; Forming a first dielectric layer ( 7 ) in the vertical trench ( 19a ,); Forming a first conductive region ( 13a ) on the first dielectric layer ( 7 ) in the vertical trench ( 19a ) that the first conductive region ( 13a ) from the horizontal main surface ( 15 ) is withdrawn; Filling the vertical trench ( 19a ,) with a second dielectric layer ( 8th ), which is the first conductive area ( 13a covered); and removing the first dielectric layer ( 7 ) and the second dielectric layer ( 8th ) from an upper portion of the vertical trench ( 19a ) around the semiconductor body on a side wall of the vertical trench ( 19a ), the first conductive region ( 13a ) of the second dielectric layer ( 8th ) remains covered. The method of claim 1, wherein the filling of the vertical trench ( 19a ) by a non-conforming deposition. Method according to claim 1 or 2, wherein the filling of the vertical trench ( 19a ) comprises an HDP process. Method according to one of claims 1 to 3, further comprising removing the first dielectric layer ( 7 ) and the second dielectric layer ( 8th ) from the horizontal surface ( 15 ), including planarizing. The method of claim 4, wherein the planarizing comprises an oxide CMP process. Method according to claim 4 or 5, further comprising forming a first sacrificial layer on the semiconductor body ( 40 ) by thermal oxidation and removal of the first sacrificial layer after planarization. Method according to one of the preceding claims, wherein the removal of the first dielectric layer ( 7 ) and the second dielectric layer ( 8th ) comprises a plasma etching process. The method of claim 7, further comprising forming a second sacrificial layer on the sidewall by thermal oxidation and removing the second sacrificial layer after the plasma etch process. Method according to one of the preceding claims, further comprising selectively etching back the first dielectric layer ( 7 ) before filling the vertical trench ( 19a ). Method according to one of the preceding claims, wherein the first dielectric layer ( 7 ) and / or the second dielectric layer ( 8th ) are formed as silicon oxide. Method according to one of the preceding claims, further comprising forming a silicon nitride layer ( 6 ) on the horizontal main surface ( 15 ). The method of claim 11, wherein the silicon nitride layer ( 6 ) as an etching mask in forming the vertical trench ( 19a ) and / or serves as a stop layer during planarization. Method according to one of the preceding claims, further comprising forming a thin dielectric layer ( 9 ) on the sidewall of the semiconductor body ( 40 ) in the upper portion of the vertical trench ( 19a ). The method of claim 13, further comprising forming a second conductive region ( 14 ) in the upper portion of the vertical trench ( 19a ). The method of claim 13 or 14, further comprising forming a transistor structure in the semiconductor body ( 40 ), whose pn junctions to the thin dielectric layer ( 9 ). Method according to one of the preceding claims, wherein the forming of the first conductive area ( 13a ) and / or the formation of the second conductive region ( 14 ) comprises a respective deposition of polysilicon. Method according to one of the preceding claims, wherein the removal of the first dielectric layer ( 7 ) and the second dielectric layer ( 8th ) from the upper portion of the vertical trench ( 19a ) comprises a common etching process. Method for producing a semiconductor transistor structure ( 100 ), comprising: providing a semiconductor body ( 40 ) with a horizontal main surface ( 15 ); Forming a vertical trench ( 19a ) extending from the horizontal main surface ( 15 ) in the semiconductor body ( 40 ) extends; Forming a field oxide ( 7 ) and a field plate ( 13a ) in a lower portion of the vertical trench ( 19a ); Filling the vertical trench ( 19a ) with a HDP oxide ( 8th ); Plasma etching to the HDP oxide ( 8th ) from an upper portion of the vertical trench ( 19a ) to remove; and, forming an insulated gate electrode ( 14 . 9 ) in the upper portion of the vertical trench ( 19a ). The method of claim 18, wherein the field oxide ( 7 ) after filling the vertical trench ( 19a ) from the upper portion of the vertical trench ( 19a ) is removed to the semiconductor body ( 40 ) on a side wall of the vertical trench ( 19a ) in the upper section. A method according to claim 18 or 19, wherein the field oxide ( 7 ) and / or the HDP oxide ( 8th ) from the horizontal main surface ( 15 ) are removed by planarization before plasma etching.

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