US20080150013A1 - Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer - Google Patents
Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer Download PDFInfo
- Publication number
- US20080150013A1 US20080150013A1 US11/644,344 US64434406A US2008150013A1 US 20080150013 A1 US20080150013 A1 US 20080150013A1 US 64434406 A US64434406 A US 64434406A US 2008150013 A1 US2008150013 A1 US 2008150013A1
- Authority
- US
- United States
- Prior art keywords
- trench
- trenched
- hdp
- filling
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000009413 insulation Methods 0.000 title claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 25
- 229920005591 polysilicon Polymers 0.000 title claims description 25
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 82
- 230000008569 process Effects 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 238000011049 filling Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 238000005137 deposition process Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 23
- 230000008021 deposition Effects 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 15
- 238000000280 densification Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 210000000746 body region Anatomy 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 3
- -1 boron ions Chemical class 0.000 claims description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002028 premature Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Definitions
- the invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for providing the split trench gates with high-density plasma (HDP) deposition oxide layer as the inter-poly oxide layer.
- HDP high-density plasma
- trenched DMOS devices are configured with trenched gates wherein large capacitance (Cgd) between gate and drain limits the device switching speed.
- Cgd capacitance
- the capacitance is mainly generated from the electrical field coupling between the bottom of the trenched gate and the drain.
- an improved split trenched-gate configuration e.g., a Shielded Gate Trench structure (SGT) is introduced with a bottom shielding electrode at the bottom of the trenched gate to shield the trenched gates from the drain.
- SGT Shielded Gate Trench structure
- the design concept of a SGT structure is link the bottom-shielding electrode of the trench to the source such that the trenched gates are shielded from the drain located at the bottom of the substrate as that shown in FIG. 1 .
- a reduction of gate to drain capacitance to about half of the original Cgd value can be achieved by implementing the shielding electrode in the bottom of the trenched gates.
- the switching speed and switching efficiency of the DMOS devices implemented with the SGT structure are therefore greatly improved.
- the bottom-shielding electrode when tied to source potential provides a better shielding effect than a configuration where the bottom-shielding segment is left at a floating potential.
- a reduction of the gate-drain capacitance Cgd is achieved by implementing a bottom poly shielding structure.
- bottom oxide has a greater thickness than the layer gate oxide along the trench sidewalls.
- the net effect is an advantage that for a specific epitaxial thickness, such SGT structure can deliver much higher drain-to-source breakdown voltage (BVdss).
- BVdss drain-to-source breakdown voltage
- a step of carrying out a wet etch of the first gate oxide often causes a problem of gate oxide weakness.
- the oxide etch often extends below the top surface of the first polysilicon that have been first deposited into the bottom part of the trench thus causing the formation of an over-etching pocket.
- the sharp and thin inter-poly oxide causes early breakdown between source and gate due to the problems that 1) the dip leads to electric file concentration in the area that causes premature breakdown; and 2) the dip increases a gate-drain overlay thus the Cgd improvement is compromised.
- Such technical difficulties become a problem when the conventional processes are applied.
- a wet etch process is applied to remove the sidewall oxide that is damaged during first polysilicon etch-back.
- the isotropic wet-etch process inevitably etches off a portion of sidewall oxide slightly below the top surface of poly creating a pocket on the sidewall.
- a thermal oxide is grown conformal to the underlying layer forming the upper trench sidewall gate oxide and inter-poly gate oxide followed by second poly deposition. This technical problem and performance limitation often become even more severe when the cell density is increased due to the shrinking dimension of the trench openings when form the trenched power device in the semiconductor substrate.
- the split trench gate may be formed without compromising the integrity of gate oxide
- this invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell.
- the trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate.
- the trenched gate further includes at least two mutually insulated trench-filling segments with an inter-segment insulation layer that is specially deposited to provide better planar surface characteristics and with controllable inter-segment thickness whereby trench integrity is improved.
- the inter-segment insulation is a HDP deposition layer provided with surface planar characteristics for preventing over-etching through the inter-poly layer.
- This invention further discloses a method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) cell on a semiconductor substrate with split gate separated by an inter-poly insulation layer separating a top and a bottom gate segments.
- the method further includes steps of applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
- MOSFET metal oxide semiconductor field effect transistor
- FIG. 1 is a cross sectional view of a conventional trenched MOSFET device implemented with a trenched gate configured with a conventional split trenched gate trench configuration that shows the uneven etched inter-poly layer.
- FIG. 2 is a cross sectional view of a trenched MOSFET device implemented with split trenched gate with improved inter-poly insulation layer providing improved planar surface characteristics and thicker trench bottom oxide layer of this invention.
- FIGS. 3A to 3I are a serial cross sectional views for describing the manufacturing processes to provide a trenched MOSFET device as shown in FIG. 2 .
- the trenched MOSFET device 100 is supported on a substrate 105 formed with an epitaxial layer 110 .
- the trenched MOSFET device 100 includes a bottom gate segment 130 filled with polysilicon at the bottom portion below a top trenched gate segment 150 .
- the bottom gate segment 130 filled with the polysilicon is shielded and insulated from a top gate segment 150 by an insulation inter-poly layer 140 disposed between the top and bottom segments.
- the bottom trenched-segment is also insulated from the drain disposed below 105 by the insulation layers 120 surrounding the bottom surface of the trenched gate.
- the top trenched gate segment 150 is also filled with a polysilicon layer in the top portion of the trench surrounded with a gate insulation layer 155 covering the trenched walls.
- the inter-poly insulation layer 140 is formed by HDP oxide deposition.
- the HDP deposition of the oxide layer provides a reasonable and sufficient planar top surface for the inter-poly insulation layer 140 .
- the inter-poly oxide layer 140 is annealed at a high temperature from 850 C to 1150 C from few minutes to hours followed by CMP and dry or wet etch to achieve a desired thickness above the bottom polysilicon electrode. Specifically, the problem generated from a dip of the inter-poly insulation layer 140 is now eliminated.
- the dip, i.e., a pocket 158 is now filled with HDP.
- the pocket is generated from an isotropic wet etch process that etches off a portion of the sidewall oxide slightly below the top surface of the polysilicon insulation layer 140 due to the fact that the sidewall oxide is damaged during the first polysilicon etch-back process.
- the P-body regions 160 encompassing a source region 170 doped with the dopant of first conductivity, e.g., N+ dopant.
- the source regions 170 are formed near the top surface of the epitaxial layer surrounding the trenched gates 150 .
- On the top surface of the semiconductor substrate are also insulation layers 175 , contact openings and metal layers 180 for providing electrical contacts to the source-body regions and the gates.
- these structural features are not shown in details and discussed since those of ordinary skill in the art already know these structures.
- FIGS. 3A to 3L for a serial of side cross sectional views to illustrate the fabrication steps of a MOSFET device as that shown in FIG. 2 .
- a hard oxide mask 208 is applied to open a plurality of trenches 209 on an epitaxial layer 210 overlaying a substrate 205 .
- the hard oxide mask 208 is removed and an oxide layer 212 is grown by a thermal oxide process on the sidewall and bottom surface of the trench 209 .
- the oxide layer 212 may be formed by an oxide deposition to improve the thinning situation at the bottom of the trench 209 .
- To further increase the thickness of the bottom oxide as shown in FIG.
- a thermal oxide layer is grown to form the bottom oxide layer then incorporated with a high density plasma (HDP) oxide deposition as an optional processing step.
- HDP high density plasma
- the oxide layer on the trench sidewall and on the top surface of the silicon substrate is removed in order to form a thicker bottom oxide layer 215 , and then a gate oxide layer 220 is grown.
- a non-doped polysilicon 225 is deposited then doped with POCL3 followed by implanting phosphorous or boron ions.
- An annealing process is performed to the polysilicon layer that may be either N-type of P-type doped gate filling material. Alternatively, in-situ doped poly can be deposited to fill the trench.
- a polysilicon etch back is carried out to remove from the top portion of the polysilicon layer 225 until a desired depth is reached.
- the top hard mask oxide layer 208 is partially etched off during poly etch back process.
- an oxide etch process is carried out to completely remove the hard mask layer 208 and the trench sidewall oxide layer 220 over the polysilicon layer 225 causing a dip 258 due to corner over etch as happening in prior art process.
- a HDP oxide 230 is deposited to line the trench sidewall to form the trench gate oxide and the top surface of bottom poly 225 to form the inter poly oxide.
- the nature of HDP oxide deposition provides a thick horizontal oxide layer on the top surface of bottom poly layer 225 that substantially fill in the dip 258 providing a substantial planar inter poly oxide layer without compromising the breakdown.
- a thin vertical HDP oxide will form on the sidewall of trench above poly layer 225 to function as gate oxide.
- a RTP process may be applied to intensify the HDP oxide to improve the quality of oxide layer before continue the process of FIGS. 3G-3J as describe below.
- a prefer embodiment to obtain a better improved inter poly layer oxide can be achieve through the process illustrated by FIGS. 3 E′ and 3 F′ right after the etch back of poly layer 225 of FIG. 3D .
- a HDP oxide 230 is deposited to fill the trench followed by a densification process at an elevated temperature in a N2 of O2/N2 ambient environment to carry out a wet oxidation.
- the condition of annealing is controlled so that the etch rate of HDP oxide 230 after annealing process is increased to be substantial the same as an etch rate of thermal oxide 220 .
- the annealing is carried out to achieve the HDP oxide densification by using N2 1150 C 30 sec RTP right after HDP inter-poly oxide deposition.
- RTP effect showed that Wet etch rate changed from 13 A/sec to 11.5 A/sec that is an 10% etch rate increase.
- Such effect is an indication of oxide densification.
- the densification process enhances the uniformity of the following wet etch process.
- the HDP oxide 230 ′ is dry etched back together with thermal oxide 220 to expose oxide on the top surface followed by a dry or wet-etch process to obtain a desired thickness of inter poly oxide layer 230 .
- CMP chemical-mechanical planarization
- a dry or wet etch process is followed to obtain a desired thickness of the HDP oxide layer 230 .
- the CMP process is optional to further improve the surface characteristics of the HDP surface.
- a unique inter-poly insulation layer with desired inter-poly layer profile characterized by a substantial planar surface is therefore achieved due to the etch rate of HDP oxide has been adjusted to substantially equal to the etch rate of thermal oxide through a precisely controlled RTP anneal process.
- a gate oxide layer 235 is first grown followed by in-situ polysilicon deposition to fill the trench with a polysilicon layer 240 .
- the polysilicon layer 240 is etched back from the top surface of the silicon substrate.
- a body implant is performed followed by a body diffusion to form the body region 245 .
- a source mask (not shown) is applied to carry out a source ion implant followed by a source diffusion to form the source regions 250 .
- a thick oxide layer is remained or grown on top the semiconductor while the second gate poly is deposited and etch back during the process of FIGS.
- the top surface of the second gate poly may be controlled during etch back to a depth that is that is just below the thick oxide layer but higher than the top surface of silicon substrate resulting a device as shown in FIG. 3J with high poly gate guaranteeing overlap with the source region even the source is shallow.
- the remainder of the processes includes standard processing steps. The process is followed by the deposition of PSG or BPSG passivation layer over the top surface. Then a contact opening etch is carried out to open the source contact opening and gate contact opening (not shown) through the passivation layer after the passivation layer is panelized by high temperature flow. Then, a contact metal layer is deposited over the top surface followed by standard etch process to pattern the contact metal into source metal and gate pad (not shown). For the sake of clarity, these standard processes are not specifically described in details since these processes are well known among those of ordinary skill in the art.
- the MOSFET device as described above thus provides a device structure and configuration where the inter-poly insulation has much improved and controllable thickness and surface profile.
- the first gate electrode at the bottom surface has a thick trench bottom oxide.
- the inter-poly insulation formed by HDP oxide deposition have reasonable and sufficient planar top surface.
- the inter-poly oxide layer is annealed at a high temperature from 850 C to 1150 C from few minutes to hours followed by CMP and dry or wet etch to achieve a desired thickness above the bottom polysilicon electrode.
- the quality and performance of the trenched gates are significantly improved because the well controlled and improved planar characteristics of the inter-poly oxide layer.
- a well-controlled inter-poly uniformity and thickness thus improve the control capacitance and the breakdown between source and gate.
- Such process window control is one of the key parameter to determine the success of this new technology with the shielded gate structure for device performance improvements.
- this invention further discloses a method for manufacturing a trenched semiconductor power device by opening a trench in a semiconductor substrate.
- the method further includes a step of filling the trench with a trenching filling material followed by an etch-back process to remove from a top portion of the trench until a desired depth is reached.
- the method further includes a step of depositing a high-density plasma (HDP) oxide layer followed by an annealing densification process at an elevated temperature for increasing an etch rate of the HDP oxide layer to be substantially the same as an etch rate of a thermal oxide.
- HDP high-density plasma
- the step of annealing densification process further includes a step of carrying out the annealing densification process in a N2 of O2/N2 ambient environment to carry out a wet oxidation.
- the step of annealing densification process further includes a precisely controlled RTP anneal process whereby the HDP oxide layer having substantially a same etch rate as an etch rate of a thermal oxide.
- the method further includes a step of dry etching back the HDP oxide layer to expose the HDP oxide layer followed by a dry or wet-etch to obtain a desired HDP oxide layer thickness.
- the method further includes a step of applying a chemical-mechanical planarization (CMP) process on the HDP oxide layer.
- CMP chemical-mechanical planarization
- the step of filling the trench with a trench filling material further includes a step of filling the trench with an un-doped polysilicon then doping the polysilicon with POCL3 followed by implanting phosphorous or boron ions.
- the step of etching back to remove the trench filling material from a top portion of the trench further forming an over-etching pocket along sidewalls of the trench near a top portion of a bottom portion of the trench-filling material.
- the step of depositing a high-density plasma (HDP) oxide layer further includes a step of filling the over-etching pocket for improving a device ruggedness of the semiconductor power device.
- the method further includes a step of filling the trench on top of the inter-segment insulation layer to form at least two mutually insulated trench-filling segments constituting a split gate for the semiconductor device.
- the method further includes a step of implanting a source region surrounding the split gate and impaling a body region encompassing the source region for manufacturing the semiconductor power device as a trenched metal oxide semiconductor field effect transistor (MOSFET) device.
- MOSFET metal oxide semiconductor field effect transistor
- This invention further discloses a method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer separating a top and a bottom gate segments.
- the method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
Abstract
This invention discloses method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
Description
- 1. Field of the Invention
- The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for providing the split trench gates with high-density plasma (HDP) deposition oxide layer as the inter-poly oxide layer.
- 2. Description of the Prior Art
- Conventional technologies for reducing the gate to drain capacitance Cgd in a DMOS device by employing the split trenched-gate, e.g., shielded gate trench (SGT) structure, are still confronted with technical limitations and difficulties. Specifically, trenched DMOS devices are configured with trenched gates wherein large capacitance (Cgd) between gate and drain limits the device switching speed. The capacitance is mainly generated from the electrical field coupling between the bottom of the trenched gate and the drain. In order to reduce the gate to drain capacitance, an improved split trenched-gate configuration, e.g., a Shielded Gate Trench structure (SGT), is introduced with a bottom shielding electrode at the bottom of the trenched gate to shield the trenched gates from the drain. The design concept of a SGT structure is link the bottom-shielding electrode of the trench to the source such that the trenched gates are shielded from the drain located at the bottom of the substrate as that shown in
FIG. 1 . A reduction of gate to drain capacitance to about half of the original Cgd value can be achieved by implementing the shielding electrode in the bottom of the trenched gates. The switching speed and switching efficiency of the DMOS devices implemented with the SGT structure are therefore greatly improved. The bottom-shielding electrode when tied to source potential provides a better shielding effect than a configuration where the bottom-shielding segment is left at a floating potential. A reduction of the gate-drain capacitance Cgd is achieved by implementing a bottom poly shielding structure. The problem of break down from trench bottom is eliminated since bottom oxide has a greater thickness than the layer gate oxide along the trench sidewalls. The net effect is an advantage that for a specific epitaxial thickness, such SGT structure can deliver much higher drain-to-source breakdown voltage (BVdss). Once the BVdss is not a limiting design consideration, the designer has the flexibilities to either increase the doping level or reduce thickness of the epitaxial layer, or to design a device that may accomplish both in order to improve the overall device performance. - However, as shown in
FIG. 1 , in the manufacturing process, a step of carrying out a wet etch of the first gate oxide often causes a problem of gate oxide weakness. The oxide etch often extends below the top surface of the first polysilicon that have been first deposited into the bottom part of the trench thus causing the formation of an over-etching pocket. Specifically, the sharp and thin inter-poly oxide causes early breakdown between source and gate due to the problems that 1) the dip leads to electric file concentration in the area that causes premature breakdown; and 2) the dip increases a gate-drain overlay thus the Cgd improvement is compromised. Such technical difficulties become a problem when the conventional processes are applied. When applying a conventional manufacturing process, a wet etch process is applied to remove the sidewall oxide that is damaged during first polysilicon etch-back. The isotropic wet-etch process inevitably etches off a portion of sidewall oxide slightly below the top surface of poly creating a pocket on the sidewall. A thermal oxide is grown conformal to the underlying layer forming the upper trench sidewall gate oxide and inter-poly gate oxide followed by second poly deposition. This technical problem and performance limitation often become even more severe when the cell density is increased due to the shrinking dimension of the trench openings when form the trenched power device in the semiconductor substrate. - Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the power devices such that the above discussed problems and limitations can be resolved.
- It is therefore an object of the present invention to provide a new and improved semiconductor power device implemented with the split trenched gates where the inter-poly insulation layer is formed with a HDP deposition process with improved planar surface characteristics followed by annealing process in order to overcome the above discussed technical difficulties and limitations.
- Specifically, it is an object of the present invention to provide improved device configuration and manufacturing method to reduce the gate to drain capacitance while accurately control the thickness of the inter-poly layer by depositing a HDP oxide insulation layer on top of the bottom trench polysilicon then applied a controlled etch to accurately etch off a desired layer thickness of the inter-poly insulation such that the depth above the bottom trench poly can be better controlled. With this new structure and the method to fine-tune the inter-poly oxide thickness between the 2nd oxide separately, the split trench gate may be formed without compromising the integrity of gate oxide
- Briefly in a preferred embodiment this invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments with an inter-segment insulation layer that is specially deposited to provide better planar surface characteristics and with controllable inter-segment thickness whereby trench integrity is improved. In a preferred embodiment, the inter-segment insulation is a HDP deposition layer provided with surface planar characteristics for preventing over-etching through the inter-poly layer.
- This invention further discloses a method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) cell on a semiconductor substrate with split gate separated by an inter-poly insulation layer separating a top and a bottom gate segments. The method further includes steps of applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
- These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.
-
FIG. 1 is a cross sectional view of a conventional trenched MOSFET device implemented with a trenched gate configured with a conventional split trenched gate trench configuration that shows the uneven etched inter-poly layer. -
FIG. 2 is a cross sectional view of a trenched MOSFET device implemented with split trenched gate with improved inter-poly insulation layer providing improved planar surface characteristics and thicker trench bottom oxide layer of this invention. -
FIGS. 3A to 3I are a serial cross sectional views for describing the manufacturing processes to provide a trenched MOSFET device as shown inFIG. 2 . - Referring to
FIG. 2 for a cross sectional view of a trenchedMOSFET device 100 of this invention. The trenchedMOSFET device 100 is supported on asubstrate 105 formed with anepitaxial layer 110. The trenchedMOSFET device 100 includes abottom gate segment 130 filled with polysilicon at the bottom portion below a top trenchedgate segment 150. Thebottom gate segment 130 filled with the polysilicon is shielded and insulated from atop gate segment 150 by an insulation inter-polylayer 140 disposed between the top and bottom segments. The bottom trenched-segment is also insulated from the drain disposed below 105 by theinsulation layers 120 surrounding the bottom surface of the trenched gate. The top trenchedgate segment 150 is also filled with a polysilicon layer in the top portion of the trench surrounded with agate insulation layer 155 covering the trenched walls. Theinter-poly insulation layer 140 is formed by HDP oxide deposition. The HDP deposition of the oxide layer provides a reasonable and sufficient planar top surface for theinter-poly insulation layer 140. Furthermore, theinter-poly oxide layer 140 is annealed at a high temperature from 850 C to 1150 C from few minutes to hours followed by CMP and dry or wet etch to achieve a desired thickness above the bottom polysilicon electrode. Specifically, the problem generated from a dip of theinter-poly insulation layer 140 is now eliminated. The dip, i.e., apocket 158 is now filled with HDP. The pocket is generated from an isotropic wet etch process that etches off a portion of the sidewall oxide slightly below the top surface of thepolysilicon insulation layer 140 due to the fact that the sidewall oxide is damaged during the first polysilicon etch-back process. Once thepocket 158 is now filled with the HDP, the difficulties of premature breakdown and Cgd compromise are therefore resolved. - A
body region 160 that is doped with a dopant of second conductivity type, e.g., P-type dopant, extends between thetrenched gates 150. The P-body regions 160 encompassing asource region 170 doped with the dopant of first conductivity, e.g., N+ dopant. Thesource regions 170 are formed near the top surface of the epitaxial layer surrounding thetrenched gates 150. On the top surface of the semiconductor substrate are alsoinsulation layers 175, contact openings andmetal layers 180 for providing electrical contacts to the source-body regions and the gates. For the sake of brevity, these structural features are not shown in details and discussed since those of ordinary skill in the art already know these structures. - Referring to
FIGS. 3A to 3L for a serial of side cross sectional views to illustrate the fabrication steps of a MOSFET device as that shown inFIG. 2 . InFIG. 3A , ahard oxide mask 208 is applied to open a plurality oftrenches 209 on anepitaxial layer 210 overlaying asubstrate 205. InFIG. 3B , thehard oxide mask 208 is removed and anoxide layer 212 is grown by a thermal oxide process on the sidewall and bottom surface of thetrench 209. Theoxide layer 212 may be formed by an oxide deposition to improve the thinning situation at the bottom of thetrench 209. To further increase the thickness of the bottom oxide, as shown inFIG. 3C , a thermal oxide layer is grown to form the bottom oxide layer then incorporated with a high density plasma (HDP) oxide deposition as an optional processing step. The oxide layer on the trench sidewall and on the top surface of the silicon substrate is removed in order to form a thickerbottom oxide layer 215, and then agate oxide layer 220 is grown. - In
FIG. 3D , anon-doped polysilicon 225 is deposited then doped with POCL3 followed by implanting phosphorous or boron ions. An annealing process is performed to the polysilicon layer that may be either N-type of P-type doped gate filling material. Alternatively, in-situ doped poly can be deposited to fill the trench. A polysilicon etch back is carried out to remove from the top portion of thepolysilicon layer 225 until a desired depth is reached. The top hardmask oxide layer 208 is partially etched off during poly etch back process. InFIG. 3E , an oxide etch process is carried out to completely remove thehard mask layer 208 and the trenchsidewall oxide layer 220 over thepolysilicon layer 225 causing adip 258 due to corner over etch as happening in prior art process. InFIG. 3F , aHDP oxide 230 is deposited to line the trench sidewall to form the trench gate oxide and the top surface ofbottom poly 225 to form the inter poly oxide. During this process, the nature of HDP oxide deposition provides a thick horizontal oxide layer on the top surface ofbottom poly layer 225 that substantially fill in thedip 258 providing a substantial planar inter poly oxide layer without compromising the breakdown. At the same time a thin vertical HDP oxide will form on the sidewall of trench abovepoly layer 225 to function as gate oxide. A RTP process may be applied to intensify the HDP oxide to improve the quality of oxide layer before continue the process ofFIGS. 3G-3J as describe below. - A prefer embodiment to obtain a better improved inter poly layer oxide can be achieve through the process illustrated by FIGS. 3E′ and 3F′ right after the etch back of
poly layer 225 ofFIG. 3D . As shown in FIG. 3E′, aHDP oxide 230 is deposited to fill the trench followed by a densification process at an elevated temperature in a N2 of O2/N2 ambient environment to carry out a wet oxidation. The condition of annealing is controlled so that the etch rate ofHDP oxide 230 after annealing process is increased to be substantial the same as an etch rate ofthermal oxide 220. In one embodiment, the annealing is carried out to achieve the HDP oxide densification by using N2 1150 C 30 sec RTP right after HDP inter-poly oxide deposition. Such RTP effect showed that Wet etch rate changed from 13 A/sec to 11.5 A/sec that is an 10% etch rate increase. Such effect is an indication of oxide densification. The densification process enhances the uniformity of the following wet etch process. In FIG. 3F′, theHDP oxide 230′ is dry etched back together withthermal oxide 220 to expose oxide on the top surface followed by a dry or wet-etch process to obtain a desired thickness of interpoly oxide layer 230. Alternatively a chemical-mechanical planarization (CMP) process may be first performed on top of the surface of theHDP oxide layer 230 to provide a planar surface then a dry or wet etch process is followed to obtain a desired thickness of theHDP oxide layer 230. The CMP process is optional to further improve the surface characteristics of the HDP surface. A unique inter-poly insulation layer with desired inter-poly layer profile characterized by a substantial planar surface is therefore achieved due to the etch rate of HDP oxide has been adjusted to substantially equal to the etch rate of thermal oxide through a precisely controlled RTP anneal process. - In
FIG. 3G , agate oxide layer 235 is first grown followed by in-situ polysilicon deposition to fill the trench with apolysilicon layer 240. InFIG. 3H , thepolysilicon layer 240 is etched back from the top surface of the silicon substrate. InFIG. 3I , a body implant is performed followed by a body diffusion to form thebody region 245. Then a source mask (not shown) is applied to carry out a source ion implant followed by a source diffusion to form thesource regions 250. In the case when a thick oxide layer is remained or grown on top the semiconductor while the second gate poly is deposited and etch back during the process ofFIGS. 3G and 3H , the top surface of the second gate poly may be controlled during etch back to a depth that is that is just below the thick oxide layer but higher than the top surface of silicon substrate resulting a device as shown inFIG. 3J with high poly gate guaranteeing overlap with the source region even the source is shallow. The remainder of the processes includes standard processing steps. The process is followed by the deposition of PSG or BPSG passivation layer over the top surface. Then a contact opening etch is carried out to open the source contact opening and gate contact opening (not shown) through the passivation layer after the passivation layer is panelized by high temperature flow. Then, a contact metal layer is deposited over the top surface followed by standard etch process to pattern the contact metal into source metal and gate pad (not shown). For the sake of clarity, these standard processes are not specifically described in details since these processes are well known among those of ordinary skill in the art. - The MOSFET device as described above thus provides a device structure and configuration where the inter-poly insulation has much improved and controllable thickness and surface profile. Specifically, the first gate electrode at the bottom surface has a thick trench bottom oxide. The inter-poly insulation formed by HDP oxide deposition have reasonable and sufficient planar top surface. Furthermore, the inter-poly oxide layer is annealed at a high temperature from 850 C to 1150 C from few minutes to hours followed by CMP and dry or wet etch to achieve a desired thickness above the bottom polysilicon electrode. The quality and performance of the trenched gates are significantly improved because the well controlled and improved planar characteristics of the inter-poly oxide layer. A well-controlled inter-poly uniformity and thickness thus improve the control capacitance and the breakdown between source and gate. Such process window control is one of the key parameter to determine the success of this new technology with the shielded gate structure for device performance improvements.
- According to above descriptions, this invention further discloses a method for manufacturing a trenched semiconductor power device by opening a trench in a semiconductor substrate. The method further includes a step of filling the trench with a trenching filling material followed by an etch-back process to remove from a top portion of the trench until a desired depth is reached. The method further includes a step of depositing a high-density plasma (HDP) oxide layer followed by an annealing densification process at an elevated temperature for increasing an etch rate of the HDP oxide layer to be substantially the same as an etch rate of a thermal oxide. The step of annealing densification process further includes a step of carrying out the annealing densification process in a N2 of O2/N2 ambient environment to carry out a wet oxidation. In an exemplary embodiment, the step of annealing densification process further includes a precisely controlled RTP anneal process whereby the HDP oxide layer having substantially a same etch rate as an etch rate of a thermal oxide. In an exemplary embodiment, the method further includes a step of dry etching back the HDP oxide layer to expose the HDP oxide layer followed by a dry or wet-etch to obtain a desired HDP oxide layer thickness. In an exemplary embodiment, the method further includes a step of applying a chemical-mechanical planarization (CMP) process on the HDP oxide layer. In an exemplary embodiment, the step of filling the trench with a trench filling material further includes a step of filling the trench with an un-doped polysilicon then doping the polysilicon with POCL3 followed by implanting phosphorous or boron ions. In an exemplary embodiment, the step of etching back to remove the trench filling material from a top portion of the trench further forming an over-etching pocket along sidewalls of the trench near a top portion of a bottom portion of the trench-filling material. And, the step of depositing a high-density plasma (HDP) oxide layer further includes a step of filling the over-etching pocket for improving a device ruggedness of the semiconductor power device. In an exemplary embodiment, the method further includes a step of filling the trench on top of the inter-segment insulation layer to form at least two mutually insulated trench-filling segments constituting a split gate for the semiconductor device. In an exemplary embodiment, the method further includes a step of implanting a source region surrounding the split gate and impaling a body region encompassing the source region for manufacturing the semiconductor power device as a trenched metal oxide semiconductor field effect transistor (MOSFET) device.
- This invention further discloses a method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer separating a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
- Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.
Claims (25)
1. A trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein:
said trenched gate further includes at least two mutually insulated trench-filling segments with an inter-segment insulation layer filling an over-etching pocket along sidewalls of said trenched gate surrounding a top portion of said bottom trench-filling segment thus preventing a top trench-filling segment to extend into said over-etching pocket.
2. The trenched semiconductor power device of claim 1 further comprising:
said inter-segment insulation layer is substantially thicker than a gate insulation layer disposed on trench sidewalls surrounding a top trench-filling segment.
3. The trenched semiconductor power device of claim 2 further comprising:
said inter-segment insulation layer and said gate insulation layer further comprising a continuous high density plasma (HDP) deposition layer
4. The trenched semiconductor power device of claim 2 further comprising:
said inter-segment insulation layer further comprising a HDP deposition layer with an etching rate substantially equal to the etching rate of a thermal oxide.
5. The trenched semiconductor power device of claim 2 further comprising:
said inter-segment insulation layer is a HDP deposition layer processed by an anneal operation at a temperature substantially above a temperature of 800 degrees Celsius.
6. The trenched semiconductor power device of claim 2 further comprising:
said inter-segment insulation layer is a HDP deposition layer processed by an anneal operation followed by an chemistry-mechanical planarization (CMP) and an etch process to provide a planarized surface of said HDP deposition layer.
7. The trenched semiconductor power device of claim 2 wherein:
said trench-filling segments further comprising polysilicon segments.
8. The trenched semiconductor power device of claim 7 wherein:
said top trench-filling segments further comprising polysilicon segments with top surface higher than a top surface of said source region.
9. The trenched semiconductor power device of claim 2 wherein:
said trenched gate further comprising an insulation layer disposed on sidewalls and bottom surface of said trench as an insulating padding layer for said trench-filling segments.
10. The trenched semiconductor power device of claim 2 wherein:
said trenched gate further comprising an insulation layer disposed on sidewalls and bottom surface of said trench as an insulating padding layer for said trench-filling segments wherein said insulation layer disposed on the bottom surface of said trench is substantially thicker than said insulation layer disposed on said sidewalls of said trench.
11. The trenched semiconductor power device of claim 1 wherein:
said trench-filling segment below said inter-segment insulation layer constituting an electrode for electrically connected to said source region of said MOSFET device.
12. The trenched semiconductor power device of claim 1 wherein:
said trenched semiconductor power device constituting a N-channel metal oxide semiconductor field effect transistor (MOSFET) device.
13. The trenched semiconductor power device of claim 1 wherein:
said trenched semiconductor power device constituting a P-channel MOSFET device.
14. A method for manufacturing a trenched semiconductor power device comprising step of opening a trench in a semiconductor substrate and said method further comprising:
filling said trench with a trenching filling material followed by an etch back process to remove from a top portion of said trench until a desired depth is reached; and
depositing a high density plasma (HDP) oxide layer followed by an annealing densification process at an elevated temperature for increasing an etch rate of said HDP oxide layer to be substantially the same as an etch rate of a thermal oxide.
15. The method of claim 14 wherein:
said step of annealing densification process further comprising a step of carrying out said annealing densification process in a N2 of O2/N2 ambient environment to carry out a wet oxidation.
16. The method of claim 14 wherein:
said step of annealing densification process further comprising a step of carrying out said annealing densification process in a N2 of O2/N2 ambient environment at a temperature above 850 degrees Celsius for approximately 30 seconds to carry out a RTP process.
17. The method of claim 14 wherein:
said step of annealing densification process further comprising a precisely controlled RTP anneal process whereby said HDP oxide layer having substantially a same etch rate as an etch rate of a thermal oxide.
18. The method of claim 14 further comprising:
dry etching back said HDP oxide layer to expose said HDP oxide layer followed by a dry or wet-etch to obtain a desired HDP oxide layer thickness.
19. The method of claim 17 further comprising:
applying a chemical-mechanical planarization (CMP) process on said HDP oxide layer.
20. The method of claim 14 wherein:
said step of filling said trench with a trench filling material further comprising a step of filling said trench with an un-doped polysilicon then doping said polysilicon with POCL3 followed by implanting phosphorous or boron ions.
21. The method of claim 14 wherein:
said step of etching back to remove said trench filling material from a top portion of said trench further forming an over-etching pocket along sidewalls of said trench near a top portion of a bottom portion of said trench-filling material; and
said step of depositing a high density plasma (HDP) oxide layer further comprising a step of filling said over-etching pocket for improving a device ruggedness of said semiconductor power device.
22. The method of claim 14 further comprising:
filling said trench on top of said inter-segment insulation layer to form at least two mutually insulated trench-filling segments constituting a split gate for said semiconductor device.
23. The method of claim 22 further comprising:
implanting a source region surrounding said split gate and impaling a body region encompassing said source region for manufacturing said semiconductor power device as a trenched metal oxide semiconductor field effect transistor (MOSFET) device.
24. The method of claim 14 further comprising:
growing a thermal oxide layer along a bottom and sidewall of said trench; depositing a HDP oxide layer overlaying said thermal oxide layer; removing oxide layers along trench sidewall; re-growing a thermal oxide layer along said trench sidewall whereas said thermal oxide layer along side trench sidewall is thinner than said HDP oxide layer at said trench bottom.
25. A method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer separating a top and a bottom gate segments, the method further comprising:
forming said inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/644,344 US20080150013A1 (en) | 2006-12-22 | 2006-12-22 | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
TW096148823A TWI359504B (en) | 2006-12-22 | 2007-12-19 | Split gate formation with high density plasma (hdp |
CNA2007103022464A CN101207154A (en) | 2006-12-22 | 2007-12-20 | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
US12/589,045 US8053315B2 (en) | 2006-12-22 | 2009-10-16 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/644,344 US20080150013A1 (en) | 2006-12-22 | 2006-12-22 | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/589,045 Division US8053315B2 (en) | 2006-12-22 | 2009-10-16 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080150013A1 true US20080150013A1 (en) | 2008-06-26 |
Family
ID=39541590
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/644,344 Abandoned US20080150013A1 (en) | 2006-12-22 | 2006-12-22 | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
US12/589,045 Active US8053315B2 (en) | 2006-12-22 | 2009-10-16 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/589,045 Active US8053315B2 (en) | 2006-12-22 | 2009-10-16 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer |
Country Status (3)
Country | Link |
---|---|
US (2) | US20080150013A1 (en) |
CN (1) | CN101207154A (en) |
TW (1) | TWI359504B (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100078718A1 (en) * | 2008-09-30 | 2010-04-01 | Infineon Technologies Austria Ag | Semiconductor device and methods for producing a semiconductor device |
US20110095361A1 (en) * | 2009-10-26 | 2011-04-28 | Alpha & Omega Semiconductor, Inc. | Multiple layer barrier metal for device component formed in contact trench |
US20130228860A1 (en) * | 2010-03-11 | 2013-09-05 | Hong Chang | Shielded gate trench mos with improved source pickup layout |
CN104916544A (en) * | 2015-04-17 | 2015-09-16 | 苏州东微半导体有限公司 | Manufacturing method of groove type split-gate power device |
EP3637457A1 (en) * | 2018-10-09 | 2020-04-15 | Infineon Technologies Austria AG | Transistor device and method for forming a recess for a trench gate electrode |
CN111128706A (en) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Manufacturing method of field oxide with gradually-changed thickness in groove and manufacturing method of SGT (super-stable Gate Bipolar transistor) device |
CN112233983A (en) * | 2020-10-27 | 2021-01-15 | 上海华虹宏力半导体制造有限公司 | Trench gate power device and preparation method thereof |
US20210074853A1 (en) * | 2018-06-28 | 2021-03-11 | Huawei Technologies Co., Ltd. | Semiconductor Device and Manufacturing Method |
CN113035715A (en) * | 2019-12-25 | 2021-06-25 | 华润微电子(重庆)有限公司 | Shielded gate trench field effect transistor and method of making same |
CN115602541A (en) * | 2021-10-11 | 2023-01-13 | 和舰芯片制造(苏州)股份有限公司(Cn) | Preparation method of wafer with trench gate and wafer |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8427069B2 (en) * | 2009-06-22 | 2013-04-23 | Polar Semiconductor, Inc. | Current-regulated power supply with soft-start protection |
US8314471B2 (en) * | 2009-11-17 | 2012-11-20 | Diodes Incorporated | Trench devices having improved breakdown voltages and method for manufacturing same |
KR101061296B1 (en) * | 2010-07-01 | 2011-08-31 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
CN102403353B (en) * | 2010-09-14 | 2013-08-14 | 力士科技股份有限公司 | Trench metal oxide semiconductor field-effect transistor and manufacturing method for same |
CN102994974A (en) * | 2011-09-09 | 2013-03-27 | 上海华虹Nec电子有限公司 | Manufacturing method of thick oxide film |
US8669170B2 (en) | 2012-01-16 | 2014-03-11 | Globalfoundries Inc. | Methods of reducing gate leakage |
US8697520B2 (en) | 2012-03-02 | 2014-04-15 | Alpha & Omega Semiconductor Incorporationed | Method of forming an asymmetric poly gate for optimum termination design in trench power MOSFETS |
KR101828495B1 (en) | 2013-03-27 | 2018-02-12 | 삼성전자주식회사 | Semiconductor Devices Having a Planar Source Electrode |
KR101934893B1 (en) * | 2013-03-27 | 2019-01-03 | 삼성전자 주식회사 | Method of Fabricating a Semiconductor Device Having a Grooved Source Contact Region |
CN104701148B (en) * | 2013-12-04 | 2017-11-24 | 和舰科技(苏州)有限公司 | The manufacture method of splitting bar |
CN106098777A (en) * | 2016-06-22 | 2016-11-09 | 电子科技大学 | A kind of splitting bar accumulation type DMOS device |
CN107785263B (en) * | 2016-08-26 | 2020-09-04 | 台湾半导体股份有限公司 | Field effect transistor with multiple width electrode structure and its manufacturing method |
CN106298945A (en) * | 2016-09-30 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Shield grid trench MOSFET process |
CN107421655B (en) * | 2017-07-05 | 2020-02-21 | 中国科学院苏州生物医学工程技术研究所 | Even-order Lamb wave generating device and temperature detection system |
KR102358460B1 (en) | 2017-08-10 | 2022-02-07 | 삼성전자주식회사 | Semiconductor memory device and method of forming the same |
CN107492486A (en) * | 2017-08-15 | 2017-12-19 | 上海华虹宏力半导体制造有限公司 | The process of groove type double-layer grid MOS dielectric layers |
JP7085352B2 (en) * | 2018-01-15 | 2022-06-16 | 株式会社ジャパンディスプレイ | Display device |
US10510878B1 (en) * | 2018-06-13 | 2019-12-17 | Vanguard International Semiconductor Corporation | Semiconductor devices and methods for forming the same |
US11289596B2 (en) * | 2019-02-25 | 2022-03-29 | Maxpower Semiconductor, Inc. | Split gate power device and its method of fabrication |
CN110896026A (en) * | 2019-11-22 | 2020-03-20 | 矽力杰半导体技术(杭州)有限公司 | Trench type MOSFET structure and manufacturing method thereof |
CN113035951A (en) * | 2019-12-25 | 2021-06-25 | 株洲中车时代半导体有限公司 | MOSFET structure and preparation method and application thereof |
CN111489962B (en) * | 2020-04-17 | 2023-09-26 | 重庆伟特森电子科技有限公司 | Preparation method of thick bottom groove |
CN112133627B (en) * | 2020-09-29 | 2022-06-17 | 上海华虹宏力半导体制造有限公司 | Process for shielded gate trench device |
CN113013027A (en) * | 2021-03-24 | 2021-06-22 | 上海华虹宏力半导体制造有限公司 | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device |
CN113013028A (en) * | 2021-03-24 | 2021-06-22 | 上海华虹宏力半导体制造有限公司 | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device |
CN115148796A (en) * | 2021-03-30 | 2022-10-04 | 无锡华润上华科技有限公司 | Semiconductor device with split gate structure and method of manufacturing the same |
CN113192839A (en) * | 2021-04-27 | 2021-07-30 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
CN113471292B (en) * | 2021-07-02 | 2023-10-24 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
TWI809577B (en) * | 2021-11-26 | 2023-07-21 | 帥群微電子股份有限公司 | Trench power semiconductor device and method of manufacturing the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050145934A1 (en) * | 2002-08-23 | 2005-07-07 | Kocon Christopher B. | Method for improved MOS gating to reduce miller capacitance and switching losses |
US20070221952A1 (en) * | 2006-03-24 | 2007-09-27 | Paul Thorup | High density trench FET with integrated Schottky diode and method of manufacture |
US7319256B1 (en) * | 2006-06-19 | 2008-01-15 | Fairchild Semiconductor Corporation | Shielded gate trench FET with the shield and gate electrodes being connected together |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7345342B2 (en) | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US6787409B2 (en) | 2002-11-26 | 2004-09-07 | Mosel Vitelic, Inc. | Method of forming trench isolation without grooving |
KR100674971B1 (en) * | 2005-04-27 | 2007-01-26 | 삼성전자주식회사 | Method of fabricating flash memory with U type floating gate |
US7691722B2 (en) * | 2006-03-14 | 2010-04-06 | Micron Technology, Inc. | Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability |
-
2006
- 2006-12-22 US US11/644,344 patent/US20080150013A1/en not_active Abandoned
-
2007
- 2007-12-19 TW TW096148823A patent/TWI359504B/en active
- 2007-12-20 CN CNA2007103022464A patent/CN101207154A/en active Pending
-
2009
- 2009-10-16 US US12/589,045 patent/US8053315B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050145934A1 (en) * | 2002-08-23 | 2005-07-07 | Kocon Christopher B. | Method for improved MOS gating to reduce miller capacitance and switching losses |
US20070221952A1 (en) * | 2006-03-24 | 2007-09-27 | Paul Thorup | High density trench FET with integrated Schottky diode and method of manufacture |
US7319256B1 (en) * | 2006-06-19 | 2008-01-15 | Fairchild Semiconductor Corporation | Shielded gate trench FET with the shield and gate electrodes being connected together |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8796764B2 (en) * | 2008-09-30 | 2014-08-05 | Infineon Technologies Austria Ag | Semiconductor device comprising trench gate and buried source electrodes |
US20100078718A1 (en) * | 2008-09-30 | 2010-04-01 | Infineon Technologies Austria Ag | Semiconductor device and methods for producing a semiconductor device |
US20110095361A1 (en) * | 2009-10-26 | 2011-04-28 | Alpha & Omega Semiconductor, Inc. | Multiple layer barrier metal for device component formed in contact trench |
US8138605B2 (en) | 2009-10-26 | 2012-03-20 | Alpha & Omega Semiconductor, Inc. | Multiple layer barrier metal for device component formed in contact trench |
US8580676B2 (en) | 2009-10-26 | 2013-11-12 | Alpha And Omega Semiconductor Incorporated | Multiple layer barrier metal for device component formed in contact trench |
US9252265B2 (en) | 2010-03-11 | 2016-02-02 | Alpha And Omega Semiconductor Incorporated | Shielded gate trench MOS with improved source pickup layout |
US8994101B2 (en) * | 2010-03-11 | 2015-03-31 | Alpha And Omega Semiconductor Incorporated | Shielded gate trench MOS with improved source pickup layout |
US20130228860A1 (en) * | 2010-03-11 | 2013-09-05 | Hong Chang | Shielded gate trench mos with improved source pickup layout |
CN104916544A (en) * | 2015-04-17 | 2015-09-16 | 苏州东微半导体有限公司 | Manufacturing method of groove type split-gate power device |
US20210074853A1 (en) * | 2018-06-28 | 2021-03-11 | Huawei Technologies Co., Ltd. | Semiconductor Device and Manufacturing Method |
EP3637457A1 (en) * | 2018-10-09 | 2020-04-15 | Infineon Technologies Austria AG | Transistor device and method for forming a recess for a trench gate electrode |
CN111029257A (en) * | 2018-10-09 | 2020-04-17 | 英飞凌科技奥地利有限公司 | Transistor device and method for forming recess for trench gate electrode |
CN113035715A (en) * | 2019-12-25 | 2021-06-25 | 华润微电子(重庆)有限公司 | Shielded gate trench field effect transistor and method of making same |
CN111128706A (en) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Manufacturing method of field oxide with gradually-changed thickness in groove and manufacturing method of SGT (super-stable Gate Bipolar transistor) device |
CN112233983A (en) * | 2020-10-27 | 2021-01-15 | 上海华虹宏力半导体制造有限公司 | Trench gate power device and preparation method thereof |
CN115602541A (en) * | 2021-10-11 | 2023-01-13 | 和舰芯片制造(苏州)股份有限公司(Cn) | Preparation method of wafer with trench gate and wafer |
Also Published As
Publication number | Publication date |
---|---|
TWI359504B (en) | 2012-03-01 |
CN101207154A (en) | 2008-06-25 |
US20100099230A1 (en) | 2010-04-22 |
US8053315B2 (en) | 2011-11-08 |
TW200832707A (en) | 2008-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8053315B2 (en) | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer | |
US9865694B2 (en) | Split-gate trench power mosfet with protected shield oxide | |
US20080296673A1 (en) | Double gate manufactured with locos techniques | |
US7932148B2 (en) | Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) | |
US8524558B2 (en) | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET | |
US9673289B2 (en) | Dual oxide trench gate power MOSFET using oxide filled trench | |
TWI398000B (en) | Shielded gate trench (sgt) mosfet devices and manufacturing processes | |
US9000514B2 (en) | Fabrication of trench DMOS device having thick bottom shielding oxide | |
US8643092B2 (en) | Shielded trench MOSFET with multiple trenched floating gates as termination | |
TWI417963B (en) | Structure and method for forming inter-poly dielectric in a shielded gate field effect transistor | |
US20170125531A9 (en) | Thicker bottom oxide for reduced miller capacitance in trench metal oxide semiconductor field effect transistor (mosfet) | |
US20090085107A1 (en) | Trench MOSFET with thick bottom oxide tub | |
CN103545368A (en) | Trench gate MOSFET | |
US9431495B2 (en) | Method of forming SGT MOSFETs with improved termination breakdown voltage | |
US20110254071A1 (en) | Shielded trench mosfet with multiple trenched floating gates as termination | |
US9786766B2 (en) | Methods of fabricating transistors with a protection layer to improve the insulation between a gate electrode and a junction region | |
CN110957357B (en) | Manufacturing method of shielded gate type metal oxide semiconductor field effect transistor | |
CN114639608A (en) | Depletion type trench transistor and forming method thereof | |
CN217062020U (en) | Depletion type trench transistor | |
KR102444384B1 (en) | Trench power MOSFET and manufacturing method thereof | |
US20230268421A1 (en) | Method for auto-aligned manufacturing of a trench-gate mos transistor, and shielded-gate mos transistor | |
TW202326825A (en) | Trench transistor and manufacturing method thereof | |
KR20110029332A (en) | Semiconductor device and method for forming using the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ALPHA & OMEGA SEMICONDUCTOR, LTD., BERMUDA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAI, SUNG-SHAN;HU, YONG-ZHONG;HERBERT, FRANCOIS;AND OTHERS;REEL/FRAME:018745/0536 Effective date: 20061219 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |