CN104916544A - Manufacturing method of groove type split-gate power device - Google Patents
Manufacturing method of groove type split-gate power device Download PDFInfo
- Publication number
- CN104916544A CN104916544A CN201510182461.XA CN201510182461A CN104916544A CN 104916544 A CN104916544 A CN 104916544A CN 201510182461 A CN201510182461 A CN 201510182461A CN 104916544 A CN104916544 A CN 104916544A
- Authority
- CN
- China
- Prior art keywords
- insulation film
- grid
- power device
- control gate
- divides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000009413 insulation Methods 0.000 claims description 98
- 239000000758 substrate Substances 0.000 claims description 31
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 230000008021 deposition Effects 0.000 abstract 1
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the technical field of semiconductor power device manufacture, and specially relates to a manufacturing method of a groove type split-gate power device. According to the manufacturing method of the groove type split-gate power device, in the etching forming process of a control gate groove, a transverse recess, located at the lower part of a first insulating film, of the control gate groove is formed through increasement of transverse etching, and then a first conductive film can be etched directly taking the first insulating film as a mask film after deposition of the first conductive film to form a control gate. The technology process is simplified, reliable and easy to control, and the rate of finished products of the groove type split-gate power devices can be greatly improved. The method is especially suitable for manufacture of 25V-200V semiconductor power devices.
Description
Technical field
The invention belongs to semiconductor power device manufacturing technology field, be specifically related to a kind of manufacture method of semiconductor power device, particularly relate to the manufacture method that a kind of plough groove type divides grid power device.
Background technology
Along with the development of microelectric technique, semiconductor power device with the high and low loss of its input impedance, switching speed is fast, without second breakdown, safety operation area is wide, dynamic property good, being easily coupled with front pole realizes big current, conversion efficiency advantages of higher, alternative bipolar device becomes the main flow that current power device develops gradually.The parasitic capacitance that plough groove type divides grid power device can reduce between control gate and drain region, reduces the dynamic power consumption of device and improves switching speed, having become the preferred structure of semiconductor power device.Existing typical plough groove type divides the manufacture method of grid power device, comprising: first formation control grid recess in substrate epitaxial layer 100, is returned the method at quarter afterwards again at the both sides of control gate groove difference formation control grid 105, as shown in Figure 1a by first deposit conductive layer.Next, return carving method Coverage Control grid 105 again by first deposit insulation film and form insulation film side wall 201, the edge etched substrate epitaxial loayer then along insulation film side wall 201 divides a grid recess to be formed, as shown in Figure 1 b.
Existing typical plough groove type divides the manufacture method Problems existing of grid power device to be: first the transverse width of control gate 105 is narrower, adds the etching difficulty of control gate contact hole; Secondly formed in the process of insulation film side wall 201 in the method passing through back to carve; the insulation film sidewall section being positioned at control gate 105 top is easily etched; be difficult to the effect playing protecting control grid 105, make plough groove type divide the manufacturing process of grid power device to be difficult to control thus, rate of finished products is low.
Summary of the invention
The object of the invention is to propose for overcoming the deficiencies in the prior art the manufacture method that a kind of plough groove type divides grid power device, the present invention can ensure plough groove type divide the stable manufacturing process of grid power device reliable, be easy to control, rate of finished products is high.
Divide the manufacture method of grid power device according to a kind of plough groove type of the present invention's proposition, comprise following concrete steps:
Step one: the substrate epitaxial layer first forming the first doping type on the top in the drain region of the first doping type, then the first insulation film is formed on the top of described substrate epitaxial layer, carry out first photoetching afterwards, finally described first insulation film is etched, form the opening of the first insulation film in the inside of described first insulation film;
Step 2: with described first insulation film for substrate epitaxial layer described in mask etching, at the inside formation control grid recess of described substrate epitaxial layer, the dual-side edge of this control gate groove extends to the bottom of the first insulation film of the both sides of the opening of described first insulation film, forms the lateral recesses being positioned at the bottom of described first insulation film;
Step 3: form the second insulation film on the surface of described control gate groove, then deposit first conductive film, this first conductive film fills up described control gate groove;
Step 4: etching is positioned at described first conductive film on described first insulation film top, and continue described first conductive film of etching, at the both sides formation control grid of described control gate groove along the edge of the opening of described first insulation film; Or first etch the surface of described first conductive film to described substrate epitaxial layer, and then deposit first insulation film also returns the first insulation film side wall carved and be positioned at the opening both sides of described first dielectric film with formation, afterwards along described first conductive film of edge etching of described first insulation film side wall, at the both sides formation control grid of described control gate groove;
Step 5: first the second insulation film of the described control gate groove surfaces exposed is etched, then deposit the 3rd insulation film also returns and carves, the sidewall of the control gate exposed forms the 3rd insulation film side wall, and the edge afterwards along described 3rd insulation film side wall etches described substrate epitaxial layer to form a point grid recess;
Step 6: form the 4th insulation film on the surface of described point of grid recess;
Step 7: first etch described 3rd insulation film side wall, then forms the 5th insulation film on the described control gate surface exposed;
Step 8: deposit second conductive film returning is carved, and forms point grid in described point of grid recess inside, the surface of described point of grid is a little less than the surface of described substrate epitaxial layer;
Step 9: first described first insulation film is etched, then the ion implantation of the second doping type is carried out, in described substrate epitaxial layer, form channel region, carry out the ion implantation of second photoetching and the first doping type afterwards, in described substrate epitaxial layer, form source region;
Step 10: first deposit the 6th insulation film carry out the figure that the 3rd road photoetching forms contact hole, then etching is carried out to described 6th insulation film and form contact hole, carry out the ion implantation of the second doping type afterwards and deposited metal forms ohmic contact;
Step 11: first carry out the 4th road photoetching, then etch described metal level, to form source electrode, control grid electrode and point gate electrode respectively, finally carries out the deposit of passivation layer, Graphic transitions and etching, thus formation plough groove type divides grid power device.
A kind of plough groove type of the present invention divides the further preferred version of the manufacture method of grid power device to be:
The material of the first insulation film of the present invention is silica or silicon nitride.
The material of the 3rd insulation film of the present invention is silicon nitride.
The material of the second insulation film of the present invention, the 4th insulation film and the 5th insulation film is silica.
The material of the 6th insulation film of the present invention is silex glass, boron-phosphorosilicate glass or phosphorosilicate glass.
Control gate of the present invention is polysilicon gate or metal gate.
The material of the second conductive film of the present invention is polysilicon.
The first doping type described in each scheme of the present invention is N-shaped doping, and described the second doping type is p-type doping; Or the first doping type described is p-type doping, described the second doping type is N-shaped doping.
The present invention compared with prior art its remarkable advantage is: a kind of plough groove type that the present invention proposes divides the manufacture method of grid power device in the process of etching formation control grid recess, the lateral recesses part being positioned at the first insulation film bottom of formation control grid recess is carried out by increasing lateral etching, and then can after deposit first conductive film directly with the first insulation film for mask etching first conductive film is with formation control grid, whole technical process is simplified reliably, is easy to control, greatly can improve the rate of finished products of groove-type power device.A kind of plough groove type that the present invention proposes divides the manufacture method of grid power device to be specially adapted to the manufacture of 25V-200V semiconductor power device.
Accompanying drawing explanation
Fig. 1 a and Fig. 1 b is the partial process flow schematic diagram that existing typical a kind of plough groove type divides the manufacture method of grid power device.
Fig. 2 to Figure 11 is the process flow diagram that a kind of plough groove type that the present invention proposes divides an embodiment of the manufacture method of grid power device.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
For convenience of description, be exaggerated the thickness in layer and region in the accompanying drawings, shown size does not represent actual size.Although shown accompanying drawing does not reflect to entirely accurate the actual size of device, they still intactly reflect the mutual alignment between region and composition structure, particularly form the upper and lower and neighbouring relations between structure.The following stated embodiments of the invention should not be considered to the given shape being only limitted to region shown in accompanying drawing, but comprise obtained shape, as manufactured the deviation etc. caused.
Composition graphs 2 to Figure 11, a kind of plough groove type that the present invention proposes divides the technical process of the manufacture method of grid power device specifically to comprise:
First, as shown in Figure 2, first the substrate epitaxial layer 301 of the first doping type is formed on the top in the drain region 300 of the first doping type, then the first insulation film 400 is formed on the top of substrate epitaxial layer 301, carry out the position that first photoetching process defines control gate groove afterwards, finally etch the first insulation film 400, form the opening 410 of the first insulation film in the inside of the first insulation film 400.
The material of described first insulation film 400 is silica or silicon nitride, in the present embodiment for silica.
Next, as shown in Figure 3, be mask etching substrate epitaxial layer 301 with the first insulation film 400, at the inside formation control grid recess 500 of this substrate epitaxial layer 301.In the etching technics of this step, can the lateral recesses being positioned at the first insulation film 400 bottom of formation control grid recess 500 by increasing horizontal etching, the transverse width of this lateral recesses is a.
Next, as shown in Figure 4, first form the second insulation film 302 on the surface of control gate groove, then cover the structure formed and form the first conductive film 600, this first conductive film 600 should fill up control gate groove 500.
The material of described second insulation film 302 is preferably silica, and the material of the first conductive film 600 is polysilicon or metal.
Next, as shown in Figure 5, etch away first conductive film 600 on the first insulation film 400 top, then the edge along the opening 410 of the first insulation film continues etching first conductive film 600, thus the control gate 303 that transverse width is a is formed respectively in the both sides of control gate groove, the transverse width of this control gate 303 is that a should be formed as benchmark with what meet follow-up control gate contact hole, if the transverse width of control gate 303 is that a is too small, will affect the formation of control gate contact hole.
The transverse width of described control gate 303 can be subject to the restriction of lateral etching technique, preferred version is: in the process of etching first conductive film 600, first can etch the apparent height of the first conductive film 600 to substrate epitaxial layer 301, and then deposit first insulation film also returns quarter to form the first insulation film side wall 800 in the both sides of the opening 410 of the first insulation film, the transverse width of the first insulation film 800 is b, as shown in Figure 6 a; Afterwards, the edge along the first insulation film side wall 800 etches the first conductive film 600 to distinguish formation control grid 303 in the both sides of control gate groove 500, as shown in Figure 6 b; The transverse width of control gate 303 can be designed to a+b thus, the restriction of lateral etching technique can be reduced.
Next, still with structure shown in Fig. 5, follow-up detailed description is carried out to the present embodiment.
As shown in Figure 7, etch the second insulation film 302 exposed, then deposit the 3rd insulation film also returns and carves, the sidewall of the control gate 303 exposed forms the 3rd insulation film side wall 401, and the edge etched substrate epitaxial loayer 301 afterwards along the 3rd insulation film side wall 401 divides a grid recess to be formed; The material of described 3rd insulation film is preferably silicon nitride.
In above-mentioned steps, divide grid recess by taking the 3rd insulation film side wall 401 as self aligned etched substrate epitaxial loayer 301 formation of mask, because control gate groove and the etching of point grid recess only used one piece of mask plate for etching control gate groove, thus reduce complexity and the cost of device fabrication.
Next, as shown in Figure 8, the material first forming the 4th insulation film the 304, four insulation film 304 on the surface of point grid recess is preferably silica; Then, as shown in Figure 9, etch away the 3rd insulation film side wall 401, and the material forming the 5th insulation film the 305, five insulation film 305 on the surface of the control gate 303 exposed is preferably silica.
Next, as shown in Figure 10, structure deposit second conductive film that covering is formed also returns and carves, and in point grid recess, formation divides grid 306, and the surface of this point of grid 306 should a little less than the surface of substrate epitaxial layer 301, and the material of point grid 306 is preferably the polysilicon of doping.
Next, as shown in figure 11, first etch away the first insulation film 400, then oxidation forms the thin oxide layer 307 of one deck in order to repair the surface of substrate epitaxial layer 301; Then the ion implantation of the second doping type is carried out to form channel region 308 in substrate epitaxial layer 301, the bottom of this channel region 308 is preferably placed at the bottom position of control gate groove, carry out the position in second photoetching process definition source region afterwards, carry out the ion implantation of the first doping type again, source region 309 is formed in substrate epitaxial layer 301, cover structure deposit the 6th insulation film 310 formed afterwards, carry out the figure that the 3rd road photoetching process forms contact hole again, then etch described 6th insulation film 310 and form contact hole; Finally carry out the ion implantation of the second doping type and deposited metal 311 forms ohmic contact.Wherein, the material of described 6th insulation film 310 is silex glass, boron-phosphorosilicate glass or phosphorosilicate glass.
The second doping type of the present invention and the first doping type are contrary doping type, and even the first doping type is N-shaped doping, then the second doping type is p-type doping; Or if the first doping type is p-type doping, then the second doping type is N-shaped doping.
Finally, carry out the 4th road photoetching, and metal level is etched, to form source electrode, control grid electrode and point gate electrode respectively, carry out the deposit of passivation layer, Graphic transitions and etching afterwards, thus formation plough groove type divides grid power device.
In the specific embodiment of the present invention, all explanations do not related to belong to the known technology of this area, can be implemented with reference to known technology.
The present invention, through validation trial, achieves satisfied effect.
Embodiment involved in above embodiment is the concrete support that a kind of plough groove type proposed the present invention divides the manufacture method technological thought of grid power device; protection scope of the present invention can not be limited with this; every technological thought proposed according to the present invention; any equivalent variations that the technical program basis is done or the change of equivalence, all still belong to the scope of technical solution of the present invention protection.
Claims (8)
1. plough groove type divides a manufacture method for grid power device, it is characterized in that comprising following concrete steps:
Step one: the substrate epitaxial layer first forming the first doping type on the top in the drain region of the first doping type, then the first insulation film is formed on the top of described substrate epitaxial layer, carry out first photoetching afterwards, finally described first insulation film is etched, form the opening of the first insulation film in the inside of described first insulation film;
Step 2: with described first insulation film for substrate epitaxial layer described in mask etching, at the inside formation control grid recess of described substrate epitaxial layer, the dual-side edge of this control gate groove extends to the bottom of the first insulation film of the both sides of the opening of described first insulation film, forms the lateral recesses being positioned at the bottom of described first insulation film;
Step 3: form the second insulation film on the surface of described control gate groove, then deposit first conductive film, this first conductive film fills up described control gate groove;
Step 4: etching is positioned at described first conductive film on described first insulation film top, and continue described first conductive film of etching, at the both sides formation control grid of described control gate groove along the edge of the opening of described first insulation film; Or first etch the surface of described first conductive film to described substrate epitaxial layer, and then deposit first insulation film also returns the first insulation film side wall carved and be positioned at the opening both sides of described first dielectric film with formation, afterwards along described first conductive film of edge etching of described first insulation film side wall, at the both sides formation control grid of described control gate groove;
Step 5: first the second insulation film of the described control gate groove surfaces exposed is etched, then deposit the 3rd insulation film also returns and carves, the sidewall of the control gate exposed forms the 3rd insulation film side wall, and the edge afterwards along described 3rd insulation film side wall etches described substrate epitaxial layer to form a point grid recess;
Step 6: form the 4th insulation film on the surface of described point of grid recess;
Step 7: first etch described 3rd insulation film side wall, then forms the 5th insulation film on the described control gate surface exposed;
Step 8: deposit second conductive film returning is carved, and forms point grid in described point of grid recess inside, the surface of described point of grid is a little less than the surface of described substrate epitaxial layer;
Step 9: first described first insulation film is etched, then the ion implantation of the second doping type is carried out, in described substrate epitaxial layer, form channel region, carry out the ion implantation of second photoetching and the first doping type afterwards, in described substrate epitaxial layer, form source region;
Step 10: first deposit the 6th insulation film carry out the figure that the 3rd road photoetching forms contact hole, then etching is carried out to described 6th insulation film and form contact hole, carry out the ion implantation of the second doping type afterwards and deposited metal forms ohmic contact;
Step 11: first carry out the 4th road photoetching, then etch described metal level, to form source electrode, control grid electrode and point gate electrode respectively, finally carries out the deposit of passivation layer, Graphic transitions and etching, thus formation plough groove type divides grid power device.
2. a kind of plough groove type according to claim 1 divides the manufacture method of grid power device, it is characterized in that the material of described first insulation film is silica or silicon nitride.
3. a kind of plough groove type according to claim 1 divides the manufacture method of grid power device, it is characterized in that the material of described 3rd insulation film is silicon nitride.
4. a kind of plough groove type according to claim 1 divides the manufacture method of grid power device, it is characterized in that the material of described second insulation film, the 4th insulation film and the 5th insulation film is silica.
5. a kind of plough groove type according to claim 1 divides the manufacture method of grid power device, it is characterized in that the material of described 6th insulation film is silex glass, boron-phosphorosilicate glass or phosphorosilicate glass.
6. a kind of plough groove type according to claim 1 divides the manufacture method of grid power device, it is characterized in that described control gate is polysilicon gate or metal gate.
7. a kind of plough groove type according to claim 1 divides the manufacture method of grid power device, it is characterized in that the material of described second conductive film is polysilicon.
8. a kind of plough groove type according to claim 1-7 divides the manufacture method of grid power device, and it is characterized in that the first doping type described is N-shaped doping, described the second doping type is p-type doping; Or the first doping type described is p-type doping, described the second doping type is N-shaped doping.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510182461.XA CN104916544B (en) | 2015-04-17 | 2015-04-17 | A kind of manufacture method of plough groove type point grid power device |
| US15/307,341 US9673299B2 (en) | 2015-04-17 | 2016-03-15 | Method for manufacturing split-gate power device |
| PCT/CN2016/076432 WO2016165516A1 (en) | 2015-04-17 | 2016-03-15 | Manufacturing method for split-gate power device |
| KR1020167033055A KR101812440B1 (en) | 2015-04-17 | 2016-03-15 | Manufacturing method for split-gate power device |
| JP2016570830A JP6310577B2 (en) | 2015-04-17 | 2016-03-15 | Manufacturing method of split gate type power device |
| DE112016000050.2T DE112016000050B4 (en) | 2015-04-17 | 2016-03-15 | Method for manufacturing a split gate power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510182461.XA CN104916544B (en) | 2015-04-17 | 2015-04-17 | A kind of manufacture method of plough groove type point grid power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104916544A true CN104916544A (en) | 2015-09-16 |
| CN104916544B CN104916544B (en) | 2017-09-05 |
Family
ID=54085524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510182461.XA Active CN104916544B (en) | 2015-04-17 | 2015-04-17 | A kind of manufacture method of plough groove type point grid power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104916544B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105551964A (en) * | 2015-12-25 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for MOSFET adopting separated trench side gate structure with shield gate |
| WO2016165516A1 (en) * | 2015-04-17 | 2016-10-20 | 苏州东微半导体有限公司 | Manufacturing method for split-gate power device |
| CN106653834A (en) * | 2015-09-22 | 2017-05-10 | 苏州东微半导体有限公司 | Method for manufacturing semiconductor power device |
| CN109216174A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The division grid structure and its manufacturing method of semiconductor devices |
| CN112271134A (en) * | 2020-10-20 | 2021-01-26 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device |
| CN113628968A (en) * | 2020-05-06 | 2021-11-09 | 苏州东微半导体股份有限公司 | Manufacturing method of semiconductor super junction device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050139910A1 (en) * | 2003-12-30 | 2005-06-30 | Koh Kwan J. | Semiconductor devices and methods for fabricating the same |
| CN1729558A (en) * | 2002-12-19 | 2006-02-01 | 皇家飞利浦电子股份有限公司 | Vertical split gate non-volatile memory cell and method of fabrication thereof |
| US20080150013A1 (en) * | 2006-12-22 | 2008-06-26 | Alpha & Omega Semiconductor, Ltd | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
| CN101325157A (en) * | 2007-06-11 | 2008-12-17 | 南亚科技股份有限公司 | Memory construction and preparation method thereof |
| US20090317953A1 (en) * | 2004-12-31 | 2009-12-24 | Heung Jin Kim | Memory Device and Method for Manufacturing the Same |
| CN102157527A (en) * | 2009-12-31 | 2011-08-17 | 三星电子株式会社 | Semiconductor memory devices |
-
2015
- 2015-04-17 CN CN201510182461.XA patent/CN104916544B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1729558A (en) * | 2002-12-19 | 2006-02-01 | 皇家飞利浦电子股份有限公司 | Vertical split gate non-volatile memory cell and method of fabrication thereof |
| US20050139910A1 (en) * | 2003-12-30 | 2005-06-30 | Koh Kwan J. | Semiconductor devices and methods for fabricating the same |
| US20090317953A1 (en) * | 2004-12-31 | 2009-12-24 | Heung Jin Kim | Memory Device and Method for Manufacturing the Same |
| US20080150013A1 (en) * | 2006-12-22 | 2008-06-26 | Alpha & Omega Semiconductor, Ltd | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
| CN101325157A (en) * | 2007-06-11 | 2008-12-17 | 南亚科技股份有限公司 | Memory construction and preparation method thereof |
| CN102157527A (en) * | 2009-12-31 | 2011-08-17 | 三星电子株式会社 | Semiconductor memory devices |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016165516A1 (en) * | 2015-04-17 | 2016-10-20 | 苏州东微半导体有限公司 | Manufacturing method for split-gate power device |
| US9673299B2 (en) | 2015-04-17 | 2017-06-06 | Su Zhou Oriental Semiconductor Co., Ltd. | Method for manufacturing split-gate power device |
| CN106653834A (en) * | 2015-09-22 | 2017-05-10 | 苏州东微半导体有限公司 | Method for manufacturing semiconductor power device |
| CN105551964A (en) * | 2015-12-25 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for MOSFET adopting separated trench side gate structure with shield gate |
| CN109216174A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The division grid structure and its manufacturing method of semiconductor devices |
| CN113628968A (en) * | 2020-05-06 | 2021-11-09 | 苏州东微半导体股份有限公司 | Manufacturing method of semiconductor super junction device |
| CN113628968B (en) * | 2020-05-06 | 2022-06-24 | 苏州东微半导体股份有限公司 | Manufacturing method of semiconductor super junction device |
| CN112271134A (en) * | 2020-10-20 | 2021-01-26 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device |
| CN112271134B (en) * | 2020-10-20 | 2021-10-22 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device |
| WO2022082902A1 (en) * | 2020-10-20 | 2022-04-28 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device |
| US12015078B2 (en) | 2020-10-20 | 2024-06-18 | Suzhou Oriental Semiconductor Co., Ltd. | Manufacturing method of semiconductor power device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104916544B (en) | 2017-09-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104952718B (en) | A kind of manufacture method of point of grid power device | |
| CN104916544A (en) | Manufacturing method of groove type split-gate power device | |
| CN104716177B (en) | A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage | |
| CN104103694A (en) | Trench type insulated gate field effect transistor and manufacture method thereof | |
| CN106206322B (en) | The manufacturing method of autoregistration low pressure super node MOSFET | |
| CN104779166B (en) | A kind of plough groove type divides grid power device and its manufacture method | |
| CN108649072B (en) | Low-on-resistance trench MOSFET device and manufacturing method thereof | |
| US9673299B2 (en) | Method for manufacturing split-gate power device | |
| CN104347422A (en) | Manufacturing method of groove type MOS (Metal Oxide Semiconductor) transistor with electrostatic discharge protection circuit | |
| CN108962989B (en) | Groove type MOS device and manufacturing method thereof | |
| CN104103523A (en) | Method for manufacturing power device with U-shaped grooves | |
| CN104795445A (en) | Low-loss super-junction power device and manufacturing method thereof | |
| CN108091573A (en) | Shield grid groove MOSFET ESD structures and its manufacturing method | |
| CN103151309A (en) | Deeply-grooved power MOS (Metal Oxide Semiconductor) device and preparation method thereof | |
| CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
| CN103151310A (en) | Deeply-grooved power MOS (Metal Oxide Semiconductor) device and production method thereof | |
| CN116110944A (en) | Shielded gate trench MOSFET device based on Resurf effect and preparation method thereof | |
| CN104617045A (en) | Manufacturing method of trench gate power device | |
| CN104103693A (en) | U-groove power device and manufacturing method thereof | |
| CN104253050B (en) | A kind of manufacture method of grooved lateral MOSFET device | |
| CN104425279A (en) | Fin type field effect transistor, forming method of fin type field effect transistor and semiconductor device | |
| CN102956481B (en) | There is the manufacture method of the groove type power semiconductor component of source electrode groove | |
| CN112864019A (en) | Method for manufacturing semiconductor power device and semiconductor power device | |
| CN103066102B (en) | Groove type power semiconductor element for raising breakdown voltage and its manufacturing method | |
| CN206134689U (en) | Low pressure trench gate DMOS device of high integration |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: C102-1, phase II, international science and Technology Park, 1355 Jinjihu Avenue, Suzhou Industrial Park, Jiangsu Province Patentee after: Suzhou Dongwei Semiconductor Co.,Ltd. Address before: C102-1, phase II, international science and Technology Park, 1355 Jinjihu Avenue, Suzhou Industrial Park, Jiangsu Province Patentee before: SU ZHOU ORIENTAL SEMICONDUCTOR Co.,Ltd. |