CN107068758A - VDMOS device with internal field plate structure - Google Patents
VDMOS device with internal field plate structure Download PDFInfo
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- CN107068758A CN107068758A CN201710039708.1A CN201710039708A CN107068758A CN 107068758 A CN107068758 A CN 107068758A CN 201710039708 A CN201710039708 A CN 201710039708A CN 107068758 A CN107068758 A CN 107068758A
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000003989 dielectric material Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910020286 SiOxNy Inorganic materials 0.000 claims description 5
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The present invention provides a kind of VDMOS device with internal field plate structure, and each structure cell includes metalized drain, N+ substrates, N drift regions and the metallizing source set gradually from bottom to up；There is trough-shaped body field plate region, trough-shaped body field plate region, which includes being respectively arranged on the left side and the right side inside gradual change dielectric layer, polysilicon field plate, N drift regions above p-type doped region, p-type doped region, is provided with N+ heavy doping source regions in N drift regions；The upper surface of N drift regions, which is provided with above gate oxide, gate oxide, gate electrode；Dielectric layer is provided with above gate electrode；Without P+ heavily doped regions in the structure cell of device, gradual change dielectric layer is the composite dielectric materials of graded dielectric constant, and its dielectric constant is gradually reduced from close to metallizing source side to close to metalized drain side；The invention enables its internal drift region Electric Field Distribution is more uniform, compared to traditional field plate class device, it can bear higher pressure-resistant, higher outer layer doping concentration can be used, so that with smaller conducting resistance.
Description
Technical field
The present invention relates to power semiconductor device technology field, and in particular to a kind of power with internal field plate structure
VDMOS (vertical DMOS field-effect transistor).
Background technology
VDMOS has the advantage of bipolar transistor and common MOS device concurrently.Its switching speed is very fast with respect to bipolar transistor,
Switching loss is small；Input impedance is high, and driving power is small；Mutual conductance highly linear；Frequency characteristic is good；Safety operation area is relatively large.
The development of power VDMOSFET is on the basis of MOS device its own advantages, to make great efforts to improve the pressure-resistant and low-loss process of drop.
Power MOS two important fundamental characteristics are its conducting resistance RdsonWith breakdown voltage VBR, conducting resistance Rdson
It is the resistance for weighing its conducting, is the important parameter of static energy loss when weighing its conducting, breakdown voltage VBRIt is to weigh its pass
It is capable of the class parameter of blocking voltage when disconnected.The method of conventional lift breakdown voltage is the doping concentration of reduction drift region, increase
Its thickness, but this method is reduced due to the doping concentration of drift region, the increase of its resistivity, and drift region thickness increase so that
MOS conducting resistance rises Rdson.Traditional VDMOS device is pressure-resistant by low-doped drift region, depletion layer electricity in drift region
Field distribution is triangular in shape, its is pressure-resistant VBRWith conducting resistance RdsonMeet below equation：
Rdson=5.93 × 10-9*VBR 2.5
Above-mentioned formula is referred to as the silicon limit, it can be seen that traditional VDMOS conducting resistance Rdson∝VBR 2.5.To break this
The silicon limit, occurs in that different device architectures, such as super-junction structure (super junction) and separate gate structures (split
Gate), new structure is different from traditional one-dimensional device architecture, is the two-dimensional structure by introducing extra electric field component, carries
Rise device pressure-resistant, break the silicon limit.On this basis, the VDMOS of field plate structure becomes the solution that another breaks the silicon limit
Certainly scheme, but conventional field plate structure VDMOS, due to field plate and source electrode equipotential, the longitudinal electric field in its drift region is distributed
As shown in Fig. 2-2, it can be seen that because the current potential on whole field plate is identical, longitudinal electric field value in drift region is along Vertical Square
To decline, reversely pressure-resistant further raising is constrained.
The content of the invention
The purpose of the present invention is that there is provided a kind of VDMOS devices with internal field plate structure for defect of the prior art
Part.
For achieving the above object, technical solution of the present invention is as follows：
A kind of VDMOS device with internal field plate structure, each structure cell includes the gold set gradually from bottom to up
Categoryization drain electrode, N+ substrates, N- drift regions and metallizing source；There is trough-shaped body field plate region, the flute profile in the N- drift regions
Body field plate region includes：Gradual change dielectric layer positioned at the N- drift regions left and right sides, the polysilicon field plate in gradual change dielectric layer, institute
State and be connected above polysilicon field plate with metallizing source；Left and right sides difference inside N- drift regions between left and right gradual change dielectric layer
Provided with p-type doped region, N+ heavy doping source regions are provided with above the p-type doped region of the left and right sides；N+ heavy doping source regions junction depth is less than p-type
Doped region, the upper end of gradual change dielectric layer is located at the friendship of lower surface top, N+ heavy doping source region and the p-type doped region of p-type doped region
Below interface, and the p-type doped region and the remote device center of N+ heavy doping source regions side wall with the polysilicon field plate
It is in contact, the upper surface of the N+ heavy doping source region is connected with metallizing source；The upper surface of the N- drift regions is provided with grid oxygen
Changing above layer, the gate oxide has gate electrode；Semiconductor surface between p-type doped region and gate electrode is covered by gate oxide
Lid, the semiconductor between the incomplete covering grid electrode of gate oxide and N+ heavy doping source regions；Medium is provided with above the gate electrode
Layer；Without P+ heavily doped regions, the gradual change medium in covering source metal, the structure cell of the device above the dielectric layer
Layer is the composite dielectric materials of graded dielectric constant, and its dielectric constant is from close to metallizing source side to close metalized drain side
It is gradually reduced.
It is preferred that, gate electrode is trench gate structure.
It is preferred that, the gradual change dielectric layer is silicon oxynitride SiOxNy。
It is preferred that, the device includes more than one above-mentioned structure cell.Actual power device is by multi cell
Collectively form, realize in requisition for function.
The present invention can improve pressure-resistant, reduction conducting resistance principle：
A kind of VDMOS device with internal field plate structure, electrode connection mode during its reverse blocking is：Gate electrode and
Metallizing source short circuit and connecting to neutral current potential, metalized drain connect positive potential.Under a reverse bias, PXing Ti areas and drain electrode PN junction shape
Into depletion layer, bear pressure-resistant.Due to the appearance of groove body field plate, depletion layer can be formed at the edge of body field plate, so as to promote consumption
Layer to the greatest extent extends downwards, and Fig. 5-1 show the device when off, its depletion region edge boundary line schematic diagram.Fig. 5-2 turns off for device
When, longitudinal electric field distribution schematic diagram.In the invention, internal field plate uses the dielectric material of graded dielectric constant, makes the sense of current
Electric fields uniform is distributed, while electric-field intensity will not be made to advance to up to critical electric field strength.Mathematical formulae is carried out to the principle below
Derive, its simplified model can be extracted from device architecture as shown in Figure 4.The V in simplified modelFP(x) source potential is connect, i.e.,
Field plate current potential zero potential when device is pressure-resistant；The width t of semiconductor in modelsFor one of the drift region length between device field plate
Half, the dielectric constant of semiconductor is εs, doping concentration is ρ (x), y-axis direction uniform doping；Gradual change between field plate and semiconductor
The thickness of dielectric layer is tOX, dielectric constant is εd；
In MOS semiconductor regions, its Electric Field Distribution meets two-dimentional Poisson's equation：
Due to
Make the pressure-resistant direction Electric Field Distribution of semiconductor uniform, i.e., semiconductor domestic demand meets ideal RESURF equations
Assuming that the dielectric constant of semiconductor is εs, dielectric layer dielectric constant εd, left end P+ become zero point position, right-hand member N+ be BV
Voltage.Present double of conductor potential is derived, due to preferable RESURF knots, and electric field is distributed in semiconductor inner homogeneous,
Therefore consider formula：
The formula meets Poisson's equation (formula 1.4) and ideal RESURF equations (formula 1.5).Usual doping concentration is in y-axis direction
Upper uniform, concentration gradient is 0 or constant in the direction of the x axis, it is assumed that semiconductor internal charge density p is only x linear letter
Number, i.e. ρ (x, y)=ρ (x), it is possible thereby to derive place's semiconductor built-in potential distribution functionI.e.
The formula need to meet boundary condition：
The expression formula that potential distribution function in semiconductor can be derived is：
Assuming that semiconductor and dielectric layer are without interface charge, then semiconductor side and dielectric layer side electric displacement vector normal component connect
It is continuous, i.e.,：
εOXEOX=εSES
Then the potential of optional position is on field plate：
Namely electric field is the sum of the position semiconductor transverse potential and longitudinal potential on field plate, along with voltage on dielectric layer
VOX.Electrical potential difference is in oxide layer：
So,
Wherein,
Indentily transformation is carried out to above formula：
It can draw：
Equation 1 above .9 points out, can be larger using source side dielectric constant, and the less dielectric layer of drain side dielectric constant delays
With voltage's distribiuting in semiconductor, the breakdown voltage of device is improved.When it is implemented, can be changed by changing the component of dielectric material
Become its dielectric constant, such as use SiOxNyAs dielectric layer, by changing the proportion shared by O and N, SiO can be changedxNyMaterial
Dielectric constant.
The relatively conventional MOS of the structure cell reduces parasitic base resistance without P+ areas simultaneously, using source polysilicon
Plate is realized with p-type polysilicon and is connected, and can realize smaller cellular size, improves integration density, reduces conducting resistance.
Beneficial effects of the present invention are：Field plate dielectric layer of the present invention using tapered dielectric constants material gradual change dielectric layer with
The body field plate structure of polysilicon field plate formation so that its internal drift region Electric Field Distribution is more uniform, compared to traditional field plate class
Device, can bear higher pressure-resistant.Meanwhile, it is capable to using higher outer layer doping concentration, so that with smaller electric conduction
Resistance.In addition, saving traditional P+ heavily doped regions, it is connected using field plate polysilicon with source metal and body area so that cellular size
Reduce, improve integration density so that conducting resistance further reduces.
Brief description of the drawings
Fig. 1 is common aspect field plate VDMOS cross-sectional view.
Line schematic diagram is exhausted when Fig. 2-1 is common aspect field plate VDMOS pressure-resistant.
Fig. 2-2 is common aspect field plate VDMOS drift region Electric Field Distribution schematic diagram.
Fig. 3 is the cross-sectional view of embodiment 1.
Fig. 4 is the simplification figure of the principle of the invention.
Fig. 5-1, which is embodiment 1, exhausts line schematic diagram when pressure-resistant.
Fig. 5-2 is the drift region Electric Field Distribution schematic diagram of embodiment 1.
Fig. 6 is the cross-sectional view of embodiment 2.
Fig. 7-1, which is embodiment 2, exhausts line schematic diagram when pressure-resistant.
Fig. 7-2 is the drift region Electric Field Distribution schematic diagram of embodiment 2.
1 is metalized drain, and 2 be N+ substrates, and 3 be N- drift regions, and 4 be polysilicon field plate, and 5 be p-type doped region, and 6 be grid
Oxide layer, 7 be N+ heavy doping source regions, and 8 be gate electrode, and 9 be gradual change dielectric layer, and 10 be dielectric layer, and 11 be metallizing source.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Embodiment 1
Each structure cell includes metalized drain 1, N+ substrates 2, N- drift regions 3 and the metal set gradually from bottom to up
Change source electrode 11；There is trough-shaped body field plate region, the trough-shaped body field plate region includes in the N- drift regions 3：It is left positioned at N- drift regions 3
The gradual change dielectric layer 9 of right both sides, the polysilicon field plate 4 in gradual change dielectric layer 9, the top of polysilicon field plate 4 and metal
Change source electrode 11 to be connected；P-type doped region 5 is respectively arranged on the left side and the right side inside N- drift regions 3 between left and right gradual change dielectric layer 9, it is left
The top of p-type doped region 5 of right both sides is provided with N+ heavy doping source region 7；The junction depth of N+ heavy doping source region 7 is less than p-type doped region 5, gradual change
The upper end of dielectric layer 9 is located under the interface of the lower surface of p-type doped region 5 top, N+ heavy doping source region 7 and p-type doped region 5
Side, and the side wall of the p-type doped region 5 and the remote device center of N+ heavy doping source region 7 connects with the polysilicon field plate 4
Touch, the upper surface of the N+ heavy doping source region 7 is connected with metallizing source 11；The upper surface of the N- drift regions 3 is provided with grid oxygen
Change layer 6, there is gate electrode 8 top of gate oxide 6；Semiconductor surface between p-type doped region 5 and gate electrode 8 is by gate oxidation
Layer 6 is covered, the semiconductor between the incomplete covering grid electrode 8 of gate oxide 6 and N+ heavy doping source region 7；Above the gate electrode
Provided with dielectric layer 10；Without P+ heavy doping in the top of the dielectric layer 10 covering source metal 11, the structure cell of the device
Area, the gradual change dielectric layer 9 is the composite dielectric materials of graded dielectric constant, and its dielectric constant is from close to the side of metallizing source 11
It is gradually reduced to close to the side of metalized drain 1.
The gradual change dielectric layer 9 is silicon oxynitride SiOxNy.By changing the proportion shared by O and N, SiOxNy materials can be changed
The dielectric constant of material.
The structure cell of the present embodiment, relatively conventional MOS reduces parasitic base resistance without P+ heavily doped regions, using source
Pole polysilicon field plate is realized with p-type polysilicon and is connected, and can realize smaller cellular size, improves integration density, reduces conducting
Resistance.The device may include more than one above-mentioned structure cell, and actual power device is collectively formed by multi cell, realizes phase
In requisition for function.
Embodiment 2
The present embodiment and embodiment 1 are essentially identical, and difference is：The gate electrode 8 is trench gate structure.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art without departing from disclosed spirit with being completed under technological thought
All equivalent modifications or change, should by the present invention claim be covered.
Claims (4)
1. a kind of VDMOS device with internal field plate structure, it is characterised in that：Each structure cell is included from bottom to up successively
Metalized drain (1), N+ substrates (2), N- drift regions (3) and the metallizing source (11) of setting；Have in the N- drift regions (3)
There is trough-shaped body field plate region, the trough-shaped body field plate region includes：Gradual change dielectric layer (9), position positioned at N- drift regions (3) left and right sides
It is connected above polysilicon field plate (4) in gradual change dielectric layer (9), the polysilicon field plate (4) with metallizing source (11)；It is left
P-type doped region (5), the P of the left and right sides are respectively arranged on the left side and the right side inside N- drift regions (3) between right gradual change dielectric layer (9)
N+ heavy doping source region (7) is provided with above type doped region (5)；N+ heavy doping source region (7) junction depth is less than p-type doped region (5), and gradual change is situated between
The upper end of matter layer (9) is located at the boundary of lower surface top, N+ heavy doping source region (7) and the p-type doped region (5) of p-type doped region (5)
Below face, and the p-type doped region (5) and the remote device center of N+ heavy doping source region (7) side wall with the polysilicon
Field plate (4) is in contact, and the upper surface of the N+ heavy doping source region (7) is connected with metallizing source (11)；The N- drift regions (3)
Upper surface be provided with above gate oxide (6), the gate oxide (6) and have gate electrode (8)；P-type doped region (5) and gate electrode
(8) semiconductor surface between is covered by gate oxide (6), gate oxide (6) not exclusively covering grid electrode (8) and N+ heavy doping
Semiconductor between source region (7)；Dielectric layer (10) is provided with above the gate electrode；Covering source electrode gold above the dielectric layer (10)
Belong to without P+ heavily doped regions in layer (11), the structure cell of the device, the gradual change dielectric layer (9) is answered for graded dielectric constant
Dielectric material is closed, its dielectric constant is gradually reduced from close to metallizing source (11) side to close to metalized drain (1) side.
2. a kind of VDMOS device with internal field plate structure according to claim 1, it is characterised in that：Gate electrode (8)
For trench gate structure.
3. a kind of VDMOS device with internal field plate structure according to claim 1, it is characterised in that：The gradual change
Dielectric layer (9) is silicon oxynitride SiOxNy。
4. a kind of VDMOS device with internal field plate structure according to claim 1, it is characterised in that：The device
Including more than one above-mentioned structure cell.
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| CN201710039708.1A CN107068758A (en) | 2017-01-19 | 2017-01-19 | VDMOS device with internal field plate structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108091695A (en) * | 2017-12-13 | 2018-05-29 | 深圳市晶特智造科技有限公司 | Vertical bilateral diffusion field-effect tranisistor and preparation method thereof |
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|---|---|---|---|---|
| US20110275210A1 (en) * | 2009-04-20 | 2011-11-10 | Texas Instruments Incorporated | Method of making vertical transistor with graded field plate dielectric |
| US20150357461A1 (en) * | 2014-06-09 | 2015-12-10 | Texas Instruments Incorporated | Integrated termination for multiple trench field plate |
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2017
- 2017-01-19 CN CN201710039708.1A patent/CN107068758A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110275210A1 (en) * | 2009-04-20 | 2011-11-10 | Texas Instruments Incorporated | Method of making vertical transistor with graded field plate dielectric |
| US20150357461A1 (en) * | 2014-06-09 | 2015-12-10 | Texas Instruments Incorporated | Integrated termination for multiple trench field plate |
| US9450082B2 (en) * | 2014-06-09 | 2016-09-20 | Texas Instruments Incorporated | Integrated termination for multiple trench field plate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108091695A (en) * | 2017-12-13 | 2018-05-29 | 深圳市晶特智造科技有限公司 | Vertical bilateral diffusion field-effect tranisistor and preparation method thereof |
| CN108091695B (en) * | 2017-12-13 | 2020-08-28 | 南京溧水高新创业投资管理有限公司 | Vertical double-diffused field effect transistor and manufacturing method thereof |
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