CN107154426A - A kind of device architecture and implementation method for improving silicon substrate GaN HEMT breakdown voltages - Google Patents
A kind of device architecture and implementation method for improving silicon substrate GaN HEMT breakdown voltages Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 52
- 239000010703 silicon Substances 0.000 title claims abstract description 52
- 239000000758 substrate Substances 0.000 title claims abstract description 52
- 230000015556 catabolic process Effects 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 29
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 7
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 238000005036 potential barrier Methods 0.000 claims abstract description 7
- 230000009471 action Effects 0.000 claims abstract description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000005566 electron beam evaporation Methods 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 238000002156 mixing Methods 0.000 claims description 7
- 238000012360 testing method Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 239000007772 electrode material Substances 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 3
- 229910052737 gold Inorganic materials 0.000 claims 3
- 239000010931 gold Substances 0.000 claims 3
- 229910052741 iridium Inorganic materials 0.000 claims 3
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims 3
- 229910052750 molybdenum Inorganic materials 0.000 claims 3
- 239000011733 molybdenum Substances 0.000 claims 3
- 229910052759 nickel Inorganic materials 0.000 claims 3
- 229910052697 platinum Inorganic materials 0.000 claims 3
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 2
- 229910052790 beryllium Inorganic materials 0.000 claims 2
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052681 coesite Inorganic materials 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 2
- 229910052593 corundum Inorganic materials 0.000 claims 2
- 229910052906 cristobalite Inorganic materials 0.000 claims 2
- 229910052763 palladium Inorganic materials 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- 229910052711 selenium Inorganic materials 0.000 claims 2
- 239000011669 selenium Substances 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- 229910052682 stishovite Inorganic materials 0.000 claims 2
- 229910052718 tin Inorganic materials 0.000 claims 2
- 229910052905 tridymite Inorganic materials 0.000 claims 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 239000004411 aluminium Substances 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 239000010941 cobalt Substances 0.000 claims 1
- 229910017052 cobalt Inorganic materials 0.000 claims 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052758 niobium Inorganic materials 0.000 claims 1
- 239000010955 niobium Substances 0.000 claims 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims 1
- HYXGAEYDKFCVMU-UHFFFAOYSA-N scandium(III) oxide Inorganic materials O=[Sc]O[Sc]=O HYXGAEYDKFCVMU-UHFFFAOYSA-N 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a kind of device architecture for improving silicon substrate GaN HEMT breakdown voltages and preparation method thereof, the structure includes silicon substrate, carbon doping GaN or AlN cushion, GaN channel layers, AlGaN potential barrier, insulation gate dielectric layer, gate electrode, dielectric passivation layer, source Schottky ohm mixed electrode and drain terminal Ohmic electrode.Epitaxial growth AlGaN/GaN heterojunction materials, and being formed on this structure after insulation gate dielectric layer, active area, source and drain Ohmic contact and grid metal on a silicon substrate, form source Schottky ohm mixed electrode.Schottky contact structure serves certain shielding action to high pressure, reduces the electric current for being injected into drain terminal via device channel barrier layer or cushion from source, and then improve the breakdown voltage of device.Implementation method of the present invention is simple, increases substantially GaN HEMT breakdown voltage, widens its application in power switch field.
Description
Technical field
The invention belongs to microelectronics technology, it is related to the making of GaN base power electronic devices
Background technology
In recent years, wide bandgap semiconductor GaN is received significant attention with the superior material property such as its high electron mobility, high breakdown field strength.In addition, due to strong spontaneous polarization effect, in the two-dimensional electron gas of the conventional naturally occurring high concentration of AlGaN/GaN heterojunction boundaries.Therefore in theory for, AlGaN/GaN HEMTs (HEMT) have extremely wide application prospect in fields such as high frequency, high-voltage circuit breakers.
The backing material of GaN device is generally silicon, carborundum, three kinds of sapphire, and wherein silicon substrate AlGaN/GaN HEMT enjoy favor because of low, the good wafer size scalability of its price.Although good material property and heterojunction characteristics, silicon substrate GaN HEMT breakdown voltage is still far below theoretic limiting value, and this significantly limit its application in high-voltage switch gear field.
In silicon substrate GaN HEMT, because substrate silicon is completely insulated not as carborundum, sapphire, so its OFF state breakdown characteristics is different from conventional HEMT device：Silicon substrate GaN HEMT breakdown voltage is as gradually saturation is understood in the increase of grid leak spacing rather than gradually increases.The size of saturation breakdown voltage has direct relation when grid leak spacing is not very big with the epitaxy layer thickness in vertical direction.Based on considering for flexibility under lattice mismatch and big wafer size etc., epitaxial layer can not be too thick, therefore with certain challenge in terms of silicon substrate GaN HEMT breakdown voltage is improved.
Improving the method for silicon substrate GaN HEMT breakdown voltages at present mainly has：1. the local silicon substrate removed under source and drain areas；2. substrate transfer technology：After original silicon substrate is all removed, HEMT-structure is allowed to be transferred on the carrier wafer of an insulation, though this method can be completely eliminated limitation of the silicon substrate to GaN HEMT breakdown voltages, and it is more complicated cumbersome and cost is higher；3. the electric leakage of vertical direction can also be controlled so as to obtain high breakdown voltage by improving the thickness of cushion to a certain extent, the method is simple but improves limitation.
The content of the invention
It is an object of the invention to silicon substrate GaN HEMT breakdown voltage is improved with simpler method.On the basis of further investigation silicon substrate GaN HEMT OFF state punctures mechanism, from the angle of device structure design, it is improved in traditional silicon substrate GaN HEMT-structures, in source formation source mixing Schottky-ohmic electrode structure, to realize the silicon substrate GaN HEMT of high-breakdown-voltage, application demand of the GaN base power electronic devices to high switching voltage is met.
The technical thought of the present invention is as follows：The discovery in mechanism is punctured using leakage injection Research on measuring technique silicon substrate GaN HEMT OFF state, when grid leak spacing is larger (such as 10um), breakdown voltage is pulled up a horse with device pinch off and risen to a very high value, but as the further negative sense of grid voltage is moved, breakdown voltage is slowly reduced to after a constant value, this pinch off showed with conventional device again saturation or gradually rises equal difference immediately.Found in the two ends breakdown voltages test carried out therewith, if some two-dimensional electron gas (as shown in Figure 1) beside Ohmic electrode, its breakdown voltage is apparently higher than no two-dimensional electron gas.It is possible thereby to illustrate that two-dimensional electron gas serves certain shielding action to high pressure, also Just because of this, in three terminal device voltage-withstand test, can just have and be moved with grid voltage negative sense, two-dimensional electron gas is gradually depleted, and shielding action weakens, and breakdown voltage is also just gradually reduced after pinch off, after being depleted at utmost, pressure-resistant saturation.Ohm injection that this explanation silicon substrate GaN HEMT OFF state punctures with source is relevant, and damage originally will be produced in source Ohmic contact forming process, in high-pressure process, and Injection Current can be very big, so that causing the breakdown voltage of device reduces.Puncture mechanism along this, silicon substrate GaN HEMT source Ohmic contact can be modified to source Schottky-ohm mixing contact, i.e. on the basis of Ohmic contact, add one section of Schottky contacts, the metal of the Schottky contacts serves the shielding action played the same tune on different musical instruments with two-dimensional electron gas, and when device is subject to high pressure, the influence of a part of high pressure has been fallen in the metallic shield of this section of Schottky contacts, the injection of source Ohmic contact is reduced, so as to improve silicon substrate GaN HEMT breakdown voltage.
According to above-mentioned technical thought, in order to improve silicon substrate GaN HEMT breakdown voltages, a kind of new device structure of utilization source Schottky-ohm mixing contact, including following preparation process：
(1) on a silicon substrate according to GaN the or AlN cushions of certain growth conditions successively Growth of Carbon Doped, intrinsic GaN channel layers, intrinsic AlGaN potential barrier；
(2) the AlGaN/GaN material good to epitaxial growth carries out organic washing, and HCl: H is put into after being cleaned with the deionized water of flowing21~2min is cleaned in O=1: 10 solution, then one layer of thin gate dielectric layer is formed on its surface using PECVD, ICPCVD or LPCVD；
(3) photoetching is carried out to the AlGaN/GaN materials for forming gate dielectric layer, etch source and drain ohmic contact regions, metal ohmic contact is prepared by electron beam evaporation or magnetron sputtering and peeled off, last (800~900 DEG C of rapid thermal annealing in nitrogen environment, 30s), Ohmic contact is formed；
(4) formed after Ohmic contact, further photoetching defines active area, the method injected using Planar Ion and (be generally fluorine ion) or etched realizes the active area isolation of device；
(5) after isolation is formed, photoetching gate electrode region, deposited by electron beam evaporation or observing and controlling sputtering prepare metal gate electrode material, and then carrying out stripping technology processing to device forms gate electrode；
(6) after gate electrode is formed, chemical wet etching formation source Schottky contact area, deposited by electron beam evaporation or observing and controlling sputtering prepare source Schottky contact metal material, and stripping technology processing formation source Schottky-ohm mixing is then carried out to device and is contacted；
(7) after the completion of device is preliminary, the dielectric passivation layer of a thickness is formed on its surface using PECVD, ICPCVD or LPCVD；
(8) after dielectric passivation layer is formed, chemical wet etching goes out grid, source electrode and the test of drain electrode electrode zone, and finally whole wafer is made annealing treatment in a nitrogen environment, completes the preparation of integral device.
The invention has the advantages that：
(1) devices use source Schottky of the present invention-ohm mixing contact structures, so that device is in OFF state breakdown process, the influence of high pressure of source schottky metal partly shielding effect, reduces the leakage current injection of source Ohmic contact, so as to improve silicon substrate GaN HEMT breakdown voltage；
(2) angle of the invention from device structure design, the breakdown voltage for raising silicon substrate GaN HEMT provides a kind of new thinking, can be considered with reference to more excellent techniques, develop high performance silicon substrate GaN HEMT power electronic devices；
(3) implementation method of the invention is more simple compared to the pressure-resistant methods of other raising silicon substrate GaN HEMT, it is easy to accomplish, by regulating and controlling the length of source Schottky contact metal in the horizontal, the pressure-resistant scopes of silicon substrate GaN HEMT can be regulated and controled.
Brief description of the drawings
The principle and its structure of device of the present invention can be more fully hereinafter illustrated by referring to accompanying drawing, and further describes the exemplary embodiment of the present invention, in the accompanying drawings：
Fig. 1 is two ends voltage-withstand test structure (having two-dimensional electron gas at Ohm contact electrode), helps preferably to illustrate the mentality of designing of the present invention；
Fig. 2 is the overall cross-sectional view of device of the present invention；
Fig. 3~Fig. 8 is the cross-sectional view after each step manufacturing process of new structure silicon substrate GaN HEMT in the present invention, reflects the technique manufacturing process of the present invention.
Embodiment
Hereinafter, the present invention is more fully described with reference to the accompanying drawings, embodiment and its implementation process is shown in the drawings, described embodiment is only that a kind of way of realization in the present invention, the i.e. present invention should not be construed as limited to embodiment set forth herein.Based on the embodiment, those skilled in the art are fully conveyed the scope of the present invention to.
Hereinafter, the exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.
Reference picture 2, the order of the device architecture from bottom to top includes silicon-based substrate, GaN the or AlN cushions of carbon doping, intrinsic GaN channel layers, intrinsic AlGaN potential barrier, insulation gate dielectric layer, gate electrode, dielectric passivation layer, source Schottky-ohm mixed electrode and drain terminal Ohmic electrode successively.Its preparation method includes step in detail below：
(1) as shown in Figure 3, first in silicon-based substrate, GaN the or AlN cushions of one layer of carbon doping are grown with MOCVD, then the intrinsic GaN channel layers of one layer of regrowth, intrinsic AlGaN potential barrier is grown above, so far completes the epitaxial growth of silicon substrate AlGaN/GaN materials；
(2) the AlGaN/GaN material good to epitaxial growth in (1) carries out organic washing, and HCl: H is put into after being cleaned with the deionized water of flowing21~2min is cleaned in O=1: 10 solution, then one layer of 20nm Si is formed on its surface using PECVD, ICPCVD or LPCVD3N4Gate dielectric layer, as shown in Figure 4；
(3) photoetching is being carried out shown in Fig. 4 on architecture basics, etch source and drain ohmic contact regions, metal ohmic contact (Ti/Al/Ni/Au=20nm/150nm/50nm/80nm) is prepared by electron beam evaporation and peeled off, last (850 DEG C of rapid thermal annealing in nitrogen environment, 30s), Ohmic contact is formed, as shown in Figure 5；
(4) formed shown in Fig. 5 after structure, further photoetching defines active area, inject the isolation to be formed between device with fluorine ion, fluorine ion energy injection (80kev, 40kev, 20kev) in three times, dosage is 1E14；
(5) after isolation is formed, photoetching gate electrode region, deposited by electron beam evaporation prepares gate metal (Ni/Au=50nm/250nm) and peeled off, and the device cross after formation grid metal is as shown in Figure 6；
(6) after gate electrode is formed, lithographic definition goes out source Schottky contact area, first with the Si that deposit is formed in RIE dry etchings (2)3N4, then deposited by electron beam evaporation prepare source Schottky contact metal and (Ni/Au=50nm/150nm) and peeled off, the device cross so far formed is as shown in Figure 7；
(7) on architecture basics as shown in Figure 7,200nm Si is formed on its surface with PECVD3N4Dielectric passivation layer, as shown in Figure 8；
(8) in the structure shown in Fig. 8, RIE etches grid, source electrode and the test of drain electrode electrode, (400 DEG C, 10min) processing of finally being annealed in a nitrogen environment to whole wafer；
(9) the new structure silicon substrate GaN HEMT devices prepared by above step are pressure-resistant to improve many for conventional structure.
Claims (11)
1. a kind of device architecture and implementation method for improving silicon substrate GaN HEMT breakdown voltages, it is characterised in that：It is described
Structure include silicon substrate, GaN the or AlN cushions of carbon doping, intrinsic GaN channel layers, intrinsic AlGaN potential barrier, absolutely
Edge gate dielectric layer, gate electrode, dielectric passivation layer, source Schottky-ohm mixed electrode and drain terminal Ohmic electrode；The insulation
Gate dielectric layer, source Schottky-ohm mixed electrode and drain terminal Ohmic electrode are respectively positioned on intrinsic AlGaN potential barrier, grid
Electrode is located on insulation gate dielectric layer, and dielectric passivation layer is then located at the superiors；In silicon-based substrate Epitaxial growth containing carbon doping
AlGaN/GaN heterojunction materials, and formed on the heterojunction material mos gate pole, source Schottky-ohm mixed electrode with
And drain terminal Ohmic electrode, finally deposit the passivation that passivation layer realizes device.
2. the device architecture and implementation method according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：Backing material therein is Si.
3. the device architecture and implementation method according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：The material of the insulation gate dielectric layer is any one in following material：Si3N4、Al2O3、AlN、HfO2、
SiO2、HfTiO、Sc2O3、Ga2O3And SiNO.
4. the device architecture and implementation method according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：The gate metal is one or more combinations of following conductive material：Platinum, iridium, nickel, gold, molybdenum, palladium,
Selenium, beryllium, TiN, polysilicon, ITO.
5. the device architecture and implementation method according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：The source electrode and the metal ohmic contact of drain electrode are：Titanium, aluminium, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium,
One or more alloys in cobalt, zirconium, tungsten etc..
6. the device architecture and implementation method according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：The Schottky contact metal material of source Schottky-ohm mixed electrode for following conductive material one kind or
A variety of combinations：Platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, TiN, polysilicon, ITO.
7. the device architecture and implementation method according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：The material of the dielectric passivation layer is any one in material：Si3N4、AlN、Al2O3、SiO2。
8. the device architecture and implementation method according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：The metal of source Schottky contacts serves certain shielding action to high pressure, punctures so as to reduce in OFF state
During source Ohmic contact leakage current injection, so that silicon substrate GaN HEMT breakdown voltage is improved, according to this
Shielding action principle, its structure also can be MOS- ohm of mixing contact electrodes of source.
9. the device architecture and implementation method according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：The length that source schottky metal spills metal ohmic contact can adjust to reach regulation silicon substrate GaN
The purpose of HEMT device breakdown voltage, length range is 1.5~3um.
10. the device architecture according to claim 1 for improving silicon substrate GaN HEMT breakdown voltages and realization side
Method, it is characterised in that including step is implemented as described below：
(1) on a silicon substrate according to GaN the or AlN cushions of certain growth conditions successively Growth of Carbon Doped, intrinsic GaN
Channel layer, intrinsic AlGaN potential barrier；
(2) the AlGaN/GaN material good to epitaxial growth carries out organic washing, and HCl is put into after being cleaned with the deionized water of flowing:
H21~2min is cleaned in O=1: 10 solution, then one is formed on its surface using PECVD, ICPCVD or LPCVD
The thin gate dielectric layer of layer；
(3) photoetching is carried out to the AlGaN/GaN materials for forming gate dielectric layer, etches source and drain ohmic contact regions, pass through electricity
Beamlet evaporates or magnetron sputtering prepares metal ohmic contact and peeled off, finally the rapid thermal annealing in nitrogen environment
(800~900 DEG C, 30s), form Ohmic contact；
(4) formed after Ohmic contact, further photoetching defines active area, injected using Planar Ion (generally fluorine from
Son) or the method for etching realize the active area isolation of device；
(5) after isolation is formed, photoetching gate electrode region, deposited by electron beam evaporation or observing and controlling sputtering prepare metal gate electrode material,
Stripping technology processing then is carried out to device and forms gate electrode；
(6) after gate electrode is formed, chemical wet etching formation source Schottky contact area, deposited by electron beam evaporation or observing and controlling sputtering are made
Standby source Schottky contact metal material, stripping technology processing is then carried out to device and forms source Schottky-ohm mixing contact；
(7) after the completion of device is preliminary, the medium of a thickness is formed on its surface using PECVD, ICPCVD or LPCVD
Passivation layer；
(8) after dielectric passivation layer is formed, chemical wet etching goes out grid, source electrode and the test of drain electrode electrode zone, finally in nitrogen
Whole wafer is made annealing treatment under environment (400 DEG C, 10min).
11. the device architecture and implementation method according to claim 9 for improving silicon substrate GaN HEMT breakdown voltages,
It is characterized in that：Source electrode and the test electrode zone of drain electrode can pass through ICP or RIE dry etchings in the step (8)
Realize.
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