CN107195548B - InAs/AlSb HEMT and preparation method of MOS-HEMT device - Google Patents
InAs/AlSb HEMT and preparation method of MOS-HEMT device Download PDFInfo
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- CN107195548B CN107195548B CN201710364157.6A CN201710364157A CN107195548B CN 107195548 B CN107195548 B CN 107195548B CN 201710364157 A CN201710364157 A CN 201710364157A CN 107195548 B CN107195548 B CN 107195548B
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- 229910000673 Indium arsenide Inorganic materials 0.000 title claims abstract description 127
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 title claims abstract description 127
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
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- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 229910002056 binary alloy Inorganic materials 0.000 claims description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention discloses a preparation method of an InAs/AlSb HEMT and a MOS-HEMT device, which is mainly used for reducing the problems of on-resistance and grid leakage of the device. The preparation method of the InAs/AlSb HEMT device comprises the following process steps: 1) growing an epitaxial material; 2) isolating the table top; 3) preparing ohmic contact; 4) preparing a Schottky gate contact; 5) carrying out Pad deposition; 6) and (5) passivating. The invention provides a preparation method of an InAs/AlSb MOS-HEMT device, which comprises the following process steps: 1) growing an epitaxial material; 2) isolating the table top; 3) preparing ohmic contact; 4) preparing an insulated gate; 5) carrying out Pad deposition; 6) and (5) passivating. The invention saves the step of etching the grid groove, reduces the current leakage of the grid and simultaneously reduces the on-resistance of the device.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and relates to a preparation method of an InAs/AlSb HEMT and an MOS-HEMT device, which can be used for preparing the InAs/AlSb HEMT or the MOS-HEMT device with high speed and low power consumption.
Background
In the modern times, the microelectronic technology has been developed rapidly, the application thereof has penetrated into various fields of national economy, and in order to further meet the requirements of high speed, low power consumption and low noise device performance, a novel device structure is generated. From MOS devices to HEMT devices and MOS-HEMTs. The InAs/AlSb HEMT and MOS-HEMT device structure is favored by the advantages of high carrier mobility, high saturation drift velocity, low critical saturation electric field, strong radiation resistance, high speed, low power consumption, low noise and the like.
The InAs/AlSb HEMT or MOS-HEMT device is manufactured by a plurality of process steps from surface cleaning, ohmic contact, mesa isolation, grid groove etching, grid formation and the like, wherein the grid groove etching is a key step. InAlAs is often used as a contact layer of an InAs/AlSb HEMT or MOS-HEMT device grid, the characteristics of a grid material and an InAlAs contact interface are key factors influencing the overall performance of the device, the characteristics of the device such as subthreshold swing, threshold voltage and grid leakage can be influenced, and the usability and the popularization of the device in an integrated circuit are further influenced.
The gate groove etching generally comprises dry etching and chemical wet etching. Wherein the dry etch introduces damage under the gate which increases leakage. Wet etching has the advantages of simple operation, clean surface, high speed and the like, but the etching time needs to be controlled well to obtain good surface flatness.
Disclosure of Invention
The invention aims to provide a preparation method of an InAs/AlSb HEMT device, and simultaneously provides a preparation method of an InAs/AlSb MOS-HEMT device, which mainly solves the problems of gate leakage and the like of the InAs/AlSb HEMT and MOS-HEMT devices in the prior art.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a preparation method of an InAs/AlSb HEMT device comprises the following process steps: 1) growing an epitaxial material; 2) isolating the table top; 3) preparing ohmic contact; 4) preparing a Schottky gate contact; 5) carrying out Pad deposition; 6) and (5) passivating.
Further, the preparation method of the InAs/AlSb HEMT device comprises the following specific processes:
1) and (3) epitaxial material growth: growing a buffer layer, an AlSb lower barrier layer, an InAs channel layer, an AlSb isolating layer, a doping layer, an AlSb upper barrier layer and an InAlAs hole blocking layer on a substrate in sequence by using an MBE process;
2) isolating the table top:
(a) cleaning the InAs/AlSb material which grows epitaxially, and then blowing the InAs/AlSb material dry by using nitrogen;
(b) photoetching and etching the cleaned InAs/AlSb material to complete the mesa isolation of the epitaxial material;
3) preparing ohmic contact:
(a) cleaning the InAs/AlSb material subjected to mesa isolation, and then blowing dry the material by using nitrogen;
(b) photoetching a source-drain ohmic region on the surface of the cleaned InAs/AlSb material to manufacture a photoresist mask;
(c) etching the source/drain ohmic region to the AlSb isolation layer by using inductively coupled plasma etching equipment
(d) Soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(e) secondarily extending an n-type heavily doped InAs cap layer in a source-drain ohmic region by using an MBE device;
(f) soaking the InAlAs material in photoresist removing solution to remove the photoresist on the upper surface of the InAlAs material and then cleaning the InAlAs material by deionized water;
(g) depositing Pd/Ti/Pt/Au multilayer metal on the heavily doped InAs cap layer of the whole source drain ohmic region, annealing at 350 ℃ for 15-30s, forming a source electrode and a drain electrode on the heavily doped InAs cap layer, and forming ohmic contact between the source electrode and the drain electrode and the InAs cap layer;
4) preparing a Schottky gate contact:
(a) cleaning the device which is subjected to ohmic contact, and then drying the device by using nitrogen;
(b) after cleaning the device which completes ohmic contact, photoetching the gate electrode region on the surface of the InAs/AlSb material to manufacture a photoresist mask;
(c) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(d) performing electron beam evaporation to deposit metal Ti/Pt/Au;
(e) soaking the device in photoresist removing solution, stripping metal except the defined pattern, forming a grid on the InAlAs hole blocking layer, and cleaning with deionized water to complete the manufacture of Schottky grid contact between the grid and the InAlAs hole blocking layer;
5) and (4) Pad deposition:
(a) cleaning the device subjected to Schottky gate contact preparation, and then drying by using nitrogen;
(b) after cleaning a device with Schottky gate contact, photoetching in a Pad region on the surface of an InAs/AlSb material to manufacture a photoresist mask;
(c) performing electron beam evaporation to deposit metal Ti/Au;
(d) soaking the photoresist in the photoresist removing solution, stripping the metal except the defined pattern, and cleaning with deionized water;
6) passivation:
(a) cleaning the device, and then drying the device by using nitrogen;
(b) and depositing a silicon nitride passivation layer on the cleaned device by adopting PECVD equipment, thereby completing the preparation of the InAs/AlSb HEMT device.
Furthermore, the substrate is a GaAs substrate, a Si substrate or an InP substrate, the buffer layer is a binary, ternary or quaternary alloy compound of In, Al, Ga, As and Sb, and the doped layer is InAs doped with Si or AlSb doped with Te.
The invention also provides a preparation method of the InAs/AlSb MOS-HEMT device, which comprises the following process steps: 1) growing an epitaxial material; 2) isolating the table top; 3) preparing ohmic contact; 4) preparing an insulated gate; 5) carrying out Pad deposition; 6) and (5) passivating.
Further, the preparation method of the InAs/AlSb MOS-HEMT device comprises the following specific processes:
1) and (3) epitaxial material growth: growing a buffer layer, an AlSb lower barrier layer, an InAs channel layer, an AlSb isolating layer, a doping layer, an AlSb upper barrier layer and an InAlAs hole blocking layer on a substrate in sequence by using an MBE process;
2) isolating the table top:
(a) cleaning the InAs/AlSb material which grows epitaxially, and then blowing the InAs/AlSb material dry by using nitrogen;
(b) and photoetching and etching the cleaned InAs/AlSb material to finish the mesa isolation of the epitaxial material.
3) Preparing ohmic contact:
(a) cleaning the InAs/AlSb material subjected to mesa isolation, and then blowing dry the material by using nitrogen;
(b) photoetching a source-drain ohmic region on the surface of the cleaned InAs/AlSb material to manufacture a photoresist mask;
(c) etching the source-drain ohmic region by using inductively coupled plasma etching equipment until the AlSb isolation layer is etched;
(d) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(e) secondarily extending an n-type heavily doped InAs cap layer in a source-drain ohmic region by using an MBE device;
(f) soaking the InAlAs material in photoresist removing solution to remove the photoresist on the upper surface of the InAlAs material and then cleaning the InAlAs material by deionized water;
(g) depositing Pd/Ti/Pt/Au multilayer metal on the heavily doped InAs cap layer of the whole source drain ohmic region, annealing at 350 ℃ for 15-30s, forming a source electrode and a drain electrode on the heavily doped InAs cap layer, and forming ohmic contact between the source electrode and the drain electrode and the InAs cap layer;
4) preparing an insulated gate:
(a) cleaning the device which is subjected to ohmic contact, and then drying the device by using nitrogen;
(b) after cleaning the device which completes ohmic contact, photoetching the dielectric layer region on the surface of the InAs/AlSb material to manufacture a photoresist mask;
(c) soaking the substrate in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s, removing a surface oxidation layer, and depositing a dielectric layer by adopting ALD (atomic layer deposition);
(d) completing ALD deposition of a dielectric layer, and photoetching the gate electrode region on the surface of the InAs/AlSb material to manufacture a photoresist mask;
(e) depositing metal Ti/Pt/Au on the dielectric layer by electron beam evaporation;
(f) soaking the device in the photoresist removing solution, stripping the metal except the defined pattern, forming a grid on the dielectric layer, and then cleaning with deionized water to finish the manufacture of the insulated grid;
5) and (4) Pad deposition:
(a) cleaning a device subjected to insulated gate preparation, and then drying by using nitrogen;
(b) after cleaning a device which completes the preparation of the insulated gate, photoetching is carried out on a Pad area on the surface of the InAs/AlSb material, and a photoresist mask is manufactured;
(c) performing electron beam evaporation to deposit metal Ti/Au;
(d) and soaking the device in the photoresist removing solution, stripping the metal except the defined pattern, and cleaning with deionized water.
6) Passivation:
(a) cleaning the device, and then drying the device by using nitrogen;
(b) and depositing a silicon nitride passivation layer on the cleaned device by adopting PECVD equipment, thereby completing the preparation of the InAs/AlSb MOS-HEMT device.
Furthermore, the substrate is a GaAs substrate, a Si substrate or an InP substrate, the buffer layer is a binary, ternary or quaternary alloy compound of In, Al, Ga, As and Sb, and the doped layer is InAs doped with Si or AlSb doped with Te.
Further, the dielectric layer is a high-k dielectric material.
Compared with the prior art, the invention has the following advantages:
when an HEMT device or an MOS-HEMT device is manufactured, the etching cap layer is often difficult to control the etching depth, the barrier layer InAlAs can be etched, the etched surface is uneven, and the grid leakage is increased.
Drawings
FIG. 1 is a schematic structural view of an InAs/AlSb HEMT device prepared according to the present invention;
FIG. 2 is a schematic structural diagram of an InAs/AlSb MOS-HEMT device prepared by the invention;
FIG. 3 is an AFM image of the InAs surface of the epitaxial material prepared by the prior art without wet etching;
FIG. 4 is an AFM image of the InAs surface of the epitaxial material after 10s wet etching;
FIG. 5 is an AFM image of the InAs surface of the epitaxial material after 70s wet etching;
FIG. 6 is an AFM image of the InAlAs layer after the InAs cap layer is completely etched away by wet etching;
FIG. 7 is a model diagram of the on-resistance Ron of an InAs/AlSb HEMT device prepared by the prior art;
FIG. 8 is a model diagram of the on-resistance Ron of the InAs/AlSb HEMT device obtained by the preparation method of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The equipment used by the invention mainly comprises: microelectronic processing equipment such as MBE, PECVD and ALD.
Fig. 1 is a schematic structural view of an InAs/AlSb HEMT device prepared in embodiment 1 of the present invention.
Example 1
The InAs/AlSb HEMT device prepared by the embodiment takes GaAs as a substrate, the buffer layer 2 is AlGaSb, and the doping layer 6 is doped with Si with the concentration of 4 x 1019cm-3The InAs layer(s). The preparation process comprises the following steps:
(a) cleaning the InAs/AlSb material which grows epitaxially, and then blowing the InAs/AlSb material dry by using nitrogen;
(b) photoetching and etching the cleaned InAs/AlSb material to complete the mesa isolation of the epitaxial material;
(a) cleaning the InAs/AlSb material subjected to mesa isolation, and then blowing dry the material by using nitrogen;
(b) photoetching a source-drain ohmic region on the surface of the cleaned InAs/AlSb material to manufacture a photoresist mask;
(c) etching the source-drain ohmic region by using inductively coupled plasma etching equipment until the AlSb isolating layer 5 is etched;
(d) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(e) secondarily extending an n-type heavily doped InAs cap layer 9 in a source-drain ohmic region by using an MBE device;
(f) soaking the InAlAs material in photoresist removing solution to remove the photoresist on the upper surface of the InAlAs material and then cleaning the InAlAs material by deionized water;
(g) depositing Pd/Ti/Pt/Au multilayer metal on the heavily doped InAs cap layer 9 of the whole source drain ohmic region, annealing at 350 ℃ for 15-30s, forming a source electrode 10 and a drain electrode 11 on the heavily doped InAs cap layer 9, and forming ohmic contact between the source electrode 10 and the drain electrode 11 and the InAs cap layer 9;
(a) cleaning the device which is subjected to ohmic contact, and then drying the device by using nitrogen;
(b) after cleaning the device which completes ohmic contact, photoetching the gate electrode region on the surface of the InAs/AlSb material to manufacture a photoresist mask;
(c) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(d) performing electron beam evaporation to deposit metal Ti/Pt/Au;
(e) soaking the device in photoresist removing solution, stripping metal except the defined pattern, forming a grid 12 on the InAlAs hole blocking layer 8, and cleaning with deionized water to complete the manufacture of Schottky grid contact between the grid 12 and the InAlAs hole blocking layer 8;
(a) cleaning the device subjected to Schottky gate contact preparation, and then drying by using nitrogen;
(b) after cleaning a device with Schottky gate contact, photoetching in a Pad region on the surface of an InAs/AlSb material to manufacture a photoresist mask;
(c) performing electron beam evaporation to deposit metal Ti/Au;
(d) soaking the photoresist in the photoresist removing solution, stripping the metal except the defined pattern, and cleaning with deionized water;
(a) cleaning the device, and then drying the device by using nitrogen;
(b) and depositing a silicon nitride passivation layer on the cleaned device by adopting PECVD equipment, thereby completing the preparation of the InAs/AlSb HEMT device.
Fig. 2 is a schematic structural diagram of an InAs/AlSb MOS-HEMT device prepared in embodiment 2 of the present invention.
Example 2
The InAs/AlSb MOS-HEMT device prepared by the embodiment takes GaAs as a substrate, a buffer layer 2 is AlGaSb, and a doping layer 6 is doped with Si with the concentration of 4 x 1019cm-3The InAs layer and the dielectric layer 13 are HfO2. The preparation process comprises the following steps:
1) and (3) epitaxial material growth: by using an MBEMOCVD process, growing a buffer layer 2 (the buffer layer 2 is AlGaSb), an AlSb lower barrier layer 3, an InAs channel layer 4, an AlSb isolating layer 5, a doping layer 6, an AlSb upper barrier layer 7 and an InAlAs hole blocking layer 8 on a substrate 1 in sequence;
2) isolating the table top:
(a) cleaning the InAs/AlSb material which grows epitaxially, and then blowing the InAs/AlSb material dry by using nitrogen;
(b) and photoetching and etching the cleaned InAs/AlSb material to finish the mesa isolation of the epitaxial material.
3) Preparing ohmic contact:
(a) cleaning the InAs/AlSb material subjected to mesa isolation, and then blowing dry the material by using nitrogen;
(b) photoetching a source-drain ohmic region on the surface of the cleaned InAs/AlSb material to manufacture a photoresist mask;
(c) etching the source-drain ohmic region by using inductively coupled plasma etching equipment until the AlSb isolating layer 5 is etched;
(d) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(e) secondarily extending an n-type heavily doped InAs cap layer 9 in a source-drain ohmic region by using an MBE device;
(f) soaking the InAlAs material in photoresist removing solution to remove the photoresist on the upper surface of the InAlAs material and then cleaning the InAlAs material by deionized water;
(g) depositing Pd/Ti/Pt/Au multilayer metal on the heavily doped InAs cap layer 9 of the whole source drain ohmic region, annealing at 350 ℃ for 15-30s, forming a source electrode 10 and a drain electrode 11 on the heavily doped InAs cap layer 9, and forming ohmic contact between the source electrode 10 and the drain electrode 11 and the InAs cap layer 9;
4) preparing an insulated gate:
(a) cleaning the device which is subjected to ohmic contact, and then drying the device by using nitrogen;
(b) after cleaning the device which completes ohmic contact, photoetching the dielectric layer region on the surface of the InAs/AlSb material to manufacture a photoresist mask;
(c) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s, removing a surface oxidation layer, and depositing HfO by ALD2A dielectric layer 13;
(d) completing ALD deposition of HfO2The dielectric layer is used for photoetching in a gate electrode area on the surface of the InAs/AlSb material to manufacture a photoresist mask;
(e) in HfO2On the dielectric layer 13, evaporating and depositing metal Ti/Pt/Au by electron beams;
(f) soaking the device in the photoresist removing solution, stripping the metal except the defined pattern, forming a grid 12 on the dielectric layer 13, and then cleaning with deionized water to finish the manufacture of the insulated grid;
5) and (4) Pad deposition:
(a) cleaning a device subjected to insulated gate preparation, and then drying by using nitrogen;
(b) after cleaning a device which completes the preparation of the insulated gate, photoetching is carried out on a Pad area on the surface of the InAs/AlSb material, and a photoresist mask is manufactured;
(c) performing electron beam evaporation to deposit metal Ti/Au;
(d) and soaking the device in the photoresist removing solution, stripping the metal except the defined pattern, and cleaning with deionized water.
6) Passivation:
(a) cleaning the device, and then drying the device by using nitrogen;
(b) and depositing a silicon nitride passivation layer on the cleaned device by adopting PECVD equipment, thereby completing the preparation of the InAs/AlSb MOS-HEMT device.
Fig. 3 is an AFM image of the surface of the epitaxial material InAs prepared in the prior art without wet etching, fig. 4 is an AFM image of the surface of the epitaxial material InAs after wet etching for 10s, fig. 5 is an AFM image of the surface of the epitaxial material InAs after wet etching for 70s, and fig. 6 is an AFM image of the InAlAs layer after the InAs cap layer is completely etched away by wet etching. The comparison shows that the surface flatness of the material after wet etching is uncontrollable, and if the etching time is too short, the high-doped InAs cap layer is not completely etched, so that a device can cause short circuit; if the etching time is too long, the InAlAs hole blocking layer is etched away, and the grid electrode leakage of the device is increased. The preparation method of the invention omits the step of grid groove corrosion and reduces grid leakage.
Fig. 7 is a model diagram of the on-resistance Ron of an InAs/AlSb HEMT device prepared in the prior art, and fig. 8 is a model diagram of the on-resistance Ron of the InAs/AlSb HEMT device obtained by the preparation method of the present invention. Comparing fig. 7 and fig. 8, it can be seen that the on-resistance of the prior art device is Ron ═ 2(Rc + Rv) + Rch, and the on-resistance of the device of the present invention is Ron ═ 2Rc + Rch, where Rc refers to ohmic contact resistance and Rch is channel resistance, which indicates that the on-resistance of the device is reduced by the manufacturing method of the present invention.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (5)
1. A preparation method of an InAs/AlSb HEMT device is characterized by comprising the following process steps: 1) growing an epitaxial material; 2) isolating the table top; 3) preparing ohmic contact; 4) preparing a Schottky gate contact; 5) carrying out Pad deposition; 6) passivating;
the specific process comprises the following steps:
1) and (3) epitaxial material growth: the method comprises the steps that by means of an MBE process, a buffer layer (2), an AlSb lower barrier layer (3), an InAs channel layer (4), an AlSb isolating layer (5), a doping layer (6), an AlSb upper barrier layer (7) and an InAlAs hole blocking layer (8) are sequentially grown on a substrate (1);
2) isolating the table top:
(a) cleaning the InAs/AlSb material which grows epitaxially, and then blowing the InAs/AlSb material dry by using nitrogen;
(b) photoetching and etching the cleaned InAs/AlSb material to complete the mesa isolation of the epitaxial material;
3) preparing ohmic contact:
(a) cleaning the InAs/AlSb material subjected to mesa isolation, and then blowing dry the material by using nitrogen;
(b) photoetching a source-drain ohmic region on the surface of the cleaned InAs/AlSb material to manufacture a photoresist mask;
(c) etching the source-drain ohmic region by using inductively coupled plasma etching equipment until the AlSb isolation layer (5) is etched;
(d) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(e) secondarily extending an n-type heavily doped InAs cap layer (9) in a source-drain ohmic region by using an MBE device;
(f) soaking the InAlAs material in photoresist removing solution to remove the photoresist on the upper surface of the InAlAs material and then cleaning the InAlAs material by deionized water;
(g) depositing Pd/Ti/Pt/Au multilayer metal on the heavily doped InAs cap layer (9) of the whole source/drain ohmic region, annealing at the temperature of 300-350 ℃ for 15-30s, forming a source electrode (10) and a drain electrode (11) on the heavily doped InAs cap layer (9), and forming ohmic contact between the source electrode (10) and the drain electrode (11) and the InAs cap layer (9);
4) preparing a Schottky gate contact:
(a) cleaning the device which is subjected to ohmic contact, and then drying the device by using nitrogen;
(b) after cleaning the device which completes ohmic contact, photoetching the gate electrode region on the surface of the InAs/AlSb material to manufacture a photoresist mask;
(c) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(d) performing electron beam evaporation to deposit metal Ti/Pt/Au;
(e) soaking the device in photoresist removing solution, stripping metal except the defined pattern, forming a grid (12) on the InAlAs hole blocking layer (8), and then cleaning with deionized water to complete the manufacture of Schottky grid contact between the grid (12) and the InAlAs hole blocking layer (8);
5) and (4) Pad deposition:
(a) cleaning the device subjected to Schottky gate contact preparation, and then drying by using nitrogen;
(b) after cleaning a device with Schottky gate contact, photoetching in a Pad region on the surface of an InAs/AlSb material to manufacture a photoresist mask;
(c) performing electron beam evaporation to deposit metal Ti/Au;
(d) soaking the photoresist in the photoresist removing solution, stripping the metal except the defined pattern, and cleaning with deionized water;
6) passivation:
(a) cleaning the device, and then drying the device by using nitrogen;
(b) and depositing a silicon nitride passivation layer on the cleaned device by adopting PECVD equipment, thereby completing the preparation of the InAs/AlSb HEMT device.
2. The method of claim 1, wherein the substrate (1) is a GaAs substrate, a Si substrate, or an InP substrate, the buffer layer (2) is a binary, ternary, or quaternary alloy compound of In, Al, Ga, As, and Sb, and the doped layer (6) is Si-doped InAs or Te-doped AlSb.
3. A preparation method of an InAs/AlSb MOS-HEMT device is characterized by comprising the following process steps: 1) growing an epitaxial material; 2) isolating the table top; 3) preparing ohmic contact; 4) preparing an insulated gate; 5) carrying out Pad deposition; 6) passivating;
the specific process comprises the following steps:
1) and (3) epitaxial material growth: the method comprises the steps that by means of an MBE process, a buffer layer (2), an AlSb lower barrier layer (3), an InAs channel layer (4), an AlSb isolating layer (5), a doping layer (6), an AlSb upper barrier layer (7) and an InAlAs hole blocking layer (8) are sequentially grown on a substrate (1);
2) isolating the table top:
(a) cleaning the InAs/AlSb material which grows epitaxially, and then blowing the InAs/AlSb material dry by using nitrogen;
(b) photoetching and etching the cleaned InAs/AlSb material to complete the mesa isolation of the epitaxial material;
3) preparing ohmic contact:
(a) cleaning the InAs/AlSb material subjected to mesa isolation, and then blowing dry the material by using nitrogen;
(b) photoetching a source-drain ohmic region on the surface of the cleaned InAs/AlSb material to manufacture a photoresist mask;
(c) etching the source-drain ohmic region by using inductively coupled plasma etching equipment until the AlSb isolation layer (5) is etched;
(d) soaking the mixture in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s to remove a surface oxidation layer;
(e) secondarily extending an n-type heavily doped InAs cap layer (9) in a source-drain ohmic region by using an MBE device;
(f) soaking the InAlAs material in photoresist removing solution to remove the photoresist on the upper surface of the InAlAs material and then cleaning the InAlAs material by deionized water;
(g) depositing Pd/Ti/Pt/Au multilayer metal on the heavily doped InAs cap layer (9) of the whole source/drain ohmic region, annealing at the temperature of 300-350 ℃ for 15-30s, forming a source electrode (10) and a drain electrode (11) on the heavily doped InAs cap layer (9), and forming ohmic contact between the source electrode (10) and the drain electrode (11) and the InAs cap layer (9);
4) preparing an insulated gate:
(a) cleaning the device which is subjected to ohmic contact, and then drying the device by using nitrogen;
(b) after cleaning the device which completes ohmic contact, photoetching the dielectric layer region on the surface of the InAs/AlSb material to manufacture a photoresist mask;
(c) soaking the substrate in HCl solution obtained by mixing hydrochloric acid with the concentration of 37% and water according to the volume ratio of 1:10 for 15s, removing a surface oxidation layer, and depositing a dielectric layer (13) by adopting ALD (atomic layer deposition);
(d) after the ALD deposition of the dielectric layer is completed, photoetching is carried out on a gate electrode region on the surface of the InAs/AlSb material, and a photoresist mask is manufactured;
(e) depositing metal Ti/Pt/Au on the dielectric layer (13) by electron beam evaporation;
(f) soaking the device in photoresist removing liquid, stripping metal except the defined pattern, forming a grid (12) on the dielectric layer (13), and then cleaning with deionized water to finish the manufacture of the insulated grid;
5) and (4) Pad deposition:
(a) cleaning a device subjected to insulated gate preparation, and then drying by using nitrogen;
(b) after cleaning a device which completes the preparation of the insulated gate, photoetching is carried out on a Pad area on the surface of the InAs/AlSb material, and a photoresist mask is manufactured;
(c) performing electron beam evaporation to deposit metal Ti/Au;
(d) soaking the device in photoresist removing solution, stripping metal except the defined pattern, and cleaning with deionized water;
6) passivation:
(a) cleaning the device, and then drying the device by using nitrogen;
(b) and depositing a silicon nitride passivation layer on the cleaned device by adopting PECVD equipment, thereby completing the preparation of the InAs/AlSb MOS-HEMT device.
4. The method of claim 3, wherein the substrate (1) is a GaAs substrate, a Si substrate or an InP substrate, the buffer layer (2) is a binary, ternary or quaternary alloy compound of In, Al, Ga, As and Sb, and the doped layer (6) is Si-doped InAs or Te-doped AlSb.
5. The method for preparing an InAs/AlSb MOS-HEMT device as claimed in claim 3, wherein the dielectric layer (13) is a high-k dielectric material.
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