CN209843716U - Enhanced AlGaN/GaN MOS-HEMT device structure - Google Patents
Enhanced AlGaN/GaN MOS-HEMT device structure Download PDFInfo
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Abstract
The utility model provides an enhancement mode AlGaN/GaN MOS-HEMT device structure, including Al2O3A substrate sequentially laminated on Al2O3A first intrinsic GaN buffer layer, a second intrinsic GaN buffer layer, a GaN substrate layer, a first buffer layer, a second buffer layer, and a GaN substrate layer,The GaN-based device comprises an AlGaN barrier layer and a GaN cap layer, wherein the GaN cap layer and a GaN substrate layer are etched to form a left source electrode region and a right drain electrode region, metalized ohmic contacts protruding out of the surface of the device are formed on the surfaces of the left source electrode region and the right drain electrode region, a grid oxide layer is formed on the GaN cap layer and a grid region corresponding to the ohmic contact surface, and grid metal is formed on the surface of the grid oxide layer. The device structure provided by the application can improve the reliability of the device, improve the surface density and channel driving current of the 2DEG and reduce the grid leakage current of the device, and the preparation method can be compatible with the process of a main compound semiconductor process, has good substrate quality and high process repeatability, and is easy to manufacture on a large scale.
Description
Technical Field
The utility model relates to the field of semiconductor technology, concretely relates to enhancement mode AlGaN/GaN MOS-HEMT device structure.
Background
Conventional semiconductor materials, represented by silicon (Si) and gallium arsenide (GaAs), have become unable to meet the development of modern electronic technology due to the requirements of radiation resistance, high temperature, high voltage and high power. The wide bandgap semiconductor GaN electronic device can be applied to high temperature, high pressure, high frequency and severe environments, such as radar, base station of wireless communication and satellite communication. GaN is favored in high frequency, high power, high temperature electronic devices because of its large forbidden band width, high breakdown voltage, high electron saturation drift velocity, excellent electrical and optical properties, and good chemical stability. The widespread use of GaN devices promises the advent of the era of optoelectronic and even photonic information. Microelectronic devices are now expanding exponentially, and GaN devices are now used quite widely in military and civilian applications.
With the continuous maturation of the research on the growth process and mechanism of the AlGaN/GaN single heterojunction, the performance of the AlGaN/GaN HEMT device, which is the main structure of the GaN-based HEMT (High Electron Mobility Transistor), has been improved. The mechanisms that have been driven by AlGaN/GaN HEMTs from 1993 to the end of the last century have been mainly the enhancement of heterojunction performance, the gradual evolution and improvement of process technologies (such as mesa etching, schottky contact, and ohmic contact), and the continuous maturation of thermal processing technologies. From 2000 to the present, the properties of AlGaN/GaN heterojunction materials tend to be basically stable, and the performance of AlGaN/GaN HEMTs is improved mainly by the improvement of the process level and the improvement of the device structure. FIG. 1 shows a basic structure of an AlGaN/GaN HEMT which is widely used at present.
The inventor of the utility model finds, through research, that from the process technology point of substrate material preparation, the dislocation density of GaN single crystal grown by the heteroepitaxy technology taking sapphire and silicon carbide (SiC) as the substrate is higher, the performance is not satisfactory, the direct current gain of GaN HBT is still smaller, and the process is not very stable; from the viewpoint of device design and application, the conventional GaN-based HEMT is a depletion type (normally-open type), but power electronic devices are preferably of an enhancement type (normally-closed type), because the difficulty of integrated circuit design can be greatly reduced by offsetting a negative power supply.
In addition, although much effort has been made in the industry to improve the device structure of the enhancement mode AlGaN/GaN HEMT, the threshold voltage of the enhancement mode HEMT device is not significantly increased in practical applications of power conversion. The conventional AlGaN/GaN HEMT has inherent technical defects, such as difficulty in controlling the etching rate, difficulty in manufacturing a conventional concave gate HEMT device, poor process repeatability and poor uniformity of threshold voltage. Meanwhile, the damage of physical etching to the surface of a sample obviously influences the performance of the device, and fluorine ion implantation or plasma treatment generally causes damage and generates defects in a semiconductor material, so that the carrier mobility is reduced, which are technical problems existing in the structural design of the conventional AlGaN/GaN HEMT at present.
SUMMERY OF THE UTILITY MODEL
The utility model provides a be limited to the dislocation density of the GaN single crystal that grows out with the heteroepitaxy technique of sapphire and carborundum as the substrate to prior art is higher, and the performance is still unsatisfactory, and the direct current gain of GaN HBT is still less, and the technological process is not very stable technical problem, the utility model provides an enhancement mode AlGaN/GaN MOS-HEMT device structure.
In order to solve the technical problem, the utility model discloses a following technical scheme:
an enhanced AlGaN/GaN MOS-HEMT device structure comprises Al2O3Substrate of said Al2O3The GaN-based semiconductor device comprises a substrate, a first intrinsic GaN buffer layer, a second intrinsic GaN buffer layer, a GaN substrate layer, an AlGaN barrier layer, a GaN cap layer, a left source electrode region and a right drain electrode region, wherein the first intrinsic GaN buffer layer is formed on the surface of the substrate, the second intrinsic GaN buffer layer is formed on the surface of the first intrinsic GaN buffer layer, the GaN substrate layer is formed on the surface of the second intrinsic GaN buffer layer, the AlGaN barrier layer is formed on the surface of the GaN substrate layer, the GaN cap layer is etched to the GaN substrate layer to form theAnd the surface of the right drain electrode region is provided with a metalized drain electrode ohmic contact protruding out of the surface of the device, the GaN cap layer and the gate electrode region corresponding to the surface of the source drain electrode ohmic contact are provided with a gate electrode oxidation layer, and the surface of the gate electrode oxidation layer is provided with gate metal.
Further, the Al2O3An AlN transition layer is formed between the substrate and the first intrinsic GaN buffer layer.
Further, the thickness of the first intrinsic GaN buffer layer is 2 micrometers, the thickness of the second intrinsic GaN buffer layer is 1 micrometer, the thickness of the GaN substrate layer is 2 micrometers, the thickness of the AlGaN barrier layer is 5nm, and the thickness of the GaN cap layer is 1-2 nm.
Further, the ohmic contact of the left source electrode area and the right drain electrode area is made of aluminum, and the etching depth of the areas is 180 nm.
Further, the thickness of the gate oxide layer is 10 nm.
Further, the thickness of the gate metal is 50 nm.
The utility model also provides an aforementioned enhancement mode AlGaN/GaN MOS-HEMT device structure preparation method, the semiconductor material layer that mentions in the method is unintentional doping, the method includes following step:
s1 cleaning Al by chemical cleaning method2O3Substrate, removing excess oxide, drying, cleaving, and removing Al2O3Growing a first intrinsic GaN buffer layer on the surface of the substrate by using an MOCVD method, wherein the growth temperature is 600-800 ℃, then growing a second intrinsic GaN buffer layer on the surface of the first intrinsic GaN buffer layer, wherein the growth temperature is 300-400 ℃, and then growing a GaN substrate layer on the surface of the second intrinsic GaN buffer layer, wherein the growth temperature is 700 ℃ under constant temperature conditions; then growing an AlGaN barrier layer on the surface of the GaN substrate layer, wherein the typical value of the molar composition of Al in the AlGaN barrier layer is 0.2-0.3, and finally growing a GaN cap layer on the surface of the AlGaN barrier layer;
s2, defining a channel region: spin-coating a layer of positive photoresist on the GaN cap layer, determining the positions of the source electrode and the drain electrode through a mask, then carrying out photoetching, cleaning redundant photoresist, and exposing the source electrode and the drain electrode area to be metalized;
s3, etching the source electrode and the drain electrode region: selectively etching corresponding source electrode and drain electrode regions from the GaN cap layer to the GaN substrate layer, and then soaking the etched material regions in a mixed solution of hydrochloric acid and water at room temperature, wherein the volume ratio of the hydrochloric acid to the water is 1:4, and the soaking time is 1 minute, so as to remove residual oxides on the surface of the GaN substrate layer;
s4, forming metalized ohmic contact on the source electrode and the drain electrode, removing photoresist in the grid electrode area, etching the GaN cap layer until only 1-2 nm is reserved as the cap layer, and enabling the source electrode and the drain electrode to protrude out of the surface of the device to form a surrounding electrode;
s5, annealing the sample in nitrogen at 800 ℃ for 30 seconds, and forming a layer of SiO with the refractive index of 1.5 on the surface of the device by utilizing the PECVD technology at room temperature2A gate oxide layer;
s6 in SiO2A positive photoresist is spin-coated on the grid oxide layer, and then photoetching is carried out to expose a grid region;
s7, removing the photoresist on the two sides of the gate region, and selectively depositing and growing gate metal;
s8, coating positive photoresist on the periphery of the gate metal, and then using hydrogen fluoride solution to etch SiO on two sides of the gate metal2Wet etching is carried out on the grid oxide layer or plasma etching is carried out by using argon plasma to remove SiO on two sides of the grid metal2A gate oxide layer;
and S9, removing the photoresist around the gate region to expose the metal gate, so as to complete the device manufacturing.
Further, the step S1 further includes: the cleaved Al2O3Cleaning the substrate with hydrogen plasma, and adding nitrogen plasma into the reaction chamber to remove Al2O3And nitriding the surface of the substrate to form an AlN transition layer.
Furthermore, in the step S4, the metalized ohmic contact materials of the source electrode and the drain electrode are titanium, aluminum, nickel and gold, and the etching depths corresponding to the source electrode and the drain electrode in the step S3 are 30nm, 180nm, 40nm and 100nm, respectively.
Further, in step S7, the material of the gate metal is titanium or gold, and typical deposition thicknesses are 50nm and 150nm, respectively.
Compared with the prior art, the utility model provides an enhancement mode AlGaN/GaN MOS-HEMT device structure and preparation method thereof has following technical advantage:
1. using sequentially laminated Al2O3The substrate, the first intrinsic GaN buffer layer, the second intrinsic GaN buffer layer and the GaN substrate layer form a device substrate layer structure, the GaN substrate layer is used as an actual substrate of the AlGaN/GaN HEMT, the defect density of the surface of the GaN substrate layer is greatly reduced compared with that of the GaN substrate grown on sapphire or silicon carbide (SiC) in the prior art, the GaN substrate with better surface defect density is obtained, the surface recombination is reduced, and the reliability of the device is improved;
2. two-dimensional electron gas 2DEG is formed at the position, close to the surface of the GaN substrate layer, of the heterojunction interface of the AlGaN barrier layer/the GaN substrate layer, the ability of limiting the 2DEG is improved by utilizing the very thin AlGaN barrier layer, and the area density and the channel driving current of the 2DEG are improved;
3. the extremely thin GaN cap layer is used, the distance between the 2DEG and the surface of the device is increased, the deterioration of the roughness scattering of the surface of the device on the mobility ratio of a channel carrier is avoided, and the grid leakage current of the device is reduced;
4. the grid oxide layer and the grid layer structure are completely consistent with the MOSFET, so that an MOS-HEMT device structure is formed, the inherent technical defects of the conventional concave grid AlGaN/GaN HEMT can be overcome by the structure, the manufacturing process flow of the device is simplified, and the electrical characteristics of the device are improved;
5. the MOS structure is compatible with the mainstream compound semiconductor process and the CMOS process, the structure is simple, the number of material layers is reduced, the substrate quality is good, the process repeatability is high, and the large-scale manufacturing is easy compared with the traditional GaN HEMT device.
Drawings
FIG. 1 shows the basic structure of an AlGaN/GaN HEMT which is widely used at present.
Fig. 2 is a schematic structural diagram of the enhanced AlGaN/GaN MOS-HEMT device provided in the present invention.
Fig. 3a to 3i are schematic cross-sectional structure diagrams of each flow stage of the enhanced AlGaN/GaN MOS-HEMT device structure preparation method provided by the present invention.
Detailed Description
In order to make the technical means, creation features, achievement purposes and functions of the present invention easy to understand and understand, the present invention is further explained by combining with the specific drawings.
In the description of the present invention, it is to be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are merely for convenience of description and to simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
Referring to fig. 2, the present invention provides an enhanced AlGaN/GaN MOS-HEMT device structure, including Al2O3Substrate of said Al2O3The GaN-based light-emitting diode comprises a substrate, a first intrinsic GaN buffer layer, a second intrinsic GaN buffer layer, a GaN substrate layer, an AlGaN barrier layer, a GaN cap layer, a left source electrode region and a right drain electrode region, wherein the first intrinsic GaN buffer layer is formed on the surface of the substrate, the second intrinsic GaN buffer layer is formed on the surface of the first intrinsic GaN buffer layer, the GaN substrate layer is formed on the surface of the second intrinsic GaN buffer layer, the AlGaN barrier layer is formed on the surface of the GaN substrate layer, the GaN cap layer is etched to the GaN substrate layer to form the left source electrode region and the right drain electrode region, a metalized source electrode ohmic contact protruding out of the surface of a device is formed on the surface of the left source electrode region, a metalized drain electrodeAnd a gate metal is formed on the surface of the pole oxide layer.
As a specific example, the Al2O3An AlN transition layer is formed between the substrate and the first intrinsic GaN buffer layer, so that the accumulation and the climbing of lattice dislocation in the first intrinsic GaN buffer layer can be reduced, the material quality and the surface appearance of the first intrinsic GaN buffer layer can be improved, the dislocation density and the surface state can be reduced, and the electrical performance of the device can be improved.
In a specific embodiment, the thickness of the first intrinsic GaN buffer layer is 2 μm, the thickness of the second intrinsic GaN buffer layer is 1 μm, the thickness of the GaN substrate layer is 2 μm, the thickness of the AlGaN blocking layer is 5nm, and the thickness of the GaN cap layer is 1-2 nm, so that the scattering effect of the channel surface can be reduced, the mobility of channel carriers can be improved, the gate capacitance can be reduced, and the control effect of gate voltage on channel charges can be considered.
As a specific embodiment, the ohmic contact of the left source region and the right drain region is made of aluminum, the etching depth of the regions is 180nm, and the thickness is a value which is preferably selected according to the material characteristics of the source and drain metals, and meets the current common process.
As a specific example, the thickness of the gate oxide layer is 10nm, whereby the capacitance of the gate oxide layer can be reduced.
As a specific embodiment, the thickness of the gate metal is 50nm, which is a preferable value according to the material characteristics of the gate metal, and conforms to the current common process.
Referring to fig. 3a to 3i, the present invention further provides a method for manufacturing the aforementioned enhanced AlGaN/GaN MOS-HEMT device structure, wherein the semiconductor material layer mentioned in the method is unintentionally doped, and the method includes the following steps:
s1 cleaning Al by chemical cleaning method2O3Substrate, removing excess oxide, drying, cleaving, and removing Al2O3Growing a High Temperature (HT) first intrinsic GaN buffer layer with a thickness of 2 μm on the surface of the substrate by MOCVD (metal organic chemical vapor deposition)The temperature is 600-800 ℃, then a low-temperature (LT) second intrinsic GaN buffer layer with the thickness of 1 mu m grows on the surface of the first intrinsic GaN buffer layer, the growth temperature is 300-400 ℃, then a GaN substrate layer with the thickness of 2 mu m grows on the surface of the second intrinsic GaN buffer layer at constant temperature, and the growth temperature is 700 ℃, so that the defect density of the surface of the substrate layer is greatly reduced compared with the traditional GaN substrate growing on sapphire or silicon carbide; then growing an AlGaN barrier layer with the thickness of 5nm on the surface of the GaN substrate layer, wherein the typical value of the molar composition of Al in the AlGaN barrier layer is 0.2-0.3, and the thickness of the AlGaN barrier layer is far smaller than the critical thickness of AlGaN, so that two-dimensional electron gas 2DEG is formed at the position, close to the surface of the GaN substrate layer, of the heterojunction interface of the AlGaN barrier layer/GaN substrate layer; because the 2DEG at AlGaN barrier layer/GaN substrate layer heterojunction interface is very close to the surface of GaN substrate layer, and the thickness of AlGaN barrier layer is very thin, therefore the 2DEG receives the scattering effect influence that the AlGaN barrier layer is close to the interface state and the surface roughness of the upper surface of grid very easily, and the carrier mobility of 2DEG reduces greatly under the low temperature condition, and the electrical properties of device receive adverse effect, for this reason, the utility model discloses grow a GaN cap layer that thickness is 20nm on AlGaN barrier layer surface at last, increase the physical distance between device surface and the 2DEG, reduce the interface scattering, this cap layer still can further reduce grid leakage current simultaneously, the layer structure is as shown in FIG. 3 a;
s2, defining a channel region: spin-coating a layer of positive photoresist on the GaN cap layer, determining the positions of the source electrode and the drain electrode through a mask, then carrying out photoetching, cleaning redundant photoresist, exposing the source electrode and the drain electrode area to be metalized, and having a layer structure as shown in FIG. 3 b;
s3, etching the source electrode and the drain electrode region: before forming metalized gate, source and drain ohmic contacts, selectively etching away corresponding source and drain regions, specifically selectively etching away corresponding source and drain regions from the GaN cap layer to the GaN substrate layer, wherein the etching depth is determined by the metal material selected by the ohmic contacts, and the layer structure is shown in FIG. 3 c; then soaking the etched material region in a mixed solution of hydrochloric acid and water at room temperature, wherein the volume ratio of the hydrochloric acid to the water is 1:4, and the soaking time is 1 minute, so as to remove residual oxides on the surface of the GaN substrate layer;
s4, forming metalized ohmic contact on the source electrode and the drain electrode, removing photoresist in the grid electrode area, etching the GaN cap layer until only 1-2 nm is reserved as the cap layer, enabling the source electrode and the drain electrode to protrude out of the surface of the device to form a surrounding electrode, wherein the metalized electrode area is shown in figure 3d, the source electrode and the drain electrode protrude out of the surface of the device at the moment, and thus the surrounding electrode is formed, and the threshold voltage of the device is favorably adjusted;
s5, at 800 ℃, in nitrogen (N)2) Annealing the sample for 30 seconds, and then forming a layer of SiO with a refractive index of about 1.5 and a thickness of 10nm on the surface of the device by using the existing PECVD (plasma enhanced chemical vapor deposition) technology at room temperature2A gate oxide layer having a layer structure as shown in FIG. 3 e;
s6, continuing on SiO2A positive photoresist is spin-coated on the gate oxide layer, and then photolithography is performed to expose the gate region, thereby defining a gate active region, and the layer structure is shown in fig. 3 f;
s7, removing the photoresist on the two sides of the gate region, and selectively depositing and growing gate metal, wherein the layer structure is shown in FIG. 3 g;
s8, coating positive photoresist on the periphery of the gate metal, and then performing subsequent SiO etching2In the etching process of the gate oxide layer, gate metal is protected from being influenced, and physical contact between the gate and the source/drain is isolated; then, using hydrogen fluoride solution to treat SiO on two sides of the grid metal2Wet etching the gate oxide layer or plasma etching with argon (Ar) plasma to remove SiO on both sides of the gate metal2A gate oxide layer having a layer structure as shown in FIG. 3 h;
s9, removing the photoresist around the gate region to expose the metal gate, so that the device is completed, and the complete device structure is shown in fig. 3 i.
As a specific embodiment, please refer to fig. 3a, the step S1 further includes: the cleaved Al2O3The substrate is cleaned by hydrogen plasma, and nitrogen is added into the reaction chamberPlasma of Al2O3And nitriding the surface of the substrate to form an AlN transition layer, wherein the AlN transition layer grows on the AlN transition layer corresponding to the first intrinsic GaN buffer layer.
As a specific embodiment, in step S4, the metalized ohmic contact materials of the source and the drain are titanium, aluminum, nickel, and gold, and the etching depths corresponding to the source and the drain regions in step S3 are 30nm, 180nm, 40nm, and 100nm, respectively. In one embodiment, if the source and drain metalized ohmic contact material is aluminum, the etching depth of the source and drain regions in step S3 is 180 nm.
As a specific example, in step S7, the material of the gate metal is titanium or gold, and typical deposition thicknesses are 50nm and 150nm, respectively.
Compared with the prior art, the utility model provides an enhancement mode AlGaN/GaN MOS-HEMT device structure and preparation method thereof has following technical advantage:
1. using sequentially laminated Al2O3The substrate, the first intrinsic GaN buffer layer, the second intrinsic GaN buffer layer and the GaN substrate layer form a device substrate layer structure, the GaN substrate layer is used as an actual substrate of the AlGaN/GaN HEMT, the defect density of the surface of the GaN substrate layer is greatly reduced compared with that of the GaN substrate grown on sapphire or silicon carbide (SiC) in the prior art, the GaN substrate with better surface defect density is obtained, the surface recombination is reduced, and the reliability of the device is improved;
2. two-dimensional electron gas 2DEG is formed at the position, close to the surface of the GaN substrate layer, of the heterojunction interface of the AlGaN barrier layer/the GaN substrate layer, the ability of limiting the 2DEG is improved by utilizing the very thin AlGaN barrier layer, and the area density and the channel driving current of the 2DEG are improved;
3. the extremely thin GaN cap layer is used, the distance between the 2DEG and the surface of the device is increased, the deterioration of the roughness scattering of the surface of the device on the mobility ratio of a channel carrier is avoided, and the grid leakage current of the device is reduced;
4. the grid oxide layer and the grid layer structure are completely consistent with the MOSFET, so that an MOS-HEMT device structure is formed, the inherent technical defects of the conventional concave grid AlGaN/GaN HEMT can be overcome by the structure, the manufacturing process flow of the device is simplified, and the electrical characteristics of the device are improved;
5. the MOS structure is compatible with the mainstream compound semiconductor process and the CMOS process, the structure is simple, the number of material layers is reduced, the substrate quality is good, the process repeatability is high, and the large-scale manufacturing is easy compared with the traditional GaN HEMT device.
Finally, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the present invention can be modified or replaced by other means without departing from the spirit and scope of the present invention, which should be construed as limited only by the appended claims.
Claims (6)
1. An enhanced AlGaN/GaN MOS-HEMT device structure is characterized by comprising Al2O3Substrate of said Al2O3The GaN-based light-emitting diode comprises a substrate, a first intrinsic GaN buffer layer, a second intrinsic GaN buffer layer, a GaN substrate layer, an AlGaN barrier layer, a GaN cap layer, a left source electrode region and a right drain electrode region, wherein the first intrinsic GaN buffer layer is formed on the surface of the substrate, the second intrinsic GaN buffer layer is formed on the surface of the first intrinsic GaN buffer layer, the GaN substrate layer is formed on the surface of the second intrinsic GaN buffer layer, the AlGaN barrier layer is formed on the surface of the GaN substrate layer, the GaN cap layer and the GaN substrate layer are etched to form the left source electrode region and the right drain electrode region, a metalized source electrode ohmic contact protruding out of the surface of a device is formed on the surface of the left source electrode region, a metalized drain electrode ohmic contact protruding out of the surface.
2. The enhanced AlGaN/GaN MOS-HEMT device structure of claim 1, wherein the Al is2O3An AlN transition layer is formed between the substrate and the first intrinsic GaN buffer layer.
3. The enhanced AlGaN/GaN MOS-HEMT device structure according to claim 1, wherein the first intrinsic GaN buffer layer has a thickness of 2 μm, the second intrinsic GaN buffer layer has a thickness of 1 μm, the GaN substrate layer has a thickness of 2 μm, the AlGaN barrier layer has a thickness of 5nm, and the GaN cap layer has a thickness of 1-2 nm.
4. The enhanced AlGaN/GaN MOS-HEMT device structure according to claim 1, wherein the ohmic contacts of the left source region and the right drain region are made of aluminum, and the region etching depth is 180 nm.
5. The enhanced AlGaN/GaN MOS-HEMT device structure of claim 1, wherein the gate oxide layer has a thickness of 10 nm.
6. The enhanced AlGaN/GaN MOS-HEMT device structure of claim 1, wherein the gate metal has a thickness of 50 nm.
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| CN110600549B (en) * | 2019-10-21 | 2023-12-08 | 重庆麦兜实业有限公司 | Enhanced AlGaN/GaN MOS-HEMT device structure and preparation method thereof |
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Effective date of registration: 20191225 Address after: 401573 No. 500 Jiahe Avenue, Caojie Street, Information Security Industry City, Hechuan District, Chongqing Patentee after: Zhonghe Boxin (Chongqing) Semiconductor Co., Ltd. Address before: 401573 No. 500 Jiahe Avenue, Caojie Street, Hechuan District, Chongqing Patentee before: Zhong Zheng Bo Xin (Chongqing) Semiconductor Co., Ltd. |