CN110634946B - Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof - Google Patents

Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof Download PDF

Info

Publication number
CN110634946B
CN110634946B CN201911032794.9A CN201911032794A CN110634946B CN 110634946 B CN110634946 B CN 110634946B CN 201911032794 A CN201911032794 A CN 201911032794A CN 110634946 B CN110634946 B CN 110634946B
Authority
CN
China
Prior art keywords
layer
gan
gate
metal
algan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911032794.9A
Other languages
Chinese (zh)
Other versions
CN110634946A (en
Inventor
李迈克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boxin Chongqing Semiconductor Research Institute Co ltd
Original Assignee
Zhongzheng Boxin Chongqing Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhongzheng Boxin Chongqing Semiconductor Co ltd filed Critical Zhongzheng Boxin Chongqing Semiconductor Co ltd
Priority to CN201911032794.9A priority Critical patent/CN110634946B/en
Publication of CN110634946A publication Critical patent/CN110634946A/en
Application granted granted Critical
Publication of CN110634946B publication Critical patent/CN110634946B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and a preparation method thereof, comprising the following steps: located at Al 2 O 3 An AlN transition layer over the substrate; a multi-layer buffer structure over the AlN transition layer; an AlGaN barrier layer over the multi-layer buffer structure; a GaN cap layer over the AlGaN barrier layer; a source and a drain located above the first GaN layer and passing upward through the AlGaN barrier layer and GaN cap layer; a gate oxide layer over the GaN cap layer, the source electrode and the drain electrode; and a hetero-gate structure over the gate oxide layer. The invention can improve the channel driving current, flexibly adjust the threshold voltage and prevent the deterioration of channel carrier mobility.

Description

Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof
Technical Field
The invention belongs to the technical field of AlGaN/GaN HEMT devices, and particularly relates to an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and a preparation method thereof.
Background
Traditional semiconductor materials, represented by silicon (Si) and gallium arsenide (GaAs), have been increasingly unable to meet the development of modern electronic technology under the requirements of radiation resistance, high temperature, high voltage and high power. The wide band gap semiconductor GaN electronic device can be applied to high temperature, high voltage, high frequency and severe environments, such as base stations for radar and wireless communication and satellite communication. GaN has a large forbidden bandwidth, high breakdown voltage, high electron saturation drift speed, excellent electrical and optical characteristics and good chemical stability, so that the GaN is favored in high-frequency high-power high-temperature electronic devices and the like. The widespread use of GaN devices is indicative of the advent of the photovoltaic information and even the photonic information age. Microelectronic devices are now expanding in an exponential fashion, and until now GaN devices have been used quite widely both for military and civilian use.
With the continuous maturation of single heterojunction growth process and mechanism research of AlGaN/GaN, the performance of AlGaN/GaN HEMT devices serving as the main structure of GaN-based HEMTs is continuously improved. The mechanisms underlying the push to develop AlGaN/GaNHEMT from 1993 to the end of the last century are mainly the improvement of heterojunction performance, the gradual evolution improvement of process technologies such as mesa etching, schottky contacts and ohmic contacts, and the continued maturation of heat treatment technologies. The performance of the ALGaN/GaN heterojunction material tends to be basically stable since 2000 years ago, and the improvement of the performance of the ALGaN/GaNHEMT device mainly depends on the improvement of the process level and the improvement of the device structure. From the device design and application point of view, the conventional GaN-based HEMT is depletion mode (normally open mode), but the power electronic device is preferably enhanced (normally closed mode), because the difficulty of integrated circuit design can be greatly reduced by counteracting the negative polarity power supply.
Although there have been a great deal of efforts in the industry to improve the device structure of the enhanced AlGaN/GaN HEMT, in practical applications, the effect is not ideal and conventional AlGaN/GaN HEMTs have inherent technical drawbacks. For example, a conventional concave gate HEMT device is difficult to manufacture, has poor process repeatability and poor uniformity of threshold voltage; the use of fluorine ion implantation or plasma treatment typically causes damage and defects in the semiconductor material, thereby reducing carrier mobility, etc.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device capable of improving channel driving current, flexibly adjusting threshold voltage and preventing channel carrier mobility from deteriorating and a preparation method thereof.
An enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device comprising:
an AlN transition layer located over the Al2O3 substrate;
the multilayer buffer structure is positioned above the AlN transition layer, and the uppermost layer of the multilayer buffer structure is a first GaN layer;
the AlGaN barrier layer is positioned on the first GaN layer, and the thickness of the AlGaN barrier layer is 5-10 nm;
a GaN cap layer over the AlGaN barrier layer;
a source and a drain located above the first GaN layer and passing upward through the AlGaN barrier layer and GaN cap layer;
a gate oxide layer over the GaN cap layer, the source electrode and the drain electrode;
the heterogeneous gate structure is positioned above the gate oxide layer and comprises two metal gates with different work functions which are in contact with each other and are arranged in parallel;
the multi-layered buffer structure includes:
a GaN buffer layer over the AlN transition layer;
a low temperature GaN buffer layer located over the GaN buffer layer;
the first GaN layer is positioned on the low-temperature GaN buffer layer;
wherein the low temperature is 300-400 ℃.
Further, the source and drain tips are higher than the GaN cap layer.
A preparation method of an enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device comprises the following steps:
step one: nitriding the upper surface of the cleaned Al2O3 substrate to form an AlN transition layer;
depositing and growing a multi-layer buffer structure on the AlN transition layer, wherein the uppermost layer of the multi-layer buffer structure is a first GaN layer; growing an AlGaN barrier layer with the wavelength of 5-10 nm on the first GaN layer; growing a GaN cap layer on the AlGaN barrier layer;
step two: spin-coating positive photoresist on the GaN cap layer, and exposing the source electrode and drain electrode regions by photoetching;
step three: forming holes for preparing a source electrode and a drain electrode by etching to the first GaN layer;
step four: metal deposition is carried out at the position of the hole to obtain a metalized source electrode and a metalized drain electrode, and ohmic contact is formed; etching the GaN cap layer to 1-2 nm after removing the photoresist and the redundant metal in the grid region;
step five: carrying out high-temperature annealing treatment in nitrogen atmosphere; depositing and growing a layer of silicon dioxide at room temperature to serve as a gate oxide layer;
step six: spin-coating positive photoresist on the gate oxide layer, and exposing a gate region by photoetching;
step seven: depositing and growing a first gate metal layer, covering positive photoresist on the first gate metal layer as a protective layer, exposing a preset second gate metal region through photoetching, and removing the first gate metal layer positioned in the second gate metal region through etching;
step eight: depositing a second gate metal layer with the same thickness as the first gate metal layer on the surface of the device, etching away redundant parts of the two metals and the residual photoresist, and performing chemical mechanical polishing to enable the two metal gate planes to be arranged to form a heterogeneous gate structure;
step nine: positive photoresist is coated on the periphery of the heterogeneous gate structure, and gate oxide layers on two sides of the heterogeneous gate structure are etched;
step ten: removing photoresist around the heterogeneous gate structure to expose the metal gate;
the depositing and growing the multi-layer buffer structure in the first step comprises the following steps:
depositing a GaN buffer layer on the AlN transition layer, wherein the growth temperature is 600-800 ℃;
depositing and growing a low-temperature GaN buffer layer on the GaN buffer layer, wherein the growth temperature is 300-400 ℃;
and depositing and growing a first GaN layer on the low-temperature GaN buffer layer, wherein the growth temperature is 700 ℃ and the constant temperature is adopted.
In particular, etching the gate oxide layers on both sides of the hetero gate structure in the ninth step means:
and carrying out wet etching on the gate oxide layers on two sides of the heterogeneous gate structure through a hydrogen fluoride solution, or carrying out plasma etching on the gate oxide layers on two sides of the heterogeneous gate structure through argon plasma.
In particular, in the fifth step, a silicon dioxide layer is deposited and grown at room temperature to serve as a gate oxide layer, and a plasma enhanced chemical vapor deposition technology is adopted, wherein the refractive index of the silicon dioxide layer reaches 1.5.
Compared with the prior art, the invention has the following beneficial effects:
1. by arranging the AlGaN barrier layer with the thickness far smaller than the critical thickness of AlGaN, the capability of limiting the 2DEG is improved, and the areal density of the 2DEG and the channel driving current are improved;
2. by designing a GaN cap layer below the grid electrode oxide layer above the AlGaN barrier layer, the physical distance between the surface of the device and the 2DEG is increased, the interface scattering is reduced, the deterioration of the roughness scattering of the surface of the device on the channel carrier mobility is avoided, and the grid electrode leakage current can be further reduced;
3. by arranging the heterogeneous gate structure composed of two metal gates with different work functions, which are arranged in parallel in a mutual contact way, the inherent technical defects of the conventional concave gate AlGaN/GaN HEMT can be overcome, the manufacturing process flow of the device is simplified, and the electrical characteristics of the device are improved; different channel potential distributions can be introduced into a 2DEG channel close to an AlGaN/GaN heterojunction interface by flexibly designing the work function difference between the two metals and the work function difference between the GaN cap layer and the channel length corresponding to the two metal gates, so that the threshold voltage of the device is adjusted;
4. by arranging the multi-layer buffer structure consisting of the high-temperature GaN buffer layer, the low-temperature GaN buffer layer and the constant-temperature GaN layer (first GaN layer) on the substrate, the defect density of the surface of the multi-layer buffer structure is greatly reduced compared with that of the traditional GaN substrate grown on sapphire or silicon carbide (SiC), and the reliability of the device can be effectively improved;
5. the source electrode and the drain electrode are protruded out of the surface of the device to form a surrounding electrode, so that the threshold voltage of the device can be adjusted; the junction capacitance of the source drain region is also reduced without reducing the preferred value.
6. By using the MOS structure, the semiconductor structure is compatible with the mainstream compound semiconductor process and CMOS process, and has simple structure; compared with the traditional GaN HEMT device, the material layer number is reduced, the substrate quality is good, the process repeatability is high, and the large-scale manufacturing is easy.
Drawings
FIG. 1 is a schematic diagram of the structure of the preparation method of the present invention after step one;
FIG. 2 is a schematic diagram of the structure of the preparation method of the present invention after step two;
FIG. 3 is a schematic diagram of the structure of the preparation method of the present invention after step three;
FIG. 4 is a schematic diagram of the structure after step four of the preparation method of the present invention;
FIG. 5 is a schematic diagram of the structure of the preparation method of the present invention after step five;
FIG. 6 is a schematic diagram of the structure of the preparation method of the present invention after step six;
FIG. 7 is a schematic diagram of the structure of the preparation method of the present invention after step seven;
FIG. 8 is a schematic diagram of the structure after step eight of the preparation method of the present invention;
FIG. 9 is a schematic diagram of the structure of the preparation method of the present invention after step nine;
FIG. 10 is a schematic diagram of the structure of the device of the present invention;
the semiconductor device comprises a 1-Al2O3 substrate, a 2-AlN transition layer, a 3-multilayer buffer structure, a 31-GaN buffer layer, a 32-low temperature GaN buffer layer, a 33-first GaN layer, a 4-AlGaN barrier layer, a 5-GaN cap layer, a 6-gate oxide layer, a 71-first gate metal layer, a 72-second gate metal layer and 8-photoresist.
Detailed Description
The invention is further described with reference to the following detailed drawings in order to make the technical means, the creation characteristics, the achievement of the purpose and the effect of the implementation of the invention easy to understand.
An enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device, as shown in fig. 10, comprising:
located at Al 2 O 3 An AlN transition layer 2 over the substrate 1;
a multi-layer buffer structure 3 located above the AlN transition layer 2, wherein an uppermost layer of the multi-layer buffer structure 3 is a first GaN layer 33;
an AlGaN barrier layer 4 located on the first GaN layer 33, wherein the thickness of the AlGaN barrier layer 4 is 5-10 nm;
a GaN cap layer 5 on top of the AlGaN barrier layer 4;
source and drain electrodes located above the first GaN layer 33 and passing upward through the AlGaN barrier layer 4 and GaN cap layer 5;
a gate oxide layer 6 located over the GaN cap layer 5, source and drain electrodes;
and the hetero-gate structure is positioned on the gate oxide layer 6 and comprises two metal gates with different work functions which are arranged in parallel in a contact way.
The Al component in the AlGaN barrier layer can be 0.2-0.3, and the thickness of the AlGaN barrier layer is preferably 5nm. The thickness of the GaN cap layer may be 1-2 nm. The ohmic contacts of the source electrode and the drain electrode can be titanium, aluminum, nickel and gold, and typical deposition or etching thicknesses of the four metals can be 30nm, 180nm, 40nm and 100nm respectively. The multi-layer buffer structure means that at least two buffer layers exist in the multi-layer buffer structure. The heterogeneous gate structure in the invention is not limited to two metal gates with different work functions, and three or more metal gates can be arranged in parallel.
First, the thickness of the AlGaN barrier layer is much smaller than the critical thickness of AlGaN, and two-dimensional electron gas (2 DEG) can be better formed at the AlGaN/GaN heterojunction interface near the GaN surface. The scheme utilizes the very thin AlGaN barrier layer, improves the capability of limiting the 2DEG, and improves the area density of the 2DEG and the channel driving current. Secondly, as the 2DEG at the interface of the ALGaN/GaN heterojunction is very close to the surface of GaN, and the thickness of the AlGaN barrier layer is very thin, the 2DEG is easily influenced by the scattering effect of the interface state and the surface roughness of the AlGaN close to the upper surface of the grid electrode, the carrier mobility of the 2DEG is greatly reduced under the low-temperature condition, and the electrical property of the device is adversely affected; therefore, the GaN cap layer is designed on the AlGaN barrier layer, so that the physical distance between the surface of the device and the 2DEG is increased, and the interface scattering is reduced. In addition, the cap layer can further reduce gate leakage current. And the heterogeneous gate structure formed by two metal gates with different work functions which are arranged in parallel in a mutual contact way is arranged, so that the inherent technical defects of the conventional concave gate AlGaN/GaN HEMT can be overcome, the manufacturing process flow of the device is simplified, the electrical characteristics of the device are improved, different channel potential distributions can be introduced into a 2DEG channel close to an AlGaN/GaN heterojunction interface by flexibly designing the work function difference between the two metals and the work function difference between the GaN cap layer and the channel length corresponding to the two metal gates, and the threshold voltage of the device is further adjusted. The selection of the heterogeneous grid metal and the ratio of the channel length are possible, and the design freedom of devices and circuits can be improved.
As an optimized solution, the multi-layer buffer structure includes:
a GaN buffer layer 31 located on the AlN transition layer 2;
a low temperature GaN buffer layer 32 on the GaN buffer layer 31;
the first GaN layer 33 is located above the low temperature GaN buffer layer 32.
In the scheme, a Metal Organic Chemical Vapor Deposition (MOCVD) method is adopted, the growth temperature of the GaN buffer layer can be 600-800 ℃, the growth temperature of the low-temperature GaN buffer layer can be 300-400 ℃, and the growth temperature of the first GaN layer can be 700 ℃ constant temperature.
The scheme is at AI 2 O 3 And firstly, growing a high-temperature GaN buffer layer on the substrate, then, continuously growing a low-temperature GaN buffer layer on the GaN buffer layer, and finally, growing a GaN layer under the constant temperature condition, wherein the GaN layer is used as an actual substrate of the AlGaN/GaN HEMT, and compared with the conventional GaN substrate grown on sapphire or silicon carbide (SiC), the defect density of the surface of the GaN/GaN HEMT is greatly reduced, so that the reliability of the device can be effectively improved.
As an optimized solution, the source and drain tips are higher than the GaN cap layer 5.
The source electrode and the drain electrode in the scheme are protruded out of the surface of the device, so that a surrounding electrode is formed, and the threshold voltage of the device is adjusted. Firstly, the source and drain metal and the GaN cap layer are in the same plane during preparation, and the GaN cap layer needs to be etched and thinned in the process, and the optimal value of the source and drain metal is not expected to be reduced, so that the source and drain can protrude out of the GaN cap layer. Secondly, the thickness of the source drain metal is equal to the sum of the protruding portion and the embedded portion, so that not only is the preferred value reduced, but also the junction capacitance of the source drain region is reduced.
The invention also discloses a preparation method of the enhanced heterogeneous metal gate ALGaN/GaN MOS-HEMT device, as shown in figures 1-10, comprising the following steps:
step one: in the cleaned Al 2 O 3 Nitriding the upper surface of the substrate 1 to form an AlN transition layer 2;
depositing and growing a GaN buffer layer 31 on the AlN transition layer 2, wherein the growth temperature is 600-800 ℃;
depositing and growing a low-temperature GaN buffer layer 32 on the GaN buffer layer 31, wherein the growth temperature is 300-400 ℃;
depositing and growing a first GaN layer 33 on the low-temperature GaN buffer layer 32, wherein the growth temperature is 700 ℃ constant;
growing an AlGaN barrier layer 4 of 5-10 nm on the first GaN layer 33;
growing a 20nm GaN cap layer 5 on the AlGaN barrier layer 4;
step two: spin-coating a positive photoresist 8 on the GaN cap layer 5, exposing source and drain regions (defining a channel region) by photolithography;
step three: forming holes for preparing a source electrode and a drain electrode by etching to the first GaN layer 33;
step four: metal deposition is carried out at the position of the hole to obtain a metalized source electrode and a metalized drain electrode, and ohmic contact is formed; etching the GaN cap layer 5 to 1-2 nm after removing the photoresist 8 and the redundant metal in the gate region;
step five: carrying out high-temperature annealing treatment in nitrogen atmosphere; depositing a grown silicon dioxide layer at room temperature as a gate oxide layer 6;
step six: a positive photoresist 8 is spin-coated on the gate oxide layer 6, and a gate region (defining a gate active region) is exposed through photoetching;
step seven: depositing and growing a first gate metal layer 71 (the gate metal is usually titanium or gold is preferred), covering positive photoresist 8 on the first gate metal layer 71 as a protective layer, exposing a preset second gate metal region through photoetching, and removing the first gate metal layer 71 positioned in the second gate metal region through etching;
step eight: depositing a second gate metal layer 72 with the same thickness as the first gate metal layer 71 on the surface of the device, completely etching away the redundant parts of the two metals and the residual photoresist 8, and performing chemical mechanical polishing to enable the two metal gate planes to be arranged to form a heterogeneous gate structure;
step nine: positive photoresist 8 is coated on the periphery of the heterogeneous gate structure, and gate oxide layers on two sides of the heterogeneous gate structure are etched;
step ten: and removing the photoresist 8 around the heterogeneous gate structure to expose the metal gate.
Step one, cleaning Al by a chemical cleaning method 2 O 3 Removing redundant oxide on the substrate, drying and cleaving,
further cleaning the cleaved substrate with hydrogen plasma, and simultaneously adding nitrogen plasma into the reaction chamber to perform Al treatment 2 O 3 The surface of the substrate is nitrided to form an AlN transition layer. A thicker intrinsic GaN buffer layer with the thickness of about 2 mu m can be generated on the transition layer by utilizing a Metal Organic Chemical Vapor Deposition (MOCVD) method, and the growth temperature is controlled between 600 and 800 ℃; then continuously growing a second layer of intrinsic GaN buffer layer at low temperature, wherein the thickness of the second layer of intrinsic GaN buffer layer is about 1 mu m, and the growth temperature is controlled at 300-400 ℃; finally, growing a GaN substrate with the thickness of about 2 mu m at the constant temperature of 700 ℃, and growing a AlGaN thin layer which can be 5-10 nm as a barrier layer on the GaN substrate.
The depth of the etching in the third step is determined by the metal material selected for the ohmic contact. The ohmic contacts of the source electrode and the drain electrode can be titanium, aluminum, nickel and gold, and typical deposition or etching thicknesses of the four metals are 30nm, 180nm, 40nm and 100nm respectively; for example, if aluminum is selected for the source and drain, the source drain region etch depth is 180nm.
The annealing temperature in the fifth step may be 800 ℃, and the annealing time may be 30 seconds. The silicon dioxide layer deposited and grown at room temperature can be used as a gate oxide layer, and a plasma enhanced chemical vapor deposition technology can be adopted. The refractive index of the silicon dioxide layer reaches 1.5, and the thickness is 10nm. Since the refractive index of common silicon dioxide is generally between 1.1 and 1.2, and the refractive index is related to uniformity, the refractive index reaching 1.5 is required in the scheme to enable the silicon dioxide film to have higher uniformity and compactness and smaller interface state.
The protection layer is provided in the seventh step to ensure that the portion of the first gate metal layer to be remained is not affected by the process when the second gate metal layer is deposited. And etching a corresponding length L2 in the first layer of gate metal layer according to the designed channel length corresponding to the second gate metal layer, wherein the length of the remaining first layer of gate metal layer is L1. If the channel length between the source and the drain is L, l1+l2=l needs to be satisfied.
In the step nine, the etching can be performed by wet etching on the gate oxide layers on two sides of the heterogeneous gate structure through a hydrogen fluoride solution, and also can be performed by plasma etching through argon plasma.
For example, if titanium (Ti) is used as the first gate metal layer, gold (Au) may be used as the second gate metal layer, the work function of titanium is 4.33eV, and the work function of gold is 5.1eV, which have a significant difference.
The invention adopts the MOS structure, is compatible with the mainstream compound semiconductor process and CMOS process, and has simple structure; compared with the traditional GaN HEMT device, the material layer number is reduced, the substrate quality is good, the process repeatability is high, and the large-scale manufacturing is easy.
The foregoing is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the foregoing embodiment, and all technical solutions belonging to the principles of the present invention are within the protection scope of the present invention. Modifications which would occur to those skilled in the art without departing from the principles of the invention are also intended to be included within the scope of the invention.

Claims (5)

1. An enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device, comprising:
located at Al 2 O 3 AlN overpass over substrateA transition layer;
the multilayer buffer structure is positioned above the AlN transition layer, and the uppermost layer of the multilayer buffer structure is a first GaN layer;
the AlGaN barrier layer is positioned on the first GaN layer, and the thickness of the AlGaN barrier layer is 5-10 nm;
a GaN cap layer over the AlGaN barrier layer;
a source and a drain located above the first GaN layer and passing upward through the AlGaN barrier layer and GaN cap layer;
a gate oxide layer over the GaN cap layer, the source electrode and the drain electrode;
the heterogeneous gate structure is positioned above the gate oxide layer and comprises two metal gates with different work functions which are in contact with each other and are arranged in parallel;
the multi-layered buffer structure includes:
a GaN buffer layer over the AlN transition layer;
a low temperature GaN buffer layer located over the GaN buffer layer;
the first GaN layer is positioned on the low-temperature GaN buffer layer;
wherein the low temperature is 300-400 ℃.
2. The enhancement-mode hetero-metal gate AlGaN/GaN MOS-HEMT device of claim 1, wherein:
the source and drain tips are higher than the GaN cap layer.
3. The preparation method of the enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device is characterized by comprising the following steps:
step one: in the cleaned Al 2 O 3 Nitriding the upper surface of the substrate to form an AlN transition layer;
depositing and growing a multi-layer buffer structure on the AlN transition layer, wherein the uppermost layer of the multi-layer buffer structure is a first GaN layer; growing an AlGaN barrier layer with the wavelength of 5-10 nm on the first GaN layer; growing a GaN cap layer on the AlGaN barrier layer;
step two: spin-coating positive photoresist on the GaN cap layer, and exposing the source electrode and drain electrode regions by photoetching;
step three: forming holes for preparing a source electrode and a drain electrode by etching to the first GaN layer;
step four: metal deposition is carried out at the position of the hole to obtain a metalized source electrode and a metalized drain electrode, and ohmic contact is formed; etching the GaN cap layer to 1-2 nm after removing the photoresist and the redundant metal in the grid region;
step five: carrying out high-temperature annealing treatment in nitrogen atmosphere; depositing and growing a layer of silicon dioxide at room temperature to serve as a gate oxide layer;
step six: spin-coating positive photoresist on the gate oxide layer, and exposing a gate region by photoetching;
step seven: depositing and growing a first gate metal layer, covering positive photoresist on the first gate metal layer as a protective layer, exposing a preset second gate metal region through photoetching, and removing the first gate metal layer positioned in the second gate metal region through etching;
step eight: depositing a second gate metal layer with the same thickness as the first gate metal layer on the surface of the device, etching away redundant parts of the two metals and the residual photoresist, and performing chemical mechanical polishing to enable the two metal gate planes to be arranged to form a heterogeneous gate structure;
step nine: positive photoresist is coated on the periphery of the heterogeneous gate structure, and gate oxide layers on two sides of the heterogeneous gate structure are etched;
step ten: removing photoresist around the heterogeneous gate structure to expose the metal gate;
the depositing and growing the multi-layer buffer structure in the first step comprises the following steps:
depositing a GaN buffer layer on the AlN transition layer, wherein the growth temperature is 600-800 ℃;
depositing and growing a low-temperature GaN buffer layer on the GaN buffer layer, wherein the growth temperature is 300-400 ℃;
and depositing and growing a first GaN layer on the low-temperature GaN buffer layer, wherein the growth temperature is 700 ℃ and the constant temperature is adopted.
4. The method for manufacturing an enhanced hetero-metal gate AlGaN/GaN MOS-HEMT device according to claim 3, wherein etching the gate oxide layers on both sides of the hetero-gate structure in step nine means:
and carrying out wet etching on the gate oxide layers on two sides of the heterogeneous gate structure through a hydrogen fluoride solution, or carrying out plasma etching on the gate oxide layers on two sides of the heterogeneous gate structure through argon plasma.
5. The method for manufacturing the enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device according to claim 3, wherein the method comprises the following steps: and fifthly, depositing and growing a silicon dioxide layer at room temperature to serve as a gate oxide layer, wherein the refractive index of the silicon dioxide layer reaches 1.5 by adopting a plasma enhanced chemical vapor deposition technology.
CN201911032794.9A 2019-10-28 2019-10-28 Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof Active CN110634946B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911032794.9A CN110634946B (en) 2019-10-28 2019-10-28 Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911032794.9A CN110634946B (en) 2019-10-28 2019-10-28 Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof

Publications (2)

Publication Number Publication Date
CN110634946A CN110634946A (en) 2019-12-31
CN110634946B true CN110634946B (en) 2023-04-28

Family

ID=68977903

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911032794.9A Active CN110634946B (en) 2019-10-28 2019-10-28 Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN110634946B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158274A (en) * 2005-12-08 2007-06-21 Toyota Motor Corp Method for manufacturing semiconductor device, and method for manufacturing semiconductor substrate
CN102169900A (en) * 2011-03-01 2011-08-31 清华大学 Tunnelling field effect transistor based on work function of heterogeneous gate and forming method of tunnelling field effect transistor
CN102169901A (en) * 2011-03-01 2011-08-31 清华大学 Tunneling field effect transistor having heterogeneous grid work function and formation method thereof
CN102629627A (en) * 2012-04-16 2012-08-08 清华大学 Heterogeneous gate tunneling transistor and forming method thereof
CN103094347A (en) * 2013-01-11 2013-05-08 南京邮电大学 Carbon nano tube field effect tube of double-material underlap heterogeneous grid structure
CN210073863U (en) * 2019-10-28 2020-02-14 中证博芯（重庆）半导体有限公司 Enhanced type heterogeneous metal gate AlGaN/GaN MOS-HEMT device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2002357640A1 (en) * 2001-07-24 2003-04-22 Cree, Inc. Insulting gate algan/gan hemt
CN103026491B (en) * 2010-07-06 2016-03-02 香港科技大学 Normal turn-off type III-nitride metal-two-dimensional electron gas tunnel junctions field-effect transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158274A (en) * 2005-12-08 2007-06-21 Toyota Motor Corp Method for manufacturing semiconductor device, and method for manufacturing semiconductor substrate
CN102169900A (en) * 2011-03-01 2011-08-31 清华大学 Tunnelling field effect transistor based on work function of heterogeneous gate and forming method of tunnelling field effect transistor
CN102169901A (en) * 2011-03-01 2011-08-31 清华大学 Tunneling field effect transistor having heterogeneous grid work function and formation method thereof
CN102629627A (en) * 2012-04-16 2012-08-08 清华大学 Heterogeneous gate tunneling transistor and forming method thereof
CN103094347A (en) * 2013-01-11 2013-05-08 南京邮电大学 Carbon nano tube field effect tube of double-material underlap heterogeneous grid structure
CN210073863U (en) * 2019-10-28 2020-02-14 中证博芯（重庆）半导体有限公司 Enhanced type heterogeneous metal gate AlGaN/GaN MOS-HEMT device

Also Published As

Publication number Publication date
CN110634946A (en) 2019-12-31

Similar Documents

Publication Publication Date Title
CN110190116B (en) High-threshold-voltage normally-off high-electron-mobility transistor and preparation method thereof
US10367074B2 (en) Method of forming vias in silicon carbide and resulting devices and circuits
JP5313424B2 (en) III-nitride based field effect transistor (FET) with reduced trapping and method of manufacturing the transistor
CN110112215B (en) Power device with gate dielectric and etching blocking function structure and preparation method thereof
CN109004017B (en) HEMT device with polarization junction longitudinal leakage current barrier layer structure and preparation method thereof
CN111463260B (en) Vertical high electron mobility field effect transistor and preparation method thereof
CN108305834B (en) Preparation method of enhanced gallium nitride field effect device
WO2022116915A1 (en) Semiconductor device, and application and manufacturing methods therefor
CN110600549B (en) Enhanced AlGaN/GaN MOS-HEMT device structure and preparation method thereof
JP5520432B2 (en) Manufacturing method of semiconductor transistor
CN112420850A (en) Semiconductor device and preparation method thereof
CN116169169A (en) Enhanced GaN HEMTs with low gate leakage current and preparation method thereof
CN210073863U (en) Enhanced type heterogeneous metal gate AlGaN/GaN MOS-HEMT device
WO2022127512A1 (en) High electron mobility transistor, preparation method, and power amplifier/switch
CN111509042A (en) MIS structure GaN high electron mobility transistor and preparation method thereof
CN113555429B (en) Normally open HFET device with high breakdown voltage and low on-resistance and method of making same
CN110634946B (en) Enhanced heterogeneous metal gate AlGaN/GaN MOS-HEMT device and preparation method thereof
CN110890423A (en) High-voltage gallium nitride power device structure and preparation method thereof
CN116092935A (en) Manufacturing method of AlGaN/GaN HEMT device
CN209843716U (en) Enhanced AlGaN/GaN MOS-HEMT device structure
CN107195670B (en) GaN-based enhanced MOS-HEMT device and preparation method thereof
CN111463259B (en) High electron mobility field effect transistor and preparation method thereof
US20230290834A1 (en) ENHANCEMENT-MODE GaN HFET
CN111739800B (en) Preparation method of SOI-based concave gate enhanced GaN power switch device
CN112018177B (en) Full-vertical Si-based GaN UMOSFET power device and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20230524

Address after: Room 1 # -1, 9th Floor, Building 1, No. 19, Fortune Avenue, Yubei District, Chongqing (Building A, Fortune 3), 401120

Patentee after: Boxin (Chongqing) Semiconductor Research Institute Co.,Ltd.

Address before: No. 500 Jiahe Avenue, Caojie Street, Hechuan District, Chongqing, 401520

Patentee before: ZHONGZHENG BOXIN (CHONGQING) SEMICONDUCTOR Co.,Ltd.

TR01 Transfer of patent right