CN113990948A - Semiconductor device and application and manufacturing method thereof - Google Patents
Semiconductor device and application and manufacturing method thereof Download PDFInfo
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- CN113990948A CN113990948A CN202111423723.9A CN202111423723A CN113990948A CN 113990948 A CN113990948 A CN 113990948A CN 202111423723 A CN202111423723 A CN 202111423723A CN 113990948 A CN113990948 A CN 113990948A
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Classifications
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The invention discloses a semiconductor device and an application and manufacturing method thereof, wherein the semiconductor device comprises: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; the gate dielectric layer is arranged on the barrier layer; the drain electrode is arranged on the gate dielectric layer and is in contact with the channel layer; the source electrode is arranged on the gate dielectric layer and is in contact with the channel layer; the grid electrode is arranged on the grid dielectric layer and is positioned between the source electrode and the drain electrode; and one end of the field plate is connected with the grid dielectric layer and positioned between the source electrode and the drain electrode, and the other end of the field plate extends out of the grid dielectric layer and extends towards the upper part of the grid electrode. Through the semiconductor device provided by the invention, the breakdown voltage of the semiconductor device can be increased.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and an application and manufacturing method thereof.
Background
Gallium nitride as a wide bandgap semiconductor has the characteristics of high breakdown electric field, high electron saturation velocity and mobility, so that the gallium nitride-based power device can be used for preparing a new generation of high-power converter, and the existing gallium nitride-based power device is a transverse heterojunction AlGaN/GaN high-electron-mobility transistor device. And the silicon substrate has the advantages of large size and low cost, a buffer layer is formed between the gallium nitride base and the substrate to improve the lattice mismatch and the thermal expansion coefficient mismatch between the substrate and the gallium nitride base, and the buffer layer is subjected to carbon doping to inhibit the lateral punch-through of the semiconductor device. But because the interfaces of the semiconductor layers with different materials have defects, the formed semiconductor device has higher leakage current and leakage voltage.
Disclosure of Invention
The invention aims to provide a semiconductor device and an application and a manufacturing method thereof.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a semiconductor device, which at least comprises:
a substrate;
a channel layer disposed on the substrate;
a barrier layer disposed on the channel layer;
the gate dielectric layer is arranged on the barrier layer;
the drain electrode is arranged on the gate dielectric layer and is in contact with the channel layer;
the source electrode is arranged on the gate dielectric layer and is in contact with the channel layer;
the grid electrode is arranged on the grid dielectric layer and is positioned between the source electrode and the drain electrode; and
one end of the field plate is connected with the grid dielectric layer and is positioned between the source electrode and the drain electrode, and the other end of the field plate extends out of the grid dielectric layer and extends towards the upper part of the grid electrode.
Optionally, the field plate includes:
one end of the first sub-field plate is arranged on the gate dielectric layer, and the other end of the first sub-field plate extends towards the opposite side of the substrate; and
one end of the second sub-field plate is connected with the other end of the first sub-field plate, the other end of the second sub-field plate extends towards one side of the grid, and the orthographic projection of the second sub-field plate covers a part of the grid.
Optionally, the other end of the first sub-field plate is higher than the gate.
Optionally, the gate dielectric layer is a silicon nitride layer.
Optionally, the semiconductor device further includes:
a first dielectric layer disposed on the gate dielectric layer; and
a second dielectric layer disposed on the gate electrode.
Optionally, the first dielectric layer and the gate are arranged at the same height.
Optionally, the first dielectric layer is disposed between the first sub-field plate and the gate, and the second dielectric layer is disposed between the second sub-field plate and the gate.
Optionally, a groove is disposed between the first sub-field plate and the gate, and the groove is located between the first sub-field plate and a portion of the first dielectric layer.
Optionally, a preset distance is provided between the second sub-field plate and the second dielectric layer.
The present invention also provides a method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a channel layer on the substrate;
forming a barrier layer on the channel layer;
forming a gate dielectric layer on the barrier layer;
and forming a source electrode, a drain electrode and a grid electrode on the grid dielectric layer. And the source electrode and the drain electrode are in contact with the channel layer, and the gate electrode is located between the source electrode and the drain electrode.
And forming a field plate on the gate dielectric layer, wherein one end of the field plate is connected with the gate dielectric layer and is positioned between the source electrode and the drain electrode, and the other end of the field plate extends out of the gate dielectric layer and extends towards the upper part of the gate electrode.
The invention also provides an electronic device comprising the semiconductor device
According to the semiconductor device and the application and manufacturing method thereof provided by the invention, the field plate extending into the gate dielectric layer is closer to the two-dimensional electron gas channel, so that the surface electric field distribution can be better adjusted, and the width of a depletion region is expanded. And the air bridge embedded source field plate arranged in a 7 shape enables the semiconductor device to support higher breakdown voltage. And the leakage current of the semiconductor device with the air bridge embedded source field plate is reduced, the parasitic capacitance between the grid and the drain is hardly increased, and the high-frequency characteristic is kept. With the help of the air bridge embedded source field plate, the semiconductor device can have a breakdown voltage of up to several hundred volts and has the ability to operate at high frequencies.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 to 6 are process diagrams of a semiconductor device.
Fig. 7 to 11 are process diagrams of manufacturing the semiconductor device with the drain surrounded by the gate.
Fig. 12 is a top view of fig. 11.
Fig. 13 to 15 are process diagrams of manufacturing a semiconductor device having a metal electrode pad.
Fig. 16-18 are process diagrams of semiconductor device fabrication with air bridge embedded source field plate.
Fig. 19 is a schematic view of a semiconductor device structure having multiple passivation layers.
Fig. 20 to 33 are process diagrams of manufacturing a semiconductor device.
Fig. 34 is a flow chart of cleaning gallium nitride epitaxy.
Fig. 35 is a flow chart of cleaning the etched gallium nitride epitaxy.
Fig. 36 is a diagram of an apparatus for processing an AlGaN/GaN semiconductor structure using a supercritical gas.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 33, the semiconductor device or the monolithically integrated semiconductor device according to the present invention includes a substrate 100, an epitaxial structure disposed on the substrate 100, and a source 107, a drain 108 and a gate 109 disposed on the epitaxial structure. Wherein the epitaxial structure includes a heterostructure formed of gallium nitride and aluminum gallium nitride (GaN/AlGaN). And in the present application, the semiconductor device is, for example, a semiconductor power device.
Referring to fig. 1, in an embodiment of the invention, the substrate 100 may be a silicon substrate, such as silicon (Si) or silicon carbide (SiC). In other embodiments, the substrate 100 may also be sapphire (Al)2O3) Gallium arsenide (GaAs), lithium aluminate (LiAlO)2) Gallium nitride (GaN), or other semiconductor substrate materials. After the substrate 100 is formed, a buffer layer 101 may be formed between the substrate 100 and the epitaxial structure by a chemical vapor deposition method or a metal organic chemical vapor deposition method to improve lattice matching between the substrate 100 and the epitaxial structure, and the material of the buffer layer 101 may be, for example, one or more of gallium nitride, aluminum gallium nitride, or aluminum nitride. In the embodiment, the buffer layer 101 is, for example, an aluminum nitride buffer layer, and the thickness of the buffer layer 101 is, for example, 1-4um, specifically, 1 um.
Referring to fig. 1, in an embodiment of the invention, the epitaxial structure includes a channel layer 102 disposed on a buffer layer 101, and a barrier layer 103 disposed on the channel layer 102. Channel layer 102 is disposed on buffer layer 101, and for example, 3-6um gallium nitride may be grown on buffer layer 101 to form channel layer 102. In the present embodiment, the thickness of the channel layer 102 is, for example, 4 um. The barrier layer 103 is formed on the channel layer 102, the barrier layer 103 is, for example, an aluminum gallium nitride layer, and the material of the barrier layer 103 is, for example, Al0.23Ga0.77And N is added. And the thickness of the barrier layer 103 is, for example, 20 to 30nm, specifically, 25nm, for example. In this embodiment, a gate opening 1041 is further disposed on the barrier layer 103 for depositing the gate 109. In the present embodiment, the channel layer 102 and the barrier layer 103 may be prepared by a chemical vapor deposition method or a metal organic chemical vapor deposition method.
Referring to fig. 1 to 33, in an embodiment of the present invention, an epitaxial structure with gallium nitride/aluminum gallium nitride (GaN/AlGaN) and a semiconductor device manufactured by the epitaxial structure are provided. In the manufacturing process, multiple cleaning is required to improve the surface roughness and the epitaxial defects, so that the stability of the metal contact resistance and the reliability of the GaN device are ensured. First, after the channel layer 102 made of gallium nitride is formed, silicon-based gallium nitride epitaxial wafers may be cleaned, and deionized water may be used to clean the silicon-based gallium nitride epitaxial wafers several times to remove large particles attached to the surfaces of the gallium nitride. Specifically, for example, the gallium nitride epitaxial wafer may be subjected to, for example, two deionized water rinses.
Referring to fig. 1 to 34, in an embodiment of the invention, after forming the aluminum gallium nitride barrier layer 103 and before growing a gate dielectric layer such as silicon nitride, the surface of the barrier layer 103 is cleaned to eliminate the interface defect on the AlGaN/SiNx surface. First, RCA cleaning is performed, specifically, for example, steps S10-S15 are performed, and for example, 2% hydrofluoric acid (HF) is used to clean for example 100S, then ultrapure water is used to clean for example 600S, and then the first solution SC1 is used to clean for 600S. Wherein the first solution SC1 is made of, for example, water (H)2O) and hydrogen peroxide (H)2O2) And ammonia (NH)4OH) in a certain proportion, and the proportion of each component in the first solution is H2O：H2O2：NH4OH ═ 5: 1: 1. after the first solution SC1 was washed, for example, 600s was washed again using ultrapure water, followed by washing for example 600s using the second solution SC 2. Wherein the second solution SC2 is, for example, a solution consisting of water (H)2O) and hydrogen peroxide (H)2O2) Mixing with hydrochloric acid (HCl) at a certain ratio, and the second solution SC2 contains components at a certain ratio such as H2O：H2O2: HCl ═ 6: 1: 1. surface ion and organic contamination can be removed through the first solution SC1 and the second solution SC2, and the roughness of the surface of the epitaxial structure is improved. And after the cleaning using the second solution SC2, the cleaning may be performed again using ultrapure water for, for example, 600 s. After the RCA cleaning, for example, steps S16 to S18 are performed, for example, cleaning is performed for 100 seconds using, for example, 2% hydrofluoric acid (HF), cleaning is performed for 600 seconds using, for example, ultrapure water, and spin-drying is performed. The epitaxial surface of the gallium nitride can be ensured not to be cleaned by hydrogen peroxide (H) by using hydrofluoric acid (HF) solution again2O2) The solution had residual oxides.
Referring to fig. 1-35, in an embodiment of the present invention, after etching the channel layer 102 and the barrier layer 103, for example, after forming a gate opening, a source opening, or a drain opening, the etched region may be cleaned. Specifically, as shown in step S20 to step S25 in fig. 35, for example, isopropyl alcohol (IPA) may be used to clean for example 600S first, and then ultrapure water may be used to clean for example 600S. After which it may be cleaned with propanol (ACE) for e.g. 600s and then with ultra pure water for e.g. 600 s. Finally, 2% hydrofluoric acid (HF) is used for cleaning for 100s, and ultrapure water is used for cleaning for 600s, and drying is carried out.
Referring to fig. 2 to 3, in an embodiment of the invention, a gate dielectric layer may be further disposed in the semiconductor device to reduce the threshold voltage hysteresis. Specifically, in the present embodiment, the gate dielectric layer includes a passivation layer 105 and an oxide layer 106 disposed on the barrier layer 103, and the passivation layer 105 is, for example, an aluminum nitride layer disposed on the barrier layer 103. In the present embodiment, the passivation layer 105 is deposited by Plasma Enhanced Atomic Layer Deposition (PEALD). The oxide layer 106 is, for example, an aluminum oxide layer disposed on the aluminum nitride layer, and is deposited by Atomic Layer Deposition (ALD), for example, and the passivation layer 105 and the oxide layer 106 cover the barrier layer 103 and the gate opening 1041 on the barrier layer 103. The thickness of the passivation layer 105 is, for example, 1 to 5nm, and may be, for example, 2 nm. The thickness of the oxide layer 106 is, for example, 5 to 10nm, specifically, 8 nm. And after the oxide layer 106 is formed, the passivation layer 105 and the oxide layer 106 are exposed to N2Ambient and temperature conditions such as 300-.
As shown in fig. 2 to fig. 6, since the AlN material of the passivation layer 105 has a higher forbidden bandwidth and a higher thermal conduction efficiency, the blocking capability of the gate dielectric against the leakage current and the quality of the interface with the gan can be improved. When the forbidden band width and the conduction band offset are large, electrons can be restrained from passing through the dielectric layer, and the grid leakage condition is reduced. Because aluminum nitride and gallium nitride have good lattice matching and thermal conductivity characteristics, the aluminum nitride in the passivation layer 105 is in direct contact with the gallium nitride, which can improve the quality of the interface. Meanwhile, in the present embodiment, aluminum nitride and aluminum oxide are used as the gate insulating dielectric, and the aluminum nitride layer formed by PEALD can reduce the interface defect between the oxide layer 106 and the gallium nitride, reduce the leakage current of the gate 109, and improve the stability and reliability of the gate 109, so that the semiconductor device has a lower threshold voltage hysteresis. The phenomenon of threshold voltage hysteresis caused by the fact that deep level traps exist at the interface of the oxidation layer 106 and the barrier layer 103 to trap channel electrons under a larger forward gate voltage can be avoided, and therefore the stability of the threshold voltage is improved.
Referring to fig. 1, 5 to 6, after the passivation layer 105 and the oxide layer 106 are formed, a source electrode 107, a gate electrode 109 and a drain electrode 108 are formed, respectively. The source 107 and drain 108 are located on either side of the gate opening 1041 and are in contact with the barrier layer 103. The gate 109 is located in the interface and contacts the oxide layer 106. In this embodiment, both sides of the passivation layer 105 and the oxide layer 106 may be etched to the barrier layer 103, and the metal Ti/Al/Ni/Au may be deposited on the barrier layer 103 on both sides of the passivation layer 105 and the oxide layer 106, respectively, to form the source electrode 107 and the drain electrode 108. Where Ti/Al/Ni/Au is indicated herein, the gate 103 includes a titanium metal layer, an aluminum metal layer disposed on the titanium metal layer, a nickel metal layer disposed on the aluminum metal layer, and a gold metal layer disposed on the nickel metal layer. The subsequent writing method is the same as that in the present embodiment, and will not be described in detail later. After forming the source 107 and drain 108, nitrogen (N) may be used2) Ambient and temperature conditions such as 750-. In the present embodiment, as shown in fig. 5, the source 107 and the drain 108 may be as high as the oxide layer 106. As shown in fig. 6, the source 107 and the drain 108 are higher than the oxide layer 106. After the source 107 and the drain 108 are formed, Ni/Au metal is deposited on the oxide layer 106 in the gate opening 1041 and on the oxide layer 106 at two sides of the gate opening 1041 to form the gate 109, and the cross section of the gate 109 may be in a symmetrical "T" shape. In the present embodiment, the distance between the source 107 and the gate 109 is, for example, 2-3um, and specifically, for example, 2.5 um. The distance between the gate 109 and the drain 108 is, for example, 14-15um, specifically, 14.5 um. The width of the gate 109 is, for example, 3-4um, specifically, 3 um. The source 107 and the drain 108 may be as high as the gate dielectric layer, or may be as high as the gate dielectric layer and as high as the gate 109. Since the barrier layer 103 at the bottom of the gate 109 in this embodiment is completely etched, the threshold voltage is not sensitive to the etching depth, and the electric field inside the gan is weak when the device is turned off, which further reduces the hysteresis of the threshold voltage.
Referring to FIGS. 7-12, another embodiment of the present inventionIn an embodiment, there is also provided a semiconductor device having a ring-shaped gate electrode, which can suppress a leakage current. In the present embodiment, for example, aluminum nitride is deposited on a silicon substrate 100 as a buffer layer 101, and a gallium nitride layer is deposited on the buffer layer 101 as a channel layer 102, and an aluminum gallium nitride forming barrier layer 103 is deposited on the channel layer 102. The material of the barrier layer 103 is specifically, for example, Al0.25Ga0.75And N is added. After the formation of the GaN/AlGaN heterostructure, silicon nitride (Si) is deposited on the barrier layer 103 to a thickness of, for example, 25-35nm3N4) As the gate dielectric layer 110, a specific thickness of the silicon nitride layer is, for example, 30 nm. And the silicon nitride can simultaneously serve as a surface passivation layer. After the gate dielectric layer 110 is formed, Cl is used on the outside of the gate dielectric2/BCl3The plasma etches toward the substrate 100 side, forming isolation trenches 118. And the gate dielectric layer 110 and the barrier layer 103 are etched away to the surface of the channel layer 102, and the channel layer 102 with a part of thickness can also be etched away, so as to ensure that the barrier layer 103 is completely etched. So that the gate dielectric layer 110 and the barrier layer 103 in the middle of the etching form a mesa structure.
Referring to fig. 9, in the present embodiment, after forming the mesa structure, a passivation layer 119 is formed on the mesa structure and the isolation trench 118, and the passivation layer 119 covers the surface of the gate dielectric layer 110 and fills a portion of the isolation trench 118, which can be used for planarization. Specifically, for example, a layer of 400-600nm silicon dioxide (SiO) can be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD)2) To form a passivation layer 119. The thickness of the passivation layer 119 is, for example, 500 nm.
Referring to fig. 9 to 12, in the present embodiment, after the passivation layer 119 is formed, a source opening, a drain opening and a gate opening are formed on the passivation layer 119. Wherein the source opening is used for depositing metal to form the source 107, the drain opening is used for depositing metal to form the drain 108, and the gate opening is used for depositing metal to form the source 107. In the present embodiment, the source opening is located at one side of the passivation layer 119 and near the isolation trench 118. The drain opening is located on the other side of the passivation layer 119 and near the central region of the passivation layer 119 to ensure the formation of the ring-shaped gate 109. The gate opening is disposed around the drain opening and has a predetermined distance from the isolation trench 118. And the source opening and the drain opening are etched into channel layer 102 and contact channel layer 102, and the gate opening is etched into gate dielectric layer 110 and contact gate dielectric layer 110.
Referring to fig. 9-12, in the present embodiment, after forming the source opening and the drain opening, Ti/Al/Ti/TiN metal is deposited in the source opening to form the source 107, and Ti/Al/Ti/TiN metal is deposited in the drain opening to form the drain 108. After forming the source 107 and the drain 108, a gate opening is formed by etching, and a metal TiN is deposited in the gate opening to form the gate 109, and a plurality of electrodes may be deposited by Physical Vapor Deposition (PVD). The source 107 is disposed on one side of the gate 109, and the gate 109 is disposed around the drain 108. The gate 109 channel surrounding the drain 108 can suppress leakage current because leakage current not provided around the ring gate 109 includes gate 109 to source 107 leakage current, mesa edge to source 107 leakage current, and gate 109 surrounded region to source 107 leakage current. After the gate 109 surrounding the drain 108 is provided, the high voltage applied to the drain 108 can be cut off by the channel of the gate 109, so that the mesa edge outside the gate 109 and the region surrounded by the gate 109 can be protected from the high voltage of the drain 108, thereby eliminating the leakage current caused by the high voltage at the mesa edge and the isolation region, realizing ultra-low leakage current and high on/off drain 108 current ratio, and further protecting the semiconductor device from the damage of the high leakage voltage.
Referring to fig. 12, in the present embodiment, the source 107 and the drain 108 are disposed in a rectangular shape, and the gate 109 is disposed in a rectangular ring shape. The source 107 and the gate 109 have a first distance L1. The gate 109 is equidistant from the drain 108 on opposite sides of the drain 108. The gate 109 and the drain 108 have a second distance L2 in a connecting direction of the source 107 and the drain 108, and the gate 109 and the drain 108 have a third distance L3 in a connecting direction perpendicular to the source 107 and the drain 108. In the present embodiment, the first distance L1 is greater than the second distance L2 and the third distance L3, and the second distance L2 is equal to the third distance L3. The voltage between the gate 109 and the drain 108 can be balanced, ensuring the quality of the formed semiconductor device. In other embodiments, the source 107 and drain 108 are arranged in a circular configuration and the gate 109 is arranged in a circular ring. Alternatively, the source 107 and the drain 108 are disposed in an elliptical shape, and the gate 109 is disposed in an elliptical ring shape. The present invention does not limit the specific shapes of the source 107, the drain 108, and the gate 109 as long as the drain 108 and the gate 109 disposed outside the drain 108 correspond in shape.
Referring to fig. 13-15 in combination with fig. 7-12, in one embodiment of the present invention, a plurality of layers of different electrode materials may be used, and a metal pad is formed on the electrode, so that the electrode has low contact resistance, a flat surface and good thermal stability. In this embodiment, a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, a gate dielectric layer 110, an isolation trench 118 formed by etching the barrier layer 103 and the gate dielectric layer 110, and a passivation layer 119 are sequentially disposed on the substrate 100. In the present embodiment, the source 107 and the drain 108 are located on two sides of the mesa structure and are respectively connected to the channel layer 102. The gate 109 is located between the source 107 and the drain 108 and close to the source 107, and the gate 109 is connected to the gate dielectric layer 110. And the source 107, the drain 108 and the gate 109 in this embodiment are disposed at the same height as the passivation layer 119.
Referring to fig. 13 to 14, in the present embodiment, the source 107 and the drain 108 are made of Ti/Al/Ti/TiN, and the gate 109 is made of TiN. Namely, the source electrode 107 and the drain electrode 108 include a first titanium metal layer 1072 in contact with the channel layer 102 and the barrier layer 103, an aluminum metal layer 1073 on the first titanium metal layer 1072, a second titanium metal layer 1074 on the aluminum metal layer 1073, and a titanium nitride layer 1075 on the first titanium metal layer 1072. In the annealing process, titanium metal on the channel layer 102 and the barrier layer 103 reacts with nitrogen atoms out-diffused by aluminum gallium nitride to form titanium nitride (TiN), the chemical property of the TiN is stable, upper metal with a work function larger than that of the TiN can be prevented from being diffused to the surface of AlGaN, and meanwhile, N vacancies left in the AlGaN play a role of shallow donors, so that the doping concentration of the AlGaN can be improved, and ohmic contact can be formed more easily. The aluminum metal layer 1073 covers the first titanium metal layer 1072 and serves as a catalyst to promote the reaction of Ti with N atoms, and the aluminum metal layer 1073 itself can be bonded with N to form a stable AlN compoundAnd an alloy having a low work function can be formed with Ti. For example, an AlTi alloy, such as TiAl, may be formed between first Ti-metal layer 1072, Al-metal layer 1073, and second Ti-metal layer 10743. The titanium nitride layer 1075 on the second titanium metal layer 1074 can be used as a conductive material such as an electrode and an electrical contact, and the thickness of the titanium nitride is 20nm, for example.
Referring to fig. 13 to 15, in the present embodiment, after the source electrode 107, the drain electrode 108 and the gate electrode 109 are formed, a layer of SiO material is deposited on the passivation layer 1192/Si3N4/SiO2The composite dielectric layer 120 is passivated. After the composite dielectric layer 120 is formed. A plurality of windows are formed on the source 107, the drain 108 and the gate 109 by using Inductively Coupled Plasma (ICP) or Reactive Ion Etching (RIE) and the like, and the windows penetrate through the composite dielectric layer 120. When the window is formed by etching the composite dielectric layer 120, the titanium nitride layer 1075 can be completely removed by using methods such as physical bombardment plasma etching and the like because the titanium nitride layer 1075 is thin, and the appearance of the window formed by etching can be ensured to be smooth enough. After forming the window, metal is deposited within the window, and on both sides of the window, to form a metal pole pad. And the metal pad includes a first metal pad 121 located above the source 107 and connected to the source 107. And a second metal pad 122 located above the drain 108 and connected to the drain 108. And a third metal pad 123 over the gate 109 and connected to the gate 109. The metal electrode pad is made of chemically stable metal. In the present embodiment, the metal electrode pad has a symmetrical "T" shape, for example.
Referring to fig. 13 to 15, in the present embodiment, the titanium nitride on the source 107 and the drain 108 is etched away when the metal pad is formed. Can avoid the formation of TiAl3When alloyed, TiN does not take part in the reaction of the alloy, so that in TiAl3There is a boundary between the alloy and TiN, resulting in TiAl3And the contact resistance between the electrode and TiN is higher, so that the contact resistance of the electrode is further reduced. And a metal pad is formed above the electrode to increase the contact area, to have a flat surface and to have good heatAnd (4) stability.
Referring to fig. 16 to 18, in another embodiment of the present invention, a semiconductor device having a field plate is further provided to increase the breakdown voltage of the drain region without increasing the parasitic capacitance. In the present embodiment, the semiconductor device includes a substrate 100, an epitaxial structure on the substrate 100, a plurality of electrodes connected to the epitaxial structure, and a field plate 125 disposed on the gate electrode 109.
Referring to fig. 16, in the present embodiment, a buffer layer 101 is disposed on a substrate 100, and the material of the buffer layer 101 is, for example, aluminum nitride. A channel layer 102 is provided on the buffer layer 101, and a material of the channel layer 102 is, for example, gallium nitride. A barrier layer 103 is provided on the channel layer 102, and the material of the barrier layer 103 is, for example, aluminum gallium nitride. A gate dielectric layer 110 is disposed on the barrier layer 103, and the gate dielectric layer 110 is made of, for example, silicon nitride. In other embodiments, a layer of gallium nitride may also be deposited as a capping layer on barrier layer 103.
Referring to fig. 16-18, in the present embodiment, after forming the gate dielectric layer 110, a plurality of openings may be formed on the gate dielectric layer 110, and the gate dielectric layer 110 and the barrier layer 103 are etched away to reach the channel layer 102 during the etching of the openings. And to ensure that the barrier layer 103 at the opening is completely etched, a portion of the channel layer 102 may be etched away. And metal is deposited in the openings in a stacked arrangement to form source 107, drain 108 and gate 109. For example, a source opening and a drain opening may be formed on both sides of the gate dielectric layer 110, and metal Ti/Al/Ni/Au may be deposited in the source opening and the drain opening to form the source 107 and the drain 108. After forming the source 107 and drain 108, the semiconductor device is filled with N at, for example, 800-2For example, 45 to 50 seconds, and the temperature may be, for example, 870 ℃, and the time for the rapid heat treatment may be, for example, 50 seconds. Then, an opening is formed between the source electrode 107 and the drain electrode 108 by using electron beam lithography or reactive ion dry etching (RIE), and metal Ni/Au is deposited in the opening to form the gate electrode 109. In the present embodiment, a source 107, a drain 108, and a gate 109 are in contact with the channel layer 102. Source 107, drain 108 and 109 are higher than the gate dielectric layer 110 and are arranged at the same height. The top of the gate electrode 109 extends to both sides of the opening to form the gate electrode 109.
Referring to fig. 16 to 18, in the present embodiment, after forming the source 107, the drain 108 and the gate 109, a dielectric layer 124 is formed between the source 107 and the gate 109, between the drain 108 and the gate 109, and on top of the gate 109. The dielectric layer 124 may be formed by depositing a silicon nitride layer on the gate dielectric layer 110 between the source 107 and the gate 109, between the drain 108 and the gate 109, and on top of the gate 109, for example, by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method at a temperature of, for example, 250-300 ℃. In the present embodiment, for example, the dielectric layer 124 between the source 107 and the gate 109 and between the drain 108 and the source 107 is defined as a first dielectric layer 1241, and the dielectric layer 124 above the gate 109 is defined as a second dielectric layer 1242. The first dielectric layer 1241 is disposed at the same height as the gate 109, and the second dielectric layer 1242 is located above the gate 109 and extends to both sides of the gate 109, and covers a portion of the first dielectric layer 1241 to form an isolation structure between the formed field plate 125 and the gate 109.
Referring to fig. 16 to 18, in the present embodiment, after forming the dielectric layer 124, a groove 126 is formed between the gate 109 and the drain 108, and a metal Ni/Au is deposited on one side of the groove 126 and above the groove 126 to form a field plate 125. The field plate 125 is disposed, for example, in a 7-shape, and is close to the gate 109. In the present embodiment, for convenience of description, the field plate 125 is divided into a first subfield plate 1251 and a second subfield plate 1252, and the field plate 125 in the growth direction of the semiconductor device is defined as the first subfield plate 1251, for example, and the field plate 125 in the vertical direction to the growth direction of the semiconductor device is defined as the second subfield plate 1252, for example.
Referring to fig. 16 to 18, in the present embodiment, after the dielectric layer 124 is formed, the second dielectric layer 1242 is etched toward the substrate 100 at a side close to the drain 108. And the second dielectric layer 1242, the first dielectric layer 1241 and the gate dielectric layer 110 with a predetermined thickness are etched away to form the recess 126. In this embodiment, a gate dielectric layer 110, a first dielectric layer 1241 and a second dielectric layer 1242 with a predetermined width are further disposed between the recess 126 and the gate 109 for forming an isolation structure. After forming the groove 126, metal is evaporated on one side of the groove 126 and on the groove 126 to form the field plate 125. The first subfield-board 1251 is located at the side of the recess 126 remote from the isolation structure and the width of the first subfield-board 1251 is for example 1/2-3/5 of the width of the recess 126. In this embodiment the width of the first subfield-board 1251 is e.g. 1/2 of the width of the groove 126. The first sub-field plate 1251 is disposed in the growth direction of the semiconductor device, and one end of the first sub-field plate 1251 extends into the gate dielectric layer 110 and the other end extends toward the growth direction of the semiconductor device and is higher than the second dielectric layer 1242. One end of the second subfield board 1252 is connected to the other end of the first subfield board 1251 and the other end of the second subfield board 1252 extends towards the gate 109 and ends above the gate 109. Specifically, the other end of the second subfield plate 1252 is located above the central region of the gate electrode 109, for example. The second subfield-board 1252 is perpendicular to the first subfield-board 1251 and parallel to the plane in which the second dielectric layer 1242 lies. Since one end of the first sub-field plate 1251 is higher than the second dielectric layer 1242, the second sub-field plate 1252 has a predetermined distance from the second dielectric layer 124.
Referring to fig. 16 to 18, in the present embodiment, the field plate 125 extending into the gate dielectric layer 110 is closer to the two-dimensional electron gas channel, so that the surface electric field distribution can be better adjusted and the depletion region width can be expanded. And the air bridge embedded source field plate arranged in a 7 shape enables the semiconductor device to support higher breakdown voltage. And the leakage current of the semiconductor device having the air bridge embedded source field plate is reduced and the parasitic capacitance between the gate electrode 109 and the drain electrode 108 is hardly increased, maintaining the high frequency characteristic. With the help of the air bridge embedded source field plate, the semiconductor device can have a breakdown voltage of up to several hundred volts and has the ability to operate at high frequencies.
Referring to fig. 19, in an embodiment of the invention, a semiconductor device with improved breakdown performance is provided. In the present embodiment, the substrate 100 is, for example, a silicon substrate, and is, for example, made of nonpolar silicon Si (111). A buffer layer 101 is provided on the substrate 100 and is doped, for exampleCarbon gallium nitride, and channel layer 102 is disposed on buffer layer 101, for example, a non-doped gallium nitride layer. Barrier layer 103 is disposed on channel layer 102 and is, for example, a non-doped aluminum gallium nitride layer. After the barrier layer 103 is formed, mesa etching is performed on the edge of the barrier layer 103. For example, BCl can be used3Reactive Ion Etching (RIE) of the gas etches the epitaxial structure to form isolation trenches outside the semiconductor devices to achieve isolation between adjacent semiconductor devices. After the isolation groove is formed by etching, the substrate can be cleaned by using isopropanol, acetone and ultrapure water.
Referring to fig. 19, in the present embodiment, after forming the isolation trench, silicon nitride (SiNx) is deposited on the barrier layer 103 and in the isolation trench to form a gate dielectric layer 110. And gate dielectric layer 110 covers the isolation trench. After the gate dielectric layer 110 is formed, a layer of tetraethyl orthosilicate (TEOS) is deposited on the gate dielectric layer 110 to form a first passivation layer 1301. The thickness of the first passivation layer 1301 is, for example, 8 to 12um, and specifically, for example, 9um, 10um, or 11 um. After the first passivation layer 1301 is formed, the first passivation layer 1301, the gate dielectric layer 110 and a partial thickness of the barrier layer 103 are etched on both sides near the isolation trench to form a source opening and a drain opening. Wherein the source opening and the drain opening extend into the barrier layer 103 and the barrier layer 103 at the bottom of the openings has a thickness of, for example, 3-5 nm. Ti/Al/Ti/TiN is deposited in the source and drain openings and on the first passivation layer 1301 by sputtering, and then patterned by dry etching to form the source electrode 107 and the drain electrode 108. In the present embodiment, the source 107 and the drain 108 extend to two sides of the source opening and the drain opening, respectively, to form the source 107 and the drain 108 with T-shaped cross sections. After the source 107 and drain 108 are formed, annealing may be performed at 800-900 deg.C for 30-50 seconds in a nitrogen atmosphere to ensure good ohmic contact. After annealing, the first passivation layer 1301 is etched on the first passivation layer 1301, and on a side thereof adjacent to the source 107, forming a gate opening. And the bottom of the gate opening contacts gate dielectric layer 110. TiN/Ti/Al is deposited in the gate opening and then patterned by dry etching to form gate 109. In this embodiment, the gate electrode 109 extends toward both sides of the gate opening to form the gate electrode 109 having a T-shaped cross section.
Referring to fig. 19, in the present embodiment, after forming the source electrode 107, the drain electrode 108 and the gate electrode 109, a layer of Tetraethylorthosilicate (TEOS) is deposited on the source electrode 107, the drain electrode 108 and the gate electrode 109 to form a second passivation layer 1302. The thickness of the second passivation layer 1302 is, for example, 2-6um, and specifically, for example, 3um or 4 um. A second passivation layer 1302 covers the source electrode 107, the drain electrode 108, and the gate electrode 109. An opening is formed in the second passivation layer 1302 and above the source 107 and the drain 108, respectively. A metal Ti/Al/Ti/TiN is deposited in the opening and on the second passivation layer 1302 to form a first field plate 131 connected to the source electrode 107 and a second field plate 132 connected to the drain electrode 108. The first field plate 131 is located in the opening on the source electrode 107 and extends toward the side of the gate 109, and the orthographic projection of the first field plate 131 on the first passivation layer 1301 covers the gate 109. The second field plate 132 is located in the opening on the drain electrode 108, extends toward the side of the gate electrode 109, and has a predetermined distance from the first field plate 131.
Referring to fig. 19, in the present embodiment, after the first field plate 131 and the second field plate 132 are formed, silicon nitride (SiNx) is deposited on the first field plate 131 and the second field plate 132 to form a third passivation layer 1303, and the third passivation layer 1303 covers the first field plate 131 and the second field plate 132. And the thickness of the third passivation layer 1303 is, for example, 2-5um, specifically, 3um, for example. On the third passivation layer 1303, the first and second windows 133 and 134 are etched. Wherein a first window 133 is disposed over the source electrode 107 and communicates with the first field plate 131. A second aperture 134 is disposed over the drain 108 and communicates with the second field plate 132. After the third passivation layer 1303 is formed, it is located at N at a temperature of, for example, 400 ℃ and 450 DEG C2/H2And carrying out alloy annealing treatment in the atmosphere.
Referring to fig. 19, in the present embodiment, after the third passivation layer 1303 is formed, polyimide (polyimide) is coated on the third passivation layer 1303, so as to form a protection layer 1304. The polyimide has the relative dielectric constant of 3.1-3.5, the breakdown field strength of more than 200KV/mm, good mechanical properties, good adhesion, corrosion resistance, high temperature resistance, irradiation resistance and better planarization performance. Meanwhile, the passivation layer formed by the silicon nitride and the polyimide can bear mechanical stress caused by the filler during plastic packaging, and the passivation layer is prevented from cracking and metal deformation.
Referring to fig. 19, in the present embodiment, a layer of polyimide may be coated on the third passivation layer 1303 by using dynamic spin coating. After the photoresist is applied, the passivation layer 1304 may be exposed and developed to form a patterned passivation layer 1304. For example, the polyimide on the first window 133 and the second window 134 may be exposed and removed by using ultraviolet light, deep ultraviolet light, or an electron beam, and the polyimide in the unexposed area is dissolved by using an oil solution, thereby forming the patterned protection layer 1304. In the present embodiment, the protective layer 1304 exposes the first window 133 and the second window 134. After the patterned protective layer 1304 is formed, the protective layer 1304 is post-baked to improve the adhesion of the polyimide. The baking temperature is 50-800 deg.C, and the baking time is 30s-1 h. After post-baking, the protective layer 1304 is cured, so that the surface density of the protective layer 1304 can be improved, and defects can be avoided or reduced. The curing process is a heating curing process, and the temperature of the heating curing process is, for example, 100 ℃ to 150 ℃, and the time is, for example, 30 to 100 seconds. The density of the solidified protective layer 1304 is high, and the traps on the surface of the passivation layer are passivated by the protective layer 1304, so that the situation that the field plate has more traps and charges on the surface or in the body of the medium, and a local high electric field is generated at the edge of the metal field plate to generate high-energy carriers to cause an avalanche effect, and further the whole semiconductor device is broken down, can be avoided.
Referring to fig. 20 to 33, in an embodiment of the present invention, a semiconductor device is further provided, which can suppress leakage current and improve the quality of the semiconductor device. Specifically, referring to fig. 20 to 24, in the present embodiment, an aluminum nitride buffer layer 101 is disposed on a silicon substrate 100, a gallium nitride channel layer 102 is disposed on the aluminum nitride buffer layer 101, a barrier layer 103 is disposed on the channel layer 102, and the barrier layer 103 is made of, for example, aluminum gallium nitride. A gallium nitride layer 127 is deposited on barrier layer 103 and gallium nitride layer 127 is etched to form patterned gallium nitride layer 127. Wherein the patterned gan structure is, for example, annular gan layers 127 to form the drain 108 between the annular gan layers 127. After patterned gallium nitride layer 127 is formed, a silicon nitride layer is deposited on gallium nitride layer 127, forming first passivation layer 1301. A source opening 1043 and a drain opening 1044 are etched in the first passivation layer 1301, wherein the source opening 1043 is located on one side of the annular gallium nitride layer 127 and the drain opening 1044 is located in the annular gallium nitride layer 127. And while etching the source opening 1043 and the drain opening 1044, the first passivation layer 1301 and the barrier layer 103 are etched away such that the bottom of the source opening 1043 and the drain opening 1044 are in contact with the channel layer 102. A Ti/Al/Ti/TiN metal layer is deposited within source opening 1043 and drain opening 1044 to form source 107 and drain 108, with drain 108 centered on annular gallium nitride layer 127.
Referring to fig. 24 to 29, in the present embodiment, after the source 107 and the drain 108 are formed, silicon nitride (SiN) is deposited on the source 107, the drain 108 and the first passivation layer 1301 to form a first insulating layer 1371. Over the gan layer 127, the first insulating layer 1371 is etched to form a gate 109 opening. In etching the gate 109 opening, the first insulating layer 1371 and the first passivation layer 1301 above the gallium nitride layer 127 are etched away, so that the gate 109 opening is in contact with the gallium nitride layer 127. A metal layer of TiN/Ti/Al is deposited within the gate 109 opening to form gate 109. The gate 109 fills the opening of the gate 109, extends outward of the gan ring, and covers a portion of the first insulating layer 1371. After the gate 109 is formed, silicon oxide (SiO2) is deposited over the gate 109 and the first insulating layer 1371, forming a second insulating layer 1372. Titanium nitride (TiN) is deposited on the second insulating layer 1372 to form a first field plate 1381, and the first field plate 1381 covers a portion of the gate 109 except for the portion above the gan.
Referring to fig. 30 to 31, in the present embodiment, after forming the first field plates 1381, silicon oxide (SiO2) is deposited on the first field plates 1381 and on the second insulating layer 1372, and Chemical Mechanical Polishing (CMP) is performed on the silicon oxide layer to form the flat third insulating layer 1373. An opening is etched through the third, second and first insulating layers 1373, 1372 and 1371 above the drain 108 and source 107, and tungsten is deposited in the opening to form drain conductive plug 1391 and source conductive plug 1392. And metallic aluminum is deposited on drain conductive plug 1391, source conductive plug 1392, and third insulating layer 1373 between drain conductive plug 1391 and source conductive plug 1392 to form a second field plate. And the second field plate comprises a first sub-field plate 1383 connected to drain conductive plug 1391, a second sub-field plate 1384 connected to source conductive plug 1392, and a third sub-field plate 1385 arranged between first sub-field plate 1383 and second sub-field plate 1384, and third sub-field plate 1385 covers first field plate 1381 between source 107 and drain 108.
Referring to fig. 31 to 33, in the present embodiment, after forming the second field plate, a layer of silicon nitride (SiNx) is deposited on the second field plate and the third insulating layer 1373 to form the second passivation layer 1302. And an opening is etched through second passivation layer 1302 and metal tungsten is deposited in the opening over second sub-field plate 1384 and third sub-field plate 1385 to form first conductive plug 1394 connected to second sub-field plate 1384 and second conductive plug 1395 connected to third sub-field plate 1385. And metallic aluminum is deposited on the second passivation layer 1302 to form a third field plate. And the third field plate comprises a fourth sub-field plate 1386 and a fifth sub-field plate 1387, wherein the fourth sub-field plate 1386 is on and connected to the first conductive plug 1394 and the fifth sub-field plate 1387 is on and connected to the second conductive plug 1395. Finally, a layer of polyimide (polyimide) is deposited over the first and second conductive plugs 1394 and 1395 and the second passivation layer 1302 to form a protective layer 1303.
Referring to the semiconductor devices shown in fig. 1-33, when aluminum gallium nitride is deposited on the gallium nitride channel layer to form the barrier layer, an AlGaN/GaN heterostructure may be formed. The interface of the AlGaN/GaN heterostructure can produce a high mobility two-dimensional electron gas (2DEG) for fabricating power switching transistors with very low on-resistance. After forming the AlGaN/GaN heterostructure, supercritical CO can be used on the AlGaN/GaN heterostructure2And processing to improve the AlGaN/GaN heterojunction interface to show lower defect state density and gate leakage current.
As shown in fig. 36, in the figure,in the present embodiment, for example, gaseous CO is introduced2The phase change from gaseous to supercritical fluid is accomplished by delivery from gas cylinder 12 to high pressure pump 11 at a pressure of, for example, 3000 pounds per square inch (psi). Placing the AlGaN/GaN heterostructure in a reaction chamber 10, and introducing carbon dioxide and H in a supercritical state into the reaction chamber 102O and treated at, for example, 150 c for, for example, 3 hours. During the reaction, CO is generated2Double bond structure with large activation energy and stable chemical property in supercritical CO2The treatment process does not participate in reaction, and the defects are repaired mainly by supplementing dangling bonds, so that the density of interface defect states is reduced. In this embodiment, H2Decomposition of O into H+And OH-And H generated by OH bond cleavage when a negative bias is applied+. Due to supercritical CO2Has strong solubility and penetrability, and H generated by the reaction+Will pass through supercritical CO2Into the sample. In the supercritical state, H+Ga vacancies can be filled. By H+After the defects are repaired, the vacancy caused by unmatched AlGaN and GaN crystal lattices can be repaired, and then the AlGaN/GaN interface is repaired. Thereby improving the problems of low defect state density and gate leakage current at the AlGaN/GaN heterojunction interface.
Referring to the semiconductor devices shown in fig. 7 to 12 and 13 to 15, when silicon nitride (SiNx) is deposited on the AlGaN/GaN heterostructure, after the silicon nitride is deposited, the lattice mismatch between GaN and SiNx has a plurality of dangling bonds and a plurality of N vacancies. Electrons of a grid electrode and two-dimensional electron gas in a channel are easily trapped by interface state defects, the interface state defects positioned under the grid electrode can cause unstable threshold voltage, and the interface state defects positioned in a grid leakage area can deplete channel electrons to increase dynamic resistance. In the present embodiment, the AlGaN/GaN heterostructure provided with the silicon nitride layer may use super-critical CO2And (5) processing to improve the interface defect of SiNx/GaN.
Referring to FIG. 36, in the present embodiment, for example, gaseous CO is introduced2The phase change from gaseous to supercritical fluid is accomplished by delivery from gas cylinder 12 to high pressure pump 11 at a pressure of, for example, 3000 pounds per square inch (psi). Placing the AlGaN/GaN heterostructure provided with the silicon nitride layer in a reaction chamber 10, and introducing carbon dioxide and H in a supercritical state into the reaction chamber 102O, with, for example, 1g of Mg in the reaction chamber 103N2Mixed and treated at, for example, 120 c, for example, for 1 hour.
Referring to FIG. 36, in the present embodiment, during the reaction process, CO is generated2Double bond structure with large activation energy and stable chemical property in supercritical CO2The reaction is not involved in the treatment process. In this embodiment, Mg3N2And H2O undergoes the following reaction:
Mg3N2+H2O→Mg(OH)2+NH3。
referring to FIG. 36, due to supercritical CO2Has strong solubility and penetrability, and NH generated by reaction3Will pass through supercritical CO2Into the SiNx/GaN interface and as NH3Molecular dissolution in supercritical CO2Supercritical NH3Combined with excess dangling bonds and N vacancies to form NH2. Deamination takes place in the adjacent NH2The reaction is as follows:
NH2 -+NH2 -+NH2 -→N3+3H2。
in the supercritical fluid treatment process, amination and deamination reactions are dynamically carried out in the reaction chamber 10, and finally complete Si-N bonds and Ga-N bonds are formed in the SiNx/GaN interface and the dielectric layer, and N vacancies are filled, so that traps of the SiNx/GaN interface can be improved. By supercritical CO2By processing, the trap quantity of the SiNx/GaN interface is reduced, so that the problem of device reliability caused by the fact that grid electrons or two-dimensional electron gas are trapped by the trap can be avoided, and the quality of a formed semiconductor device can be improved.
Referring to fig. 1 to 36, the epitaxial structure and the semiconductor device formed by the epitaxial structure provided in the present invention may be applied to various semiconductor structures, electronic components or electronic devices, such as a switch device, a power device, a radio frequency device, a light emitting diode, a micro light emitting diode, a display panel, a mobile phone, a watch, a notebook computer, a projection device, a charging pile, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a portable electronic device, a game machine or other electronic devices.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (11)
1. A semiconductor device, characterized in that it comprises at least:
a substrate;
a channel layer disposed on the substrate;
a barrier layer disposed on the channel layer;
the gate dielectric layer is arranged on the barrier layer;
the drain electrode is arranged on the gate dielectric layer and is in contact with the channel layer;
the source electrode is arranged on the gate dielectric layer and is in contact with the channel layer;
the grid electrode is arranged on the grid dielectric layer and is positioned between the source electrode and the drain electrode; and
one end of the field plate is connected with the grid dielectric layer and is positioned between the source electrode and the drain electrode, and the other end of the field plate extends out of the grid dielectric layer and extends towards the upper part of the grid electrode.
2. The semiconductor device of claim 1, wherein the field plate comprises:
one end of the first sub-field plate is arranged on the gate dielectric layer, and the other end of the first sub-field plate extends towards the opposite side of the substrate; and
one end of the second sub-field plate is connected with the other end of the first sub-field plate, the other end of the second sub-field plate extends towards one side of the grid, and the orthographic projection of the second sub-field plate covers a part of the grid.
3. The semiconductor device according to claim 2, wherein the other end of the first sub-field plate is higher than the gate.
4. The semiconductor device of claim 1, wherein the gate dielectric layer is a silicon nitride layer.
5. The semiconductor device according to claim 3, further comprising:
a first dielectric layer disposed on the gate dielectric layer; and
a second dielectric layer disposed on the gate electrode.
6. The semiconductor device according to claim 5, wherein the first dielectric layer is provided at the same height as the gate.
7. The semiconductor device of claim 5, wherein the first dielectric layer is disposed between the first sub-field plate and the gate, and wherein a second dielectric layer is disposed between the second sub-field plate and the gate.
8. The semiconductor device of claim 7, wherein a groove is disposed between the first sub-field plate and the gate, and the groove is between the first sub-field plate and a portion of the first dielectric layer.
9. The semiconductor device of claim 7, wherein the second sub-field plate and the second dielectric layer have a predetermined distance therebetween.
10. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a channel layer on the substrate;
forming a barrier layer on the channel layer;
forming a gate dielectric layer on the barrier layer;
and forming a source electrode, a drain electrode and a grid electrode on the grid dielectric layer. And the source electrode and the drain electrode are in contact with the channel layer, and the gate electrode is located between the source electrode and the drain electrode.
And forming a field plate on the gate dielectric layer, wherein one end of the field plate is connected with the gate dielectric layer and is positioned between the source electrode and the drain electrode, and the other end of the field plate extends out of the gate dielectric layer and extends towards the upper part of the gate electrode.
11. An electronic device characterized by comprising the semiconductor device according to claim 1.
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