CN104009077A - Heterojunction structure, preparing method thereof, heterojunction field-effect tube and preparing method thereof - Google Patents
Heterojunction structure, preparing method thereof, heterojunction field-effect tube and preparing method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000005669 field effect Effects 0.000 title claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 103
- 230000004888 barrier function Effects 0.000 claims abstract description 68
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims description 76
- 238000000576 coating method Methods 0.000 claims description 76
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 60
- 229910002601 GaN Inorganic materials 0.000 claims description 53
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 41
- 238000002360 preparation method Methods 0.000 claims description 33
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 31
- 229910052733 gallium Inorganic materials 0.000 claims description 31
- 229910052757 nitrogen Inorganic materials 0.000 claims description 30
- 125000005842 heteroatom Chemical group 0.000 claims description 24
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 claims description 20
- 238000002161 passivation Methods 0.000 claims description 18
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 13
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 12
- 229910052738 indium Inorganic materials 0.000 claims description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 10
- 229910017083 AlN Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 230000003139 buffering effect Effects 0.000 abstract 4
- 230000007547 defect Effects 0.000 description 17
- 239000000758 substrate Substances 0.000 description 16
- 238000004549 pulsed laser deposition Methods 0.000 description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 238000000927 vapour-phase epitaxy Methods 0.000 description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 238000001451 molecular beam epitaxy Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000003877 atomic layer epitaxy Methods 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052742 iron Inorganic materials 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
The invention discloses a heterojunction structure, a preparing method thereof, a heterojunction field-effect tube and a preparing method thereof. The heterojunction structure comprises a buffering layer, a channel layer, an inserting layer and a barrier layer. The buffering layer is made of semi-insulating semiconductor materials. The channel layer is placed on the buffering layer. The channel layer is made of involuntary-doped semiconductor materials. The channel layer comprises a first channel layer and a second channel layer. The first channel layer is placed on the buffering layer. The inserting layer is placed between the first channel layer and the second channel layer. The forbidden band width of the inserting layer is larger than that of the channel layer. The barrier layer is placed on the second channel layer. Two-dimensional electron gas exists between interfaces of the barrier layer and the second channel layer. The problems of current collapse and electric leakage of the heterojunction structure and the heterojunction field-effect tube are solved.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of heterojunction structure and preparation method thereof, hetero junction field effect pipe and preparation method thereof.
Background technology
Gallium nitride (GaN) heterojunction device is the wide band gap semiconductor device with high concentration two-dimensional electron gas, has high output power density, the feature that high temperature resistant, stability is strong and puncture voltage is high.Therefore, based on AlGaN/GaN High Electron Mobility Transistor (High Electron Mobility Transistor, abbreviation HEMT) device can be widely used in the high frequency high-power component fields such as radar, communication and Aero-Space, and also have very big application potential in power electronic device field.
In Fig. 1 a-Fig. 1 c, GaN heterojunction structure of the prior art has been shown, as shown in Figure 1a, Fig. 1 a is the heterojunction structure figure that aluminum gallium nitride in prior art (AlGaN) and semi-insulating GaN (S.I GaN) form, wherein, the growing method of S.I.GaN for to mix some metallic element (as iron) as deep energy level acceptor when growing gallium nitride material, compensate gallium (Ga) room and residual oxygen in non-Doped GaN, utilize compensating action to make GaN show as semi-insulating characteristic.Because mixing of iron makes GaN surface, become very coarse, introduce a large amount of defects and surface state.This can cause using the device generation current pull-in effect of heterojunction structure as shown in Figure 1a.
Fig. 1 b is the heterojunction structure figure that in prior art, low-doped gallium nitride (u-GaN) and AlGaN form, by the AlGaN that grows on u-GaN, form, in this structure, because the Ga room in u-GaN and residual oxygen and Si etc. cause this GaN material, be N-type, use the device of this kind of structure, not only leakage current is large, and the turn-off characteristic of grid has also been subject to impact.
Fig. 1 c is the heterojunction structure figure that AlGaN in prior art, u-GaN and S.I GaN form, and this heterojunction structure is the combination of the heterojunction structure in Fig. 1 a and Fig. 1 b, in this heterojunction structure, has solved to a certain extent the problem of current collapse and electric leakage.But in this structure, the thickness of u-GaN is become to very responsive, when u-GaN is too thick, the leakage current of this heterojunction structure is large, and when u-GaN is too thin, the current collapse of this heterojunction structure is serious.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of heterojunction structure and preparation method thereof, hetero junction field effect pipe and preparation method thereof, suppress the current collapse effect that heterojunction structure and hetero junction field effect pipe exist, reduced the leakage current of heterojunction structure and hetero junction field effect pipe simultaneously.
First aspect, the embodiment of the present invention provides a kind of heterojunction structure, and described heterojunction structure comprises:
Resilient coating, the material of described resilient coating is semi-insulated semi-conducting material;
Be positioned at the channel layer on described resilient coating, the semi-conducting material that the material of described channel layer is involuntary doping, described channel layer comprises the first channel layer and the second channel layer, wherein, described the first channel layer is positioned on described resilient coating;
Insert layer between described the first channel layer and described the second channel layer, wherein, the energy gap of described insert layer is greater than the energy gap of described channel layer;
Be positioned at the barrier layer on described the second channel layer, between described barrier layer and the interface of described the second channel layer, have two-dimensional electron gas.
Further, the material of described resilient coating is any one material in gallium nitride, indium gallium nitrogen or aluminium indium gallium nitrogen or the combination of multiple material.
Further, the material of described channel layer is any one material in gallium nitride, indium gallium nitrogen or aluminium indium gallium nitrogen or the combination of multiple material.
Further, the material of described insert layer is any one material in aluminium nitride, aluminum gallium nitride or aluminium indium gallium nitrogen or the combination of multiple material.
Further, the material of described barrier layer is any one material in aluminium nitride, aluminum gallium nitride or aluminium indium gallium nitrogen or the combination of multiple material.
Second aspect, the embodiment of the present invention provides a kind of hetero junction field effect pipe, and described hetero junction field effect pipe comprises:
Resilient coating, the material of described resilient coating is semi-insulated semi-conducting material;
Be positioned at the channel layer on resilient coating, the semi-conducting material that the material of described channel layer is involuntary doping, described channel layer comprises the first channel layer and the second channel layer, wherein, described the first channel layer is positioned on resilient coating;
Insert layer between the first channel layer and the second channel layer, wherein, the energy gap of described insert layer is greater than the energy gap of described channel layer;
Be positioned at the barrier layer on the second channel layer, between described barrier layer and the interface of described the second channel layer, have two-dimensional electron gas;
Be positioned at the passivation layer on barrier layer;
The gate electrode contacting with described barrier layer;
And, be positioned at source electrode and the drain electrode of described gate electrode both sides.
Further, described hetero junction field effect pipe also comprises:
Nucleating layer, described resilient coating is positioned on described nucleating layer.
Further, described hetero junction field effect pipe also comprises:
Gate medium, described gate medium is between described gate electrode and described barrier layer.
The third aspect, the embodiment of the present invention provides a kind of preparation method of heterojunction structure, and for the preparation of the heterojunction structure as described in first aspect, described method comprises:
On resilient coating, form successively the first channel layer, insert layer, the second channel layer and barrier layer;
Wherein,
The material of described resilient coating is semi-insulated semi-conducting material;
The semi-conducting material that the material of described the first channel layer and the second channel layer is involuntary doping;
The energy gap of described insert layer is greater than the energy gap of described channel layer;
Between the interface of described barrier layer and described the second channel layer, there is two-dimensional electron gas.
Fourth aspect, the embodiment of the present invention provides a kind of preparation method of hetero junction field effect pipe, and for the preparation of the hetero junction field effect pipe as described in second aspect, described method comprises:
On resilient coating, form successively the first channel layer, insert layer, the second channel layer and barrier layer;
On described barrier layer, form passivation layer;
From described passivation layer, etch into described barrier layer and form area of grid, on described area of grid, form gate electrode;
In the both sides of described area of grid, from described passivation layer etching, enter described barrier layer and form source region and drain region, on described source region, form source electrode, on described drain region, form drain electrode.
Further, form the first channel layer on resilient coating before, described method also comprises:
On nucleating layer, form resilient coating.
Further, form gate electrode on described area of grid before, described method also comprises:
On described area of grid, form gate dielectric layer.
Heterojunction structure that the embodiment of the present invention provides and preparation method thereof, hetero junction field effect pipe and preparation method thereof, the semi-conducting material of the involuntary doping of material selection of one side channel layer, because this material has advantages of that defect is few, therefore can reduce the current collapse being caused by defect; By increase broad stopband insert layer in semiconductor channel layer, being with of heterojunction adjusted on the other hand, suppressed the current collapse that the defect by semi insulating semiconductor resilient coating causes.In addition, in shutoff situation, broad stopband insert layer can also reduce leaky, therefore, has overcome the current collapse effect of heterojunction structure and hetero junction field effect pipe, can reduce the leakage current of heterojunction structure and hetero junction field effect pipe simultaneously.
Accompanying drawing explanation
To the person of ordinary skill in the art is more clear that above-mentioned and other feature and advantage of the present invention by describe exemplary embodiment of the present invention in detail with reference to accompanying drawing below, in accompanying drawing:
Fig. 1 a is the heterojunction structure figure that aluminum gallium nitride in prior art (AlGaN) and semi-insulating GaN (S.I GaN) form;
Fig. 1 b is the heterojunction structure figure that in prior art, low-doped gallium nitride (u-GaN) and AlGaN form;
Fig. 1 c is the heterojunction structure figure that AlGaN in prior art, u-GaN and S.I GaN form;
Fig. 2 is a kind of heterojunction structure figure that the embodiment of the present invention one provides;
Fig. 3 is energy band diagram in the y-direction in a kind of heterojunction structure of providing of the embodiment of the present invention one;
Fig. 4 is the preparation method's of a kind of heterojunction structure of providing of the embodiment of the present invention two flow chart;
Fig. 5 is the structure chart of a kind of T-shaped gate transistor with high electron mobility of providing of the embodiment of the present invention three;
Fig. 6 is the preparation method's of a kind of T-shaped gate transistor with high electron mobility of providing of the embodiment of the present invention four flow chart;
Fig. 7 is the structure chart of a kind of MIS gate transistor with high electron mobility of providing of the embodiment of the present invention five;
Fig. 8 is the preparation method's of a kind of MIS gate transistor with high electron mobility of providing of the embodiment of the present invention six flow chart.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, in accompanying drawing, only show part related to the present invention but not full content.
Embodiment mono-
Fig. 2 is a kind of heterojunction structure figure that the embodiment of the present invention one provides, referring to Fig. 2, channel layer 12, described channel layer 12 that this heterojunction structure comprises resilient coating 11, be positioned on resilient coating 11 comprise the first channel layer 121 and the second channel layer 122, described the first channel layer 121 is positioned on resilient coating 11, insert layer 13 between the first channel layer 121 and the second channel layer 122, and be positioned at the barrier layer 14 on the second channel layer 121, between described barrier layer 14 and the interface of described the second channel layer 122, there is two-dimensional electron gas.
Wherein, the material of described resilient coating 11 is semi-insulated semi-conducting material, and the material of described resilient coating 11 can be any one material in gallium nitride (GaN), indium gallium nitrogen (InGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material.
The material of described channel layer 12 is the semi-conducting material of involuntary doping, the semi-conducting material of described involuntary doping refers to and in semi-conducting material, stains impurity, not that people is the impurity mixing, this material has advantages of that defect is few, can reduce the current collapse being caused by defect, particularly, the material of described channel layer 12 can be any one material in gallium nitride (GaN), indium gallium nitrogen (InGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material.
The material of described insert layer 13 can be any one material in aluminium nitride (AlN), aluminum gallium nitride (AlGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material, in the present embodiment, adopt being with of 13 pairs of heterojunction of insert layer of broad stopband to adjust, because the energy gap of described insert layer 13 is greater than the energy gap of described channel layer 12, the insert layer 13 of broad stopband has been introduced electronic barrier, make the electronics in channel layer 12 be difficult to cross this potential barrier arrival resilient coating 11, and then the defect being cushioned in layer 11 is captured.Therefore, even the thinner thickness of the second channel layer 122, current collapse also can be inhibited, the thickness of the heterojunction structure that the embodiment of the present invention provides and the first channel layer 121 and the second channel layer 122 is irrelevant, has solved the problem that heterojunction structure in prior art is easily subject to channel layer thickness limits.
In addition,, in shutoff situation, the electronics that the electronic barrier of introducing due to insert layer 13 has limited in channel layer 12 and resilient coating 11 moves along the longitudinal direction, thereby has reduced leakage current.
The material of described barrier layer 14 is any one material in aluminium nitride, aluminum gallium nitride or aluminium indium gallium nitrogen or the combination of multiple material, between described barrier layer 14 and the interface of described the second channel layer 122, there is two-dimensional electron gas, be that electronics is along the quantization that becomes of moving of the surface direction perpendicular to this heterojunction structure, the energy that is it can only be got a series of discrete value, and be parallel to surperficial motion, be still freely, energy can be arbitrary value, in the present embodiment, using being parallel to surperficial direction as x direction, using the direction perpendicular to surperficial as y direction.
Fig. 3 is energy band diagram in the y-direction in a kind of heterojunction structure of providing of the embodiment of the present invention one, referring to Fig. 3, in figure, Ec represents in heterojunction structure conduction level in the y-direction, and Ev represents in heterojunction structure valence-band level in the y-direction, and Ef represents in heterojunction structure Fermi level in the y-direction.As can be seen from Figure 3, because the energy gap of insert layer 13 is greater than the energy gap of channel layer 12, make the electronics in channel layer 12 be difficult to cross the electronic barrier arrival resilient coating 11 that insert layer 13 is introduced, thereby the defect being cushioned in layer 11 is captured, thereby can suppress current collapse effect, in addition, because the material of resilient coating 11 is semi-insulated semi-conducting material, make the conduction level Ec of barrier layer 14 and resilient coating 11 away from Fermi level, thereby this heterojunction structure is easily turn-offed, and leakage current is little.
The heterojunction structure that the embodiment of the present invention provides is with respect to the heterojunction structure of aluminum gallium nitride in prior art (AlGaN) and semi-insulating GaN (S.I GaN) formation, because the resilient coating 11 of semi insulating semiconductor is away from channel region, and the motion of channel electrons is subject to the restriction of the electronic barrier of broad stopband insert layer 13 introducings, has suppressed the current collapse being caused by semi-insulating GaN layer defects.
The heterojunction structure that the embodiment of the present invention one provides is with respect to the heterojunction structure of low-doped gallium nitride (u-GaN) in prior art and AlGaN formation, because the material of resilient coating 11 is comprised of semi-insulated semi-conducting material, and the energy gap of insert layer 13 is greater than the energy gap of channel layer 12, make the conduction band of non-channel region away from Fermi level, thereby the heterojunction structure being provided by the embodiment of the present invention easily turn-offs, and leakage current reduces.
The heterojunction structure that the embodiment of the present invention one provides is with respect to AlGaN in prior art, the heterojunction structure that u-GaN and S.IGaN form, because broad stopband insert layer 13 has been introduced electronic barrier, make the electronics in channel layer 12 be difficult to cross this potential barrier arrival resilient coating 11, and then the defect being cushioned in layer 11 is captured, therefore, it doesn't matter with the thickness of channel layer 12, solved the thickness problem of involuntary Doped GaN, in addition, when the material of described insert layer 13 is AlN, can also increase the compressive strain of the second channel layer 122 of the second channel layer 122 involuntary doping that are arranged in described insert layer 13 tops, thereby the density of two-dimensional electron gas and mobility in raising heterojunction structure.
The heterojunction structure that the embodiment of the present invention one provides, by having inserted the insert layer of broad stopband in the middle of the semiconductor channel layer in involuntary doping, suppressed the current collapse that the defect by semi insulating semiconductor resilient coating causes, in addition, in shutoff situation, broad stopband insert layer can also reduce leaky.
Embodiment bis-
Fig. 4 is the preparation method's of a kind of heterojunction structure of providing of the embodiment of the present invention two flow chart, the heterojunction structure providing for the preparation of above-described embodiment, and referring to Fig. 4, described method comprises:
Step 21, on substrate, form resilient coating.
The material of described substrate can be the material of any one applicable grown buffer layer, and this backing material includes, but are not limited to sapphire (Sapphire), carborundum (SiC), gallium nitride (GaN) or silicon (Si) etc.The material of described resilient coating is semi-insulated semi-conducting material, can be any one material in gallium nitride (GaN), indium gallium nitrogen (InGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material particularly.The method that forms resilient coating on substrate can be chemical vapour deposition technique (Chemical Vapor Deposition, be called for short CVD), vapour phase epitaxy method (Vapour Phase Epitaxy, be called for short VPE), metallo-organic compound chemical gaseous phase deposition method (Metal-organic Chemical Vapor Deposition, be called for short MCVD), low-pressure chemical vapour deposition technique (Low Pressure Chemical Vapor Deposition, be called for short LPCVD), plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, be called for short PECVD), pulsed laser deposition (Pulsed Laser Deposition, be called for short PLD), atomic layer epitaxy method, molecular beam epitaxy (Molecular Beam Epitaxy, be called for short MBE), the method such as sputtering method or evaporation.When the material of described resilient coating is GaN, when preparing semi-insulating GaN, can, by mixing some metallic element (as iron) as deep energy level acceptor, compensate Ga room and residual oxygen in non-Doped GaN, trimethyl gallium (TMGa) and ammonia (NH
3) respectively as Ga source and N source, impurity source Cp
2fe passes through H
2carry and enter growth room, utilize compensating action to make gallium nitride show as semi-insulating characteristic.
Step 22, on resilient coating, form the first channel layer.
The material of described the first channel layer is the semi-conducting material of involuntary doping, particularly, the material of described channel layer 12 can be any one material in gallium nitride (GaN), indium gallium nitrogen (InGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material, this material has advantages of that defect is few, can reduce the current collapse being caused by defect.
Can on resilient coating, form the first channel layer by methods such as CVD, VPE, MOCVD, LPCVD, PECVD, pulsed laser deposition (PLD), atomic layer epitaxy, MBE, sputter, evaporations.
Step 23, on the first channel layer, form insert layer.
The method that forms insert layer on the first channel layer can be CVD, VPE, MOCVD, LPCVD or PECVD.
The material of described insert layer can be any one material in aluminium nitride (AlN), aluminum gallium nitride (AlGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material, wherein, the energy gap of described insert layer is greater than the energy gap of the first channel layer and the second channel layer, thereby introduce electronic barrier between channel layer and substrate, electronics in the first channel layer and the second channel layer is cushioned the defect compound tense in layer, need to cross this electronic barrier, thereby suppress current collapse.
In the present embodiment, the preferred AlN material of material of described insert layer, the electronic barrier that this material is introduced has limited the motion in the y-direction of electronics in substrate, resilient coating and the first channel layer, in addition, when the material of resilient coating is GaN, the introducing of broad stopband insert layer, can also reduce the stress in GaN, and the dislocation reducing in GaN obtains high-quality GaN film.
It should be noted that, the heterojunction structure that the thickness of the first channel layer and the second channel layer is prepared the present embodiment is suppressing there is no impact aspect current collapse and electric leakage.
Step 24, in insert layer, form the second channel layer.
The material of described the second channel layer is identical with the material of described the first channel layer, forms the second channel layer method and can comprise CVD, VPE, MOCVD, LPCVD, PECVD, pulsed laser deposition (PLD), atomic layer epitaxy, MBE, sputter, evaporation etc. in insert layer.
Step 25, on the second channel layer, form barrier layer.
The material of described barrier layer can be any one material in aluminium nitride (AlN), aluminum gallium nitride (AlGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material, preferably AlGaN forms heterojunction, and described barrier layer and described the second channel layer form two-dimensional electron gas conducting channel at contact interface.
On the second channel layer, form barrier layer method and comprise CVD, VPE, MOCVD, LPCVD, PECVD, pulsed laser deposition (PLD), atomic layer epitaxy, MBE, sputter, evaporation etc.
The preparation method of a kind of heterojunction structure that the embodiment of the present invention two provides, by form successively resilient coating, the first channel layer, insert layer, the second channel layer and barrier layer on substrate, wherein, described resilient coating is semi-insulated semiconductor layer, the semiconductor layer that described the first channel layer and the second channel layer are involuntary doping, the energy gap of described insert layer is greater than the energy gap of the first channel layer and the second channel layer, thereby the current collapse effect that has suppressed heterojunction structure has reduced heterojunction structure leakage current simultaneously.
Embodiment tri-
Fig. 5 is the structure chart of a kind of T-shaped gate transistor with high electron mobility of providing of the embodiment of the present invention three, this embodiment be take above-described embodiment one as basis, referring to Fig. 5, described T-shaped gate transistor with high electron mobility comprises: substrate 31, resilient coating 32, be positioned at the channel layer 33 on resilient coating 32, described channel layer 33 comprises the first channel layer 331 and the second channel layer 332, wherein, described the first channel layer 331 is positioned on resilient coating 32, insert layer 34 between the first channel layer 331 and the second channel layer 332, be positioned at the barrier layer 35 on the second channel layer 332, be positioned at the passivation layer 36 on barrier layer 35, the gate electrode 37 contacting with described barrier layer 35, be positioned at source electrode 38 and the drain electrode 39 of described gate electrode 37 both sides.
Wherein, the material of described resilient coating 32 is semi-insulated semi-conducting material, particularly, the material of described resilient coating 32 can be any one material in gallium nitride (GaN), indium gallium nitrogen (InGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material.
The material of described channel layer 33 is the semi-conducting material of involuntary doping, and the material of described channel layer 33 can be any one material in gallium nitride (GaN), indium gallium nitrogen (InGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material particularly.
The energy gap of described insert layer 34 is greater than the energy gap of described channel layer 33, and the material of described insert layer 34 can be any one material in aluminium nitride (AlN), aluminum gallium nitride (AlGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material.
Between described barrier layer 35 and the interface of described the second channel layer 332, have two-dimensional electron gas, the material of described barrier layer 35 can be any one material in aluminium nitride (AlN), aluminum gallium nitride (AlGaN) or aluminium indium gallium nitrogen (AlInGaN) or the combination of multiple material.
It is can heterogeneous current collapse identical with the principle of electric leakage that the T-shaped gate transistor with high electron mobility that the present embodiment provides can suppress heterojunction structure that the principle of current collapse and electric leakage provides with the embodiment of the present invention one, do not repeat them here.
Preferably, described T-shaped gate transistor with high electron mobility can also comprise nucleating layer 310, described nucleating layer 310 is between substrate and described resilient coating 32, described nucleating layer 310 for forming resilient coating 32 on described nucleating layer 310, the benefit that increases nucleating layer 310 is, the material of resilient coating 32 can be better grown in above substrate 31.
The T-shaped gate transistor with high electron mobility that the embodiment of the present invention three provides, by having inserted the insert layer of broad stopband in the middle of the semiconductor channel layer in involuntary doping, suppressed the current collapse that the defect by semi insulating semiconductor resilient coating causes, in addition, in shutoff situation, broad stopband insert layer can also reduce leaky.
Embodiment tetra-
Fig. 6 is the preparation method's of a kind of T-shaped gate transistor with high electron mobility of providing of the embodiment of the present invention four flow chart, the T-shaped gate transistor with high electron mobility that the preparation method of this T-shaped gate transistor with high electron mobility provides for the preparation of above-described embodiment three, referring to Fig. 6, described method comprises:
Step 41, on substrate, form resilient coating.
Step 42, on resilient coating, form the first channel layer.
Step 43, on the first channel layer, form insert layer.
Step 44, in insert layer, form the second channel layer.
Step 45, on the second channel layer, form barrier layer.
Step 46, on barrier layer, form passivation layer.
Step 47, from described passivation layer, etch into described barrier layer and form area of grid, on described area of grid, form gate electrode.
Step 48, in the both sides of described area of grid, from described passivation layer etching, enter described barrier layer and form source region and drain region, on described source region, form source electrode, on described drain region, form drain electrode.
T-shaped gate transistor with high electron mobility prepared by the preparation method of the T-shaped gate transistor with high electron mobility that utilization the present embodiment provides, can suppress current collapse and leaky.
Preferably, before step 41, in described method, also comprise:
Step 41a is formed into stratum nucleare on substrate.
The benefit that increases step 41a is, is formed into after stratum nucleare, is conducive to form resilient coating on described nucleating layer.
T-shaped gate transistor with high electron mobility prepared by the preparation method of the T-shaped gate transistor with high electron mobility that the embodiment of the present invention four provides, by having inserted the insert layer of broad stopband in the middle of the semiconductor channel layer in involuntary doping, suppressed the current collapse that the defect by semi insulating semiconductor resilient coating causes, in addition, in shutoff situation, broad stopband insert layer can also reduce leaky.
Embodiment five
Fig. 7 is the structure chart of a kind of MIS gate transistor with high electron mobility of providing of the embodiment of the present invention five, it is basis that this embodiment be take above-described embodiment one and embodiment tri-, referring to Fig. 7, described MIS gate transistor with high electron mobility comprises substrate 51, be positioned at the nucleating layer 52 on substrate 51, be positioned at the resilient coating 53 on nucleating layer 52, be positioned at the channel layer 54 on resilient coating 53, described channel layer 54 comprises the first channel layer 541 and the second channel layer 542, wherein, described the first channel layer 541 is positioned on resilient coating 53, insert layer 55 between the first channel layer 541 and the second channel layer 542, be positioned at the barrier layer 56 on the second channel layer 542, be positioned at the passivation layer 57 on barrier layer 56, the gate electrode 58 contacting with described barrier layer 56, gate medium 59 between described gate electrode 58 and described barrier layer 56, be positioned at source electrode 510 and the drain electrode 511 of described gate electrode 58 both sides.
In the present embodiment, the material of described gate medium 59 includes, but are not limited to SiO
2and Si
3n
4and SiO
2and Si
3n
4the material combining.
In the present embodiment, described substrate 51, nucleating layer 52, resilient coating 53, channel layer 54, insert layer 55, barrier layer 56, passivation layer 57, gate electrode 58, the material of source electrode 510 and drain electrode 511 respectively with third embodiment of the invention in T-shaped gate transistor with high electron mobility substrate 31, nucleating layer 310, resilient coating 32, channel layer 33, insert layer 34, barrier layer 35, passivation layer 36, gate electrode 37, source electrode 38 is identical with the material of drain electrode 39, and the principle that this MIS gate transistor with high electron mobility can suppress current collapse and leakage current is identical with the principle that the heterojunction structure providing in first embodiment of the invention suppresses current collapse and leakage current, do not repeat them here.
Embodiment six
Fig. 8 is the preparation method's of a kind of MIS gate transistor with high electron mobility of providing of the embodiment of the present invention six flow chart, the MIS gate transistor with high electron mobility that the preparation method of this MIS gate transistor with high electron mobility provides for the preparation of above-described embodiment five, referring to Fig. 8, described method comprises:
Step 61, on substrate, be formed into stratum nucleare.
Step 62, on nucleating layer, form resilient coating.
Step 63, on resilient coating, form the first channel layer.
Step 64, on the first channel layer, form insert layer.
Step 65, in insert layer, form the second channel layer.
Step 66, on the second channel layer, form barrier layer.
Step 67, on barrier layer, form passivation layer.
Step 68, from described passivation layer, etch into described barrier layer and form area of grid, on described area of grid, form gate dielectric layer.
Step 69, on described gate dielectric layer, form gate electrode.
Step 610, in the both sides of described area of grid, from described passivation layer etching, enter described barrier layer and form source region and drain region, on described source region, form source electrode, on described drain region, form drain electrode.
MIS gate transistor with high electron mobility prepared by the preparation method of the MIS gate transistor with high electron mobility that the embodiment of the present invention six provides, by having inserted the insert layer of broad stopband in the middle of the semiconductor channel layer in involuntary doping, suppressed the current collapse that the defect by semi insulating semiconductor resilient coating causes, in addition, in shutoff situation, broad stopband insert layer can also reduce leaky.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various changes and variation.All any modifications of doing, be equal to replacement, improvement etc., within protection scope of the present invention all should be included within spirit of the present invention and principle.
Claims (12)
1. a heterojunction structure, is characterized in that, described heterojunction structure comprises:
Resilient coating, the material of described resilient coating is semi-insulated semi-conducting material;
Be positioned at the channel layer on described resilient coating, the semi-conducting material that the material of described channel layer is involuntary doping, described channel layer comprises the first channel layer and the second channel layer, wherein, described the first channel layer is positioned on described resilient coating;
Insert layer between described the first channel layer and described the second channel layer, wherein, the energy gap of described insert layer is greater than the energy gap of described channel layer;
Be positioned at the barrier layer on described the second channel layer, between described barrier layer and the interface of described the second channel layer, have two-dimensional electron gas.
2. heterojunction structure according to claim 1, is characterized in that, the material of described resilient coating is any one material in gallium nitride, indium gallium nitrogen or aluminium indium gallium nitrogen or the combination of multiple material.
3. heterojunction structure according to claim 1, is characterized in that, the material of described channel layer is any one material in gallium nitride, indium gallium nitrogen or aluminium indium gallium nitrogen or the combination of multiple material.
4. heterojunction structure according to claim 1, is characterized in that, the material of described insert layer is any one material in aluminium nitride, aluminum gallium nitride or aluminium indium gallium nitrogen or the combination of multiple material.
5. heterojunction structure according to claim 1, is characterized in that, the material of described barrier layer is any one material in aluminium nitride, aluminum gallium nitride or aluminium indium gallium nitrogen or the combination of multiple material.
6. a hetero junction field effect pipe, is characterized in that, described hetero junction field effect pipe comprises:
Resilient coating, the material of described resilient coating is semi-insulated semi-conducting material;
Be positioned at the channel layer on resilient coating, the semi-conducting material that the material of described channel layer is involuntary doping, described channel layer comprises the first channel layer and the second channel layer, wherein, described the first channel layer is positioned on resilient coating;
Insert layer between the first channel layer and the second channel layer, wherein, the energy gap of described insert layer is greater than the energy gap of described channel layer;
Be positioned at the barrier layer on the second channel layer, between described barrier layer and the interface of described the second channel layer, have two-dimensional electron gas;
Be positioned at the passivation layer on barrier layer;
The gate electrode contacting with described barrier layer;
And, be positioned at source electrode and the drain electrode of described gate electrode both sides.
7. hetero junction field effect pipe according to claim 6, is characterized in that, described hetero junction field effect pipe also comprises:
Nucleating layer, described resilient coating is positioned on described nucleating layer.
8. according to the hetero junction field effect pipe described in claim 6 or 7, it is characterized in that, described hetero junction field effect pipe also comprises:
Gate medium, described gate medium is between described gate electrode and described barrier layer.
9. a preparation method for heterojunction structure, for the preparation of heterojunction structure as claimed in claim 1, is characterized in that, described method comprises:
On resilient coating, form successively the first channel layer, insert layer, the second channel layer and barrier layer;
Wherein,
The material of described resilient coating is semi-insulated semi-conducting material;
The semi-conducting material that the material of described the first channel layer and the second channel layer is involuntary doping;
The energy gap of described insert layer is greater than the energy gap of described channel layer;
Between the interface of described barrier layer and described the second channel layer, there is two-dimensional electron gas.
10. a preparation method for hetero junction field effect pipe, for the preparation of hetero junction field effect pipe claimed in claim 6, is characterized in that, described method comprises:
On resilient coating, form successively the first channel layer, insert layer, the second channel layer and barrier layer;
On described barrier layer, form passivation layer;
From described passivation layer, etch into described barrier layer and form area of grid, on described area of grid, form gate electrode;
In the both sides of described area of grid, from described passivation layer etching, enter described barrier layer and form source region and drain region, on described source region, form source electrode, on described drain region, form drain electrode.
The preparation method of 11. hetero junction field effect pipes according to claim 10, is characterized in that, form the first channel layer on resilient coating before, described method also comprises:
On nucleating layer, form resilient coating.
12. according to the preparation method of the hetero junction field effect pipe described in claim 10 or 11, it is characterized in that, form gate electrode on described area of grid before, described method also comprises:
On described area of grid, form gate medium.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783955A (en) * | 2016-12-26 | 2017-05-31 | 英诺赛科（珠海）科技有限公司 | The semiconductor devices and its manufacture method of the insert layer containing nitrogen gallium aluminium and nitrogen gallium indium |
| CN107735863A (en) * | 2015-07-01 | 2018-02-23 | 香港科技大学 | Enhanced double channel HEMT |
| CN111162117A (en) * | 2020-01-02 | 2020-05-15 | 杭州电子科技大学 | GaN device capable of resisting single-particle burning |
| CN113990950A (en) * | 2020-12-01 | 2022-01-28 | 深圳市晶相技术有限公司 | Semiconductor device and application and manufacturing method thereof |
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2014
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107735863A (en) * | 2015-07-01 | 2018-02-23 | 香港科技大学 | Enhanced double channel HEMT |
| CN106783955A (en) * | 2016-12-26 | 2017-05-31 | 英诺赛科（珠海）科技有限公司 | The semiconductor devices and its manufacture method of the insert layer containing nitrogen gallium aluminium and nitrogen gallium indium |
| CN111162117A (en) * | 2020-01-02 | 2020-05-15 | 杭州电子科技大学 | GaN device capable of resisting single-particle burning |
| CN113990950A (en) * | 2020-12-01 | 2022-01-28 | 深圳市晶相技术有限公司 | Semiconductor device and application and manufacturing method thereof |
| WO2022116915A1 (en) * | 2020-12-01 | 2022-06-09 | 深圳市晶相技术有限公司 | Semiconductor device, and application and manufacturing methods therefor |
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