JP2013187285A - Epitaxial wafer manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer manufacturing method which can improve yield of an electronic device which is manufactured by using an epitaxial wafer in which a nitride semiconductor is formed on an Si substrate.SOLUTION: An epitaxial wafer manufacturing method comprises a first process (S1) of cleaning an Si substrate by wet etching; a second process (S2) of cleaning the Si substrate by dry etching after the first process (S1); and a third process (S3) of epitaxial growing a nitride semiconductor on the Si substrate after the second process (S2).

Description

  The present invention relates to an epitaxial wafer manufacturing method, and more particularly to an epitaxial wafer manufacturing method in which a nitride semiconductor is formed on an Si substrate.

  Conventionally, as an epitaxial wafer manufacturing method, after forming an oxide film on the surface of the Si substrate, the oxide film is removed by solution etching with hydrofluoric acid, and the surface of the Si substrate is cleaned by heat treatment in hydrogen gas. (For example, refer to JP-A-2005-142445 (Patent Document 1)).

  FIG. 3 shows a cross-sectional TEM image of a main part including pits of an epitaxial wafer in which a nitride semiconductor is formed on a Si substrate. In FIG. 3, 101 is a Si substrate, 102 is an AlN layer, and 103 is a superlattice. 104 is a GaN layer, 105 is an AlN characteristic improving layer, and 106 is an AlGaN layer.

By analyzing the pit generation portion of this epitaxial wafer in more detail, it became clear that SiO ₂ exists at the origin of the defect.

  At the lower part of the pits of such an epitaxial wafer, the superlattice structure of the superlattice layer 103 is broken and the film thickness of the GaN layer 104 is thin, so that there is no longitudinal breakdown voltage that the epitaxial wafer should have. Therefore, it was a weak point to break at a low voltage. However, the presence of this defect can be confirmed by a surface inspection device, and the yield can be grasped in advance.

FIG. 4 shows the relationship between the size of the SiO _{2 serving} as the starting point of the pit and the size of the pit opening in the epitaxial wafer having the same configuration as FIG. As shown in FIG. 4, when the size of SiO ₂ is about 100 nm or less, an opening is not formed as a pit on the surface of the GaN layer 104, but the superlattice structure of the superlattice layer 103 below that is formed. This indicates the possibility that there is a defect that is broken. This type of defect cannot be detected by a surface inspector, and it is impossible to know in advance which device will break among multiple devices manufactured using such an epitaxial wafer. is there.

  In fact, as shown in FIG. 5, although the superlattice structure of the superlattice layer 203 is broken, a defect flattened in the GaN layer thereon has been found. FIG. 5 shows a cross-sectional TEM image of the main part of the epitaxial wafer. In FIG. 5, 201 is an Si substrate, 202 is an AlN layer, 203 is a superlattice layer, 204 is a GaN layer, and 205 is an AlN characteristic improvement. Layer 206 is an AlGaN layer.

As shown in FIG. 5, a first pit is formed in the AlN layer 202 grown on the upper side, starting from a residue of SiO ₂ on the Si substrate 201 (not visible in FIG. 5). Further, the superlattice layer 203 grown on the AlN layer 202 has a laminated structure collapsed by the presence of the first pits of the AlN layer 202, and second pits 203a larger than the first pits are formed. Yes.

Further, when small SiO ₂ exists, a defect in which the superlattice structure of the superlattice layer 303 is broken only in the vicinity of the Si substrate 101 is formed as shown in FIG. This defect cannot be detected by a defect inspector. In FIG. 6, 301 is an Si substrate, 302 is an AlN layer, and 303 is a superlattice layer.

  FIG. 7 is a diagram showing a CUM (cumulative) plot of the longitudinal breakdown voltage of a portion of the epitaxial wafer where there is no pit. The method for preparing the sample at this time is as follows.

  First, an electrode made of tungsten having a diameter of 1.4 mm is formed on an epitaxial wafer using a metal mask. Thereafter, the periphery of the electrode is diced into 2 mm square to separate the elements around the electrode. Next, FIG. 7 is a graph in which samples with no pits in a 2 mm square are extracted, a high voltage is applied to the samples without pits, and the number of volts destroyed is plotted.

  The defect shown in FIG. 6 causes breakage in a portion (about 400 to 600 V) having a low vertical breakdown voltage surrounded by a dotted line in FIG. On the other hand, the defect shown in FIG. 6 corresponds to the portion surrounded by the alternate long and short dash line in FIG. 7 that has a tail on the lower voltage side than the longitudinal breakdown voltage that the epitaxial wafer should have. Both of the defects in FIGS. 5 and 6 are considered to greatly affect the yield of electronic devices manufactured using an epitaxial wafer.

However, the cleaning of the epitaxial wafer with the hydrogen gas disclosed in Patent Document 1 has no effect of removing the remaining SiO ₂ , and merely terminates the Si surface with hydrogen, and defects caused by SiO _2. It is impossible to reduce.

JP 2005-142445 A

  An object of the present invention is to provide an epitaxial wafer manufacturing method capable of improving the yield of electronic devices manufactured using an epitaxial wafer in which a nitride semiconductor is formed on a Si substrate.

In order to solve the above-mentioned problem, a method for manufacturing an epitaxial wafer of the present invention includes:
A first step of cleaning the Si substrate by wet etching;
A second step of cleaning the Si substrate by dry etching after the first step;
And a third step of epitaxially growing a nitride semiconductor on the Si substrate after the second step.

  Here, the “Si substrate” is not limited to an intrinsic Si substrate, but may be an n-type doped Si substrate or a p-type doped Si substrate.

According to the above configuration, SiO ₂ remaining on the Si substrate is removed as much as possible by cleaning the Si substrate by wet etching in the first step and then cleaning the Si substrate by dry etching in the second step. In the third step, a nitride semiconductor can be epitaxially grown on a Si substrate free of SiO ₂ residue. Therefore, when the nitride semiconductor is epitaxially grown on the Si substrate, defects due to the SiO ₂ residue on the Si substrate are suppressed. Thereby, the yield of the electronic device produced using the epitaxial wafer in which the nitride semiconductor was formed on Si substrate can be improved.

Moreover, in the manufacturing method of the epitaxial wafer of one embodiment,
In the first step, the Si substrate is cleaned by wet etching using a hydrofluoric acid etchant composed of at least hydrofluoric acid or ammonium fluoride.

According to the above-described embodiment, SiO ₂ remaining on the Si substrate can be efficiently removed by using a hydrofluoric acid-based etchant composed of at least hydrofluoric acid or ammonium fluoride in the first step.

Moreover, in the manufacturing method of the epitaxial wafer of one embodiment,
In the first step, the Si substrate is cleaned by an RCA method.

  Here, RCA cleaning is a cleaning method for a semiconductor substrate developed by RCA in the US, and is a cleaning method using a chemical solution in which alkali or acid is added based on hydrogen peroxide at a high temperature.

According to the embodiment, since particles other than SiO ₂ are removed by cleaning the Si substrate by the RCA method in the first step, generation of pits caused by particles other than SiO ₂ is also suppressed, and The yield of electronic devices manufactured using a wafer can be further improved.

Moreover, in the manufacturing method of the epitaxial wafer of one embodiment,
In the second step, the Si substrate is cleaned using a fluorocarbon-based gas or a mixed gas of hydrogen gas or oxygen gas and the fluorocarbon-based gas.

According to the embodiment, in the second step, a fluorocarbon gas such as CF ₄ or C ₂ F ₆ that is a fluorine-based gas in which carbon is present, or hydrogen gas or oxygen gas and a fluorocarbon-based gas By using this mixed gas, SiO ₂ can be efficiently removed.

Moreover, in the manufacturing method of the epitaxial wafer of one embodiment,
The third step is
Forming an AlN layer on the Si substrate by epitaxial growth;
Forming a GaN-based semiconductor layer on the AlN layer by epitaxial growth.

In this specification, the “GaN-based semiconductor layer” refers to a compound semiconductor represented by Al _x Ga _1-xy In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Say.

According to the above embodiment, the SiO ₂ residue is formed in the AlN layer formed on the Si substrate by forming the AlN layer on the Si substrate by epitaxial growth and forming the GaN-based semiconductor layer on the AlN layer by epitaxial growth. As a result, the defects of the GaN-based semiconductor layer formed on the AlN layer are reduced, and good epitaxial growth can be performed. Thereby, for example, a power device having high breakdown voltage and good characteristics such as an HFET in which a GaN layer or a superlattice layer is formed as a GaN-based semiconductor layer on an AlN layer, and a GaN channel layer and an AlGaN barrier layer are formed thereon. Can be realized.

  As apparent from the above, according to the present invention, the yield of electronic devices manufactured using an epitaxial wafer in which a nitride semiconductor is formed on an Si substrate can be dramatically improved.

FIG. 1A is a flowchart showing an epitaxial wafer manufacturing method according to the first embodiment of the present invention. FIG. 1B is a flowchart showing a conventional epitaxial wafer manufacturing method. FIG. 2 is a diagram showing a CUM plot of longitudinal breakdown voltage after improvement by the epitaxial wafer manufacturing method of the first embodiment. FIG. 3 is a cross-sectional TEM image of a main part including pits of an epitaxial wafer in which a nitride semiconductor is formed on a Si substrate. FIG. 4 is a diagram showing the relationship between the SiO ₂ size and the pit opening diameter. FIG. 5 is a cross-sectional TEM image of a main part including defects due to SiO _{2 having} no pits on the surface of the GaN layer. FIG. 6 is a cross-sectional TEM image of the main part showing the disturbance of the superlattice structure due to minute SiO ₂ . FIG. 7 is a diagram showing a CUM plot of the longitudinal breakdown voltage of a portion where there is no pit on the GaN layer surface. FIG. 8 is a cross-sectional view of an HFET (Hetero-junction Field Effect Transistor) as an example of a power device using an epitaxial wafer manufactured by the epitaxial wafer manufacturing method of the third embodiment of the present invention. is there.

As described with reference to FIGS. 3 to 7, the present inventor has a defect that a residue composed of minute SiO ₂ remaining on the Si substrate before epitaxially growing the nitride semiconductor significantly reduces the yield of the epitaxial wafer. I found out that it generates.

From this, it is necessary to remove the SiO ₂ residue as much as possible in order to eliminate the weak part of the breakdown voltage of the epitaxial wafer in which the nitride semiconductor is formed on the Si substrate. The yield of the electronic device manufactured on top will be determined.

Therefore, in order to improve the yield of an electronic device manufactured using an epitaxial wafer in which a nitride semiconductor is formed on a Si substrate, how can it be performed regardless of the size of SiO ₂ remaining on the Si substrate? It is important to remove the SiO ₂ residue from the Si substrate surface.

Therefore, as a result of studying a method for removing a minute SiO ₂ residue remaining on the Si substrate before the epitaxial growth of the nitride semiconductor, the present inventor effectively removed the SiO ₂ residue on the Si substrate. Thus, the inventors have invented an epitaxial wafer manufacturing method capable of improving the yield of electronic devices manufactured using the epitaxial wafer.

  Hereinafter, an epitaxial wafer manufacturing method of the present invention will be described in detail with reference to embodiments shown in the drawings.

[First Embodiment]
FIG. 1A shows a method of manufacturing an epitaxial wafer according to the first embodiment of the present invention. FIG. 1B is a flowchart showing a conventional epitaxial wafer manufacturing method for comparison.

In the first embodiment, the process proceeds to step S1 (first process) shown in FIG. 1A, and the purchased Si substrate is hydrofluoric acid HF for 1 minute, and H ₂ SO ₄ : H ₂ O ₂ = 5: 1. Etching is performed for 5 minutes and further with HF for 1 minute.

Next, the process proceeds to step S2 (second process) shown in FIG. 1A, where the Si substrate is introduced into the dry etching apparatus, CF ₄ flow rate = 50 sccm, chamber pressure = 0.4 Pa, antenna power = 300 W, bias power. An etching rate of about 200 nm / min can be obtained at 100 W, and the Si substrate is etched for 1 minute.

Next, the process proceeds to step S3 (third process) shown in FIG. 1A, and an Si substrate is introduced into a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, a growth pressure of 13.3 kPa, and a substrate temperature of 1100 ° C. A superlattice layer composed of an AlN seed layer (TMA flow rate 100 μmol / min, NH ₃ flow rate 12.5 slm), a 3 nm thick AlN layer and a 20 nm thick Al _0.1 Ga _0.9 N layer is repeated 120 times ( The AlN layer has the same conditions as the AlN seed layer, the AlGaN layer has a TMA flow rate of 80 μmol / min, a TMG flow rate of 72 μmol / min, an NH ₃ flow rate of 12.5 slm, and a carbon-doped GaN layer is grown by 0.5 μm (TMG flow rate of 720 μmol / min). , NH ₃ flow rate 12.5slm).

Thereafter, a GaN channel layer made of GaN is grown by 1 μm at a growth pressure of 100 kPa (TMG flow rate 100 μmol / min, NH ₃ flow rate 12.5 slm),
Next, the growth pressure is again set to 13.3 kPa to grow an Al _0.17 Ga _0.83 N barrier layer (TMA flow rate 8 μmol / min, TMG flow rate 50 μmol / min, NH ₃ flow rate 12.5 slm).

The carbon-doped GaN layer is automatically doped from the TMG raw material by setting the growth pressure to 13.3 kPa and the TMG flow rate to 720 μmol / min, and a carbon concentration of 1 × 10 ¹⁹ cm ⁻³ can be realized.

On the other hand, in the channel GaN layer, carbon doping of 5 × 10 ¹⁶ cm ⁻³ is realized by setting the growth pressure to 100 kPa and the TMG flow rate to 100 μmol / min. As a method of further reducing the carbon concentration, there is a method of reducing the TMG flow rate to 100 μmol / min or less.

  In the conventional epitaxial wafer manufacturing method shown in FIG. 1B, wet etching is performed in step S11, hydrogen termination treatment is performed in step S12, and epitaxial growth is performed in step S13. Manufacturing of the epitaxial wafer according to the first embodiment shown in FIG. 1A is performed. The second step is different from the method.

  FIG. 2 shows a CUM (cumulative) plot of longitudinal breakdown voltage in the epitaxial wafer manufactured in the first embodiment.

  Compared with the CUM plot of the longitudinal breakdown voltage of the epitaxial wafer shown in FIG. 7 where there is no pit, in FIG. 2, the distribution of the longitudinal breakdown voltage is small and the breakdown point of the breakdown voltage disappears. Yield significantly improves.

Specifically, in the case of the hydrogen termination treatment of Patent Document 1, since the defect density D of the type of defects of FIG. 5 was about 2.8 / cm ² , the 10A class (chip area S = about 2 mm □) Device yield on epitaxial wafer is
Yield = exp (-DxS)
= Exp (-2.8 × 0.2 × 0.2)
= 0.89 ……… Formula (1)
It becomes.

In the case of the hydrogen termination treatment, the yield was only 89%. However, in the epitaxial wafer manufacturing method of the first embodiment, the defect density is 0.5 by introducing the second process using dry etching. The number of wafers / cm ² was improved, and the yield on the epitaxial wafer was improved to about 96%.

  As described above, according to the epitaxial wafer manufacturing method of the first embodiment shown in FIG. 1A, the epitaxial wafer in which the nitride semiconductor is formed on the Si substrate as compared with the conventional epitaxial wafer manufacturing method shown in FIG. 1B. The yield of electronic devices manufactured using can be improved.

In the first step, SiO ₂ remaining on the Si substrate can be efficiently removed by using a hydrofluoric acid-based etchant composed of at least hydrofluoric acid HF or ammonium fluoride NH ₄ F.

In the second step, a fluorocarbon gas such as CF ₄ or C ₂ F ₆ which is a fluorine-based gas in which carbon is present, or a mixed gas of hydrogen gas or oxygen gas and fluorocarbon-based gas is used. By using it, SiO ₂ can be efficiently removed.

[Second Embodiment]
The epitaxial wafer manufacturing method according to the second embodiment of the present invention is the same as the epitaxial wafer manufacturing method according to the first embodiment, except that the purchased Si substrate is cleaned by the RCA method in the first step.

The introduction of RCA method of the first step, since the removal of the SiO ₂ other than the particles is improved, generation of pits caused by other than SiO ₂ particles is suppressed, can further reduce the defect density (D = 0 .2 / cm ² ), the yield on the epitaxial wafer is further improved (about 99%).

  By using the epitaxial wafer manufacturing method of the second embodiment, the yield of electronic devices manufactured using an epitaxial wafer in which a nitride semiconductor is formed on an Si substrate, particularly power devices that require high breakdown voltage, is obtained. Is drastically improved.

[Third Embodiment]
FIG. 8 is a cross-sectional view of an HFET as an example of a power device using an epitaxial wafer manufactured by the epitaxial wafer manufacturing method according to the third embodiment of the present invention.

  As shown in FIG. 8, the epitaxial wafer according to the third embodiment includes an AlN seed layer 2, a superlattice layer 3, a carbon-doped GaN layer 4, a GaN channel layer 5, and an AlGaN barrier layer 6 in this order on an Si substrate 1. Laminated.

  In this HFET, a source electrode 11, a drain electrode 12, and a gate electrode 13 are formed on an AlGaN barrier layer 6 as shown in FIG. The manufacturing method of this source electrode 11, the drain electrode 12, and the gate electrode 13 is not specifically limited, For example, well-known methods, such as vapor deposition, are used. The distance between the source electrode 11 and the drain electrode 12 and the position of the gate electrode 13 are adjusted according to the desired performance of the field effect transistor. Further, after the source electrode 11 and the drain electrode 12 are formed, a heat treatment at 800 ° C. is performed in a nitrogen atmosphere for 1 minute, so that the ohmic contact between the AlGaN barrier layer 6 and the source electrode 11 and the AlGaN barrier layer 6 and the drain electrode 12 are performed. Ohmic contact with is obtained.

  Next, an insulating film 20 made of SiN is formed on the AlGaN barrier layer 6 by a known method such as plasma CVD. Note that the order in which the source electrode 11, the drain electrode 12, the gate electrode 13, and the insulating film 20 are formed is not particularly limited, and the insulating film 20 may be formed first.

  In the HFET, a two-dimensional electron gas (2DEG) formed at the interface between the GaN channel layer 5 and the AlGaN barrier layer 6 is generated to form a channel layer. The channel layer is controlled by applying a voltage to the gate electrode 13 to turn on and off the HFET having the source electrode 11, the drain electrode 12, and the gate electrode 13. The HFET is turned off when a depletion layer is formed in the GaN channel layer 5 under the gate electrode 13 when a negative voltage is applied to the gate electrode 13, while the gate is turned off when the voltage of the gate electrode 13 is zero. This is a normally-on type transistor in which the depletion layer disappears in the GaN channel layer 5 under the electrode 13 and is turned on.

The AlN seed layer 2 is formed on the Si substrate 1 by epitaxial growth using the epitaxial wafer manufacturing method of the first and second embodiments, and the GaN-based semiconductor layer (superlattice layer is formed on the AlN seed layer 2 by epitaxial growth. 3. By forming the carbon-doped GaN layer 4), defects caused by the SiO ₂ residue in the AlN layer formed on the Si substrate 1 are suppressed. Thereby, defects are also reduced in the GaN-based semiconductor layer (superlattice layer 3, carbon-doped GaN layer 4) formed on the AlN seed layer 2, and good epitaxial growth can be performed. Therefore, it is possible to realize an HFET that is a power device having high breakdown voltage and good characteristics.

  As described above, according to the HFET of the third embodiment, the yield of the HFET is remarkably improved by using the epitaxial wafer manufactured by the epitaxial wafer manufacturing method of the first and second embodiments.

  In the third embodiment, the epitaxial wafer manufactured by the epitaxial wafer manufacturing method of the present invention is used for manufacturing an HFET using 2DEG. However, the epitaxial wafer may be used for a semiconductor device such as a field effect transistor having another configuration. Similar effects can be obtained.

  Although specific embodiments of the present invention have been described, the present invention is not limited to the first to third embodiments, and various modifications can be made within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... AlN seed layer 3 ... Superlattice layer 4 ... Carbon dope GaN layer 5 ... GaN channel layer 6 ... AlGaN barrier layer 11 ... Source electrode 12 ... Drain electrode 13 ... Gate electrode 20 ... Insulating film

Claims (5)

A first step of cleaning the Si substrate by wet etching;
A second step of cleaning the Si substrate by dry etching after the first step;
And a third step of epitaxially growing a nitride semiconductor on the Si substrate after the second step. In the manufacturing method of the epitaxial wafer according to claim 1,
The method of manufacturing an epitaxial wafer, wherein the first step includes cleaning the Si substrate by wet etching using a hydrofluoric acid etchant comprising at least hydrofluoric acid or ammonium fluoride. In the manufacturing method of the epitaxial wafer according to claim 1,
In the first step, the Si substrate is cleaned by an RCA method. In the manufacturing method of the epitaxial wafer according to any one of claims 1 to 3,
The method for producing an epitaxial wafer, wherein the second step is performed by cleaning the Si substrate using a fluorocarbon-based gas or a mixed gas of hydrogen gas or oxygen gas and the fluorocarbon-based gas. In the manufacturing method of the epitaxial wafer according to any one of claims 1 to 4,
The third step is
Forming an AlN layer on the Si substrate by epitaxial growth;
And a step of forming a GaN-based semiconductor layer by epitaxial growth on the AlN layer.