JP2016208029A - Nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device which can satisfy both of improvement in a switching speed and improvement in voltage withstanding.SOLUTION: A nitride semiconductor device 3 includes: a nitride semiconductor layer having a gate electrode 19, a source electrode 17 and a drain electrode 18; and a field plate part 192 which is a part of the gate electrode 19. When assuming that a drain voltage value where a value of Cis decreased to 1/2 of a value at the drain voltage of 0 V is V, a breakdown voltage of a device is V, a gate length is L, a field plate length is L, a shallow acceptor concentration is N, a deep acceptor concentration is N, a permittivity of vacuum is εand a relative permittivity of GaN is ε, the following formulas (1) and (2) are satisfied: V<q(N+N)L/2εε (1); V<q(N+N)(L+L)/2εε (2).SELECTED DRAWING: Figure 2

Description

  The present invention relates to a nitride semiconductor device.

  For example, Patent Document 1 discloses a HEMT. This HEMT has a heterojunction structure in which a low-temperature buffer layer made of GaN, a buffer layer made of GaN, an electron transit layer made of GaN, and an electron supply layer made of AlGaN are laminated in this order on a substrate. have. The HEMT includes a source electrode, a gate electrode, and a drain electrode on the electron supply layer.

  In the HEMT, the electron supply layer has a larger band gap energy than the electron transit layer, and a two-dimensional electron gas layer is formed under the heterojunction interface between the two layers. A two-dimensional electron gas layer is used as a carrier. That is, when the source electrode and the drain electrode are operated, electrons supplied to the electron transit layer travel at a high speed in the two-dimensional electron gas layer and move to the drain electrode. At this time, by controlling the voltage applied to the gate electrode to change the thickness of the depletion layer under the gate electrode, electrons moving from the source electrode to the drain electrode, that is, the drain current can be controlled.

Japanese Patent No. 5064824

  In the HEMT as described above, an improvement in switching speed is always required. Although shortening the gate length contributes to higher switching speed, on the other hand, leakage current tends to flow under the gate, which causes a problem that the breakdown voltage is lowered. Therefore, a field plate may be provided on the nitride semiconductor layer in order to suppress the concentration of the electric field, but it is difficult to obtain a sufficient breakdown voltage unless it is installed under appropriate conditions.

  One embodiment of the present invention provides a nitride semiconductor device capable of achieving both improvement in switching speed and improvement in breakdown voltage.

One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, the value of C _oss The drain voltage value that decreases to 1/2 of the value when the drain voltage is 0 V is V ₁ (V), the device breakdown voltage is V ₂ (V), the gate length is L _g (cm), and the field plate length the _L fp (cm), a shallow acceptor concentration _N a (/ ^cm 3), the deep acceptor concentration _N DA (/ ^cm 3), and the vacuum permittivity epsilon _0, a dielectric constant of the nitride semiconductor layer epsilon Then, a nitride semiconductor device that satisfies the following formulas (1) and (2) is provided.

V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
_{V 2 <q (N A +} N DA) · (L g + L fp) 2 / 2ε 0 ε ··· (2)
In this case, the nitride semiconductor device may satisfy the following formulas (3) and (4).
_{q (N A + N DA)} · L g 2 / 2ε 0 ε <1.2V 1 ··· (3)
_{q (N A + N DA)} · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (4)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, the value of C _oss The drain voltage value that decreases to 1/2 of the value when the drain voltage is 0 V is V ₁ (V), the device breakdown voltage is V ₂ (V), the gate length is L _g (cm), and the field plate length L _fp (cm), shallow donor concentration is N _D (/ cm ³ ), deep donor concentration is N _DD (/ cm ³ ) _, shallow acceptor concentration is N _A (/ cm ³ ), and deep acceptor concentration is N _DA (/ cm ³ ). / Cm ³ ), a nitride semiconductor device satisfying the following formulas (5) and (6), where ε _{0 is the} vacuum dielectric constant and ε is the relative dielectric constant of the nitride semiconductor layer.

_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6)
In this case, the nitride semiconductor device may satisfy the following formulas (7) and (8).

_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, the value of C _oss The drain voltage value decreases to 1/2 of the value when the drain voltage is 0 V, V ₁ (V), the maximum rated voltage of the device is V ₂ (V), the gate length is L _g (cm), the field plate length the _L fp (cm), a shallow acceptor concentration _N a (/ ^cm 3), the deep acceptor concentration _N DA (/ ^cm 3), and the vacuum permittivity epsilon _0, a dielectric constant of the nitride semiconductor layer epsilon Then, a nitride semiconductor device that satisfies the following formulas (1) and (2) is provided.

V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
_{V 2 <q (N A +} N DA) · (L g + L fp) 2 / 2ε 0 ε ··· (2)
In this case, the nitride semiconductor device may satisfy the following formulas (3) and (4).
_{q (N A + N DA)} · L g 2 / 2ε 0 ε <1.2V 1 ··· (3)
_{q (N A + N DA)} · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (4)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, the value of C _oss The drain voltage value decreases to 1/2 of the value when the drain voltage is 0 V, V ₁ (V), the maximum rated voltage of the device is V ₂ (V), the gate length is L _g (cm), the field plate length L _fp (cm), shallow donor concentration is N _D (/ cm ³ ), deep donor concentration is N _DD (/ cm ³ ) _, shallow acceptor concentration is N _A (/ cm ³ ), and deep acceptor concentration is N _DA (/ cm ³ ). / Cm ³ ), a nitride semiconductor device satisfying the following formulas (5) and (6), where ε _{0 is the} vacuum dielectric constant and ε is the relative dielectric constant of the nitride semiconductor layer.

_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6)
In this case, the nitride semiconductor device may satisfy the following formulas (7) and (8).

_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, the value of C _oss The drain voltage value that decreases to 1/2 of the value when the drain voltage is 0 V is V ₁ (V), the sheet carrier density of the two-dimensional electron gas is N _s (/ cm ² ), and the gate length is L _g (cm ), Field plate length is L _fp (cm), shallow donor concentration is N _D (/ cm ³ ), deep donor concentration is N _DD (/ cm ³ ) _, shallow acceptor concentration is N _A (/ cm ³ ), deep acceptor. Provided is a nitride semiconductor device that satisfies the following formulas (5) and (9) when the concentration is N _DA (/ cm ³ ), the vacuum dielectric constant is ε ₀ , and the relative dielectric constant of the nitride semiconductor layer is ε. To do.

_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
^{_{N s 2 / (N A +}} N DA -N D -N DD) <(N A + N DA -N D -N DD) · (L g + L fp) 2 ··· (9)
In this case, the nitride semiconductor device may satisfy the following formulas (7) and (10).

_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{(N A + N DA -N D} -N DD) · (L g + L fp) 2 <1.2N s 2 / (N A + N DA -N D -N DD) ··· (10)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, the value of C _oss The drain voltage value that decreases to 1/2 of the value when the drain voltage is 0 V is V ₁ (V), the sheet carrier density of the two-dimensional electron gas is N _s (/ cm ² ), and the gate length is L _g (cm ), The field plate length is L _fp (cm), the shallow acceptor concentration is N _A (/ cm ³ ), the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum dielectric constant is ε ₀ , and the ratio of the nitride semiconductor layer Provided is a nitride semiconductor device that satisfies the following formulas (1) and (11) when the dielectric constant is ε.

V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
^{_{N s 2 / (N A +}} N DA) <(N A + N DA) · (L g + L fp) 2 ··· (11)
In this case, the nitride semiconductor device may satisfy the following formulas (3) and (12).
_{q (N A + N DA)} · L g 2 / 2ε 0 ε <1.2V 1 ··· (3)
_{(N A + N DA) ·} (L g + L fp) 2 <1.2N s 2 / (N A + N DA) ··· (12)
In one embodiment of the present invention, the gate length L _g is at 0.5μm or less, said field plate length L _fp is at 0.5μm or less, the maximum rated voltage of the device may be 50V or higher.

In one embodiment of the present invention, the nitride semiconductor layer includes C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, A deep acceptor level may be formed by doping at least one impurity selected from the group consisting of Mg, Ar, and He.
One embodiment of the present invention includes an electron transit layer, a nitride semiconductor layer including an electron supply layer in contact with the electron transit layer and having a composition different from that of the electron transit layer, a gate on the nitride semiconductor layer, A source plate and a drain; and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, and at least a part of the electron transit layer contains carbon, and the concentration of the carbon A nitride semiconductor device is provided, wherein is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

In one embodiment of the present invention, the electron transit layer includes a first region that forms an interface between the electron transit layer and the electron supply layer, and a second region that is formed in a portion separated by 50 nm or more from the interface. The carbon concentration of the second region may be 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ , and the carbon concentration of the first region may be 1 × 10 ¹⁷ cm ⁻³ or less. .
In one embodiment of the present invention, the shallow donor concentration is N _D (/ cm ³ ), the deep donor concentration is N _DD (/ cm ³ ) _{, the} shallow acceptor concentration is N _A (/ cm ³ ), and the deep acceptor concentration is N _DA. (/ cm ³⁾ and the _{case, N a + N DA -N D} -N DD of the second region of the electron transit layer, even ^{4 × 10 16 cm -3 ~8 ×} 10 16 cm -3 Good.

One embodiment of the present invention includes an electron transit layer, a nitride semiconductor layer including an electron supply layer in contact with the electron transit layer and having a composition different from that of the electron transit layer, a gate on the nitride semiconductor layer, a source and a drain electrically connected to the gate or the source, through an insulating film and a field plate disposed on the nitride semiconductor layer, a gate length L _g is at 0.6μm or less, Carbon is contained in at least a part of the electron transit layer, the concentration of the carbon is 1 × 10 ¹⁸ cm ⁻³ or more, the thickness of the insulating film under the field plate is d, Provided is a nitride semiconductor device that satisfies d / ε ≦ 14 when the dielectric constant is ε.

According to an embodiment of the present invention, when a voltage is applied between the source and the drain when the gate is turned off, the nitride semiconductor layer under the gate is formed as shown in the above formulas (1) and (5). The voltage when the region punches through (the right side of each equation) is larger than the voltage V ₁ (the left side of each equation) at which the two-dimensional electron gas disappears. As a result, punch-through under the gate can be prevented, and the occurrence of leakage current at the time of OFF can be suppressed.

Further, as shown in the above formulas (2), (6), (9), and (11), the voltage (right side of each formula) when the region of the nitride semiconductor layer under the field plate punches through is the device. because of greater than the breakdown voltage V ₂ or the maximum rated voltage V _2, it is possible to realize a highly reliable device.
Then, the breakdown voltage and the effect of improving the reliability as described above, as is apparent from the equation, even with a shorter gate length L _g, term calculated (shallow acceptors other than the gate length L _g of each formula it can be achieved by adjusting the concentration N _a, the deep acceptor concentration N _DA, etc.). Therefore, by designing the gate length _Lg to a desired length, the switching speed of the device can be improved while maintaining the breakdown voltage.

FIG. 1 is an external view of a semiconductor package including a nitride semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device. Figure 3A _is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD. 3B _is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD. 3C _is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD. Figure 4A is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD of semi-insulating GaN layer. Figure 4B is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD of semi-insulating GaN layer. FIG. 5 is a diagram illustrating the IV characteristics of FIGS. 4A and 4B. FIG. 6 is a graph showing the relationship between the drain voltage V _D and the output capacitance C _oss . FIG. 7 is a diagram for explaining how to obtain the depletion voltage of the two-dimensional electron gas under the field plate. FIG. 8 is a diagram for explaining how to obtain the depletion voltage of the two-dimensional electron gas in the region between the end of the field plate and the drain. FIG. 9 is a diagram for explaining the trap concentration dependence of current. FIG. 10A to FIG. 10C are energy band diagrams showing the movement of electrons over time until current starts flowing. FIG. 11 is a simulation result showing the potential distribution of the nitride semiconductor device according to the reference example. FIG. 12 is a simulation result showing the current density of the nitride semiconductor device according to the reference example. FIG. 13 is a simulation result showing the trap occupation ratio of the nitride semiconductor device according to the reference example. FIG. 14 is a simulation result showing a potential distribution of a nitride semiconductor device according to an embodiment of the present invention. FIG. 15 is a simulation result showing the current density of the nitride semiconductor device according to the embodiment of the present invention. FIG. 16 is a simulation result showing the trap occupation ratio of the nitride semiconductor device according to the embodiment of the present invention. FIG. 17 is a graph comparing the leakage currents of the present embodiment and the reference example. Figure 18 is a diagram showing the relationship between the carbon concentration and the _{N A + N DA -N D -N} DD. FIG. 19A is a diagram showing a reference structure 1 set for simulation. FIG. 19B is a diagram showing the reference structure 2 set for simulation. FIG. 20A is a diagram showing the relationship between the carbon concentration and the sheet resistance of the two-dimensional electron gas. FIG. 20B is a diagram showing the relationship between the carbon concentration and the mobility of the two-dimensional electron gas. FIG. 20C is a diagram showing the relationship between the carbon concentration and the sheet carrier density of the two-dimensional electron gas. Figure 21 is a diagram showing the relationship between sheet carrier density N _s and mobility of two-dimensional electron gas (2DEG mobility). FIG. 22A is a diagram showing the structure of AlGaN / GaN between the gate and the drain. FIG. 22B is a diagram showing an AlGaN / GaN structure in the gate portion. FIG. 23 is a diagram showing the relationship between the gate length and the gate breakdown voltage. Figure 24 _is a diagram showing the relationship between _{N A + N DA -N D -N} DD and depletion voltage under the field plate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is an external view of a semiconductor package 1 including a nitride semiconductor device 3 according to an embodiment of the present invention.
The semiconductor package 1 includes a terminal frame 2, a nitride semiconductor device 3 (chip), and a resin package 4.

  The terminal frame 2 is a metal plate shape. The terminal frame 2 includes a base portion 5 (island) that supports the nitride semiconductor device 3, a drain terminal 6, a source terminal 7, and a gate terminal 8. The drain terminal 6 is formed integrally with the base portion 5. The drain terminal 6, the source terminal 7, and the gate terminal 8 are electrically connected to the drain, source, and gate of the nitride semiconductor device 3 by bonding wires 9 to 11, respectively. The source terminal 7 and the gate terminal 8 are arranged so as to sandwich the central drain terminal 6.

The resin package 4 is made of a known mold resin such as an epoxy resin, for example, and seals the nitride semiconductor device 3. The resin package 4 covers the base portion 5 of the terminal frame 2 and the bonding wires 9 to 11 together with the nitride semiconductor device 3. Some of the three terminals 6 to 8 are exposed from the resin package 4.
FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 3. Note that FIG. 2 does not show a cut surface at a specific position in FIG. 1, but shows a cross section of an assembly of elements considered necessary for the description of the present embodiment.

  The nitride semiconductor device 3 includes a substrate 12, a buffer layer 13 formed on the surface of the substrate 12, an electron transit layer 14 epitaxially grown on the buffer layer 13, and an electron supply layer epitaxially grown on the electron transit layer 14. 15 and the like. Further, the nitride semiconductor device 3 is in ohmic contact with the electron supply layer 15 through the gate insulating film 16 covering the surface of the electron supply layer 15 and the contact holes 17a and 18a formed in the gate insulating film 16. A source electrode 17 and a drain electrode 18 as ohmic electrodes are included. The source electrode 17 and the drain electrode 18 are arranged at an interval, and the gate electrode 19 is arranged between them. The gate electrode 19 faces the electron supply layer 15 through the gate insulating film 16.

The substrate 12 may be, for example, a conductive silicon substrate. The conductive silicon substrate may have an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (more specifically, about 1 × 10 ¹⁸ cm ⁻³ ), for example.
The buffer layer 13 may be a multilayer buffer layer in which a first buffer layer 131 and a second buffer layer 132 are stacked. The first buffer layer 131 is in contact with the surface of the substrate 12, and the second buffer layer 132 is stacked on the surface of the first buffer layer 131 (the surface opposite to the substrate 12). In this embodiment, the first buffer layer 131 is composed of an AlN film, and the film thickness thereof may be, for example, about 0.2 μm. In the present embodiment, the second buffer layer 132 is composed of an AlGaN film, and the film thickness may be, for example, about 0.2 μm.

The gate insulating film 16 may be a multilayer gate insulating film in which a first insulating layer 161 and a second insulating layer 162 are stacked. The first insulating layer 161 is in contact with the surface of the electron supply layer 15, and the second insulating layer 162 is laminated on the surface of the first insulating layer 161 (the surface opposite to the electron supply layer 15). In the present embodiment, the first insulating layer 161 is composed of a SiN film, and the film thickness may be, for example, about 500 mm. Such a first insulating layer 161 can be formed by plasma CVD (chemical vapor deposition), thermal CVD, sputtering, or the like. The first insulating layer 161 has an opening 161 a for allowing the second insulating layer 162 to enter and contact the electron supply layer 15. In the present embodiment, the second insulating layer 162 is made of alumina (Al _a O _b ), and the film thickness thereof may be about 300 mm, for example. The second insulating layer 162 has a recess 162a at a portion of the first insulating layer 161 that enters the opening 161a. Such a second insulating layer 162 can be formed by precisely controlling the film thickness by, for example, the ALD method or the like.

When an alumina film is to be formed by the ALD method, generally, the composition ratio a: b between Al and O varies, and not all of them are Al ₂ O ₃ . This is because the ALD method is a relatively low temperature process. However, an insulator made of Al and O can form an insulator layer having a large band gap and a high breakdown voltage without strictly controlling the composition. In this specification, the term “alumina” is used even when the composition ratio a: b of Al and O is other than 2: 3.

The electron transit layer 14 and the electron supply layer 15 are made of a group III nitride semiconductor (hereinafter simply referred to as “nitride semiconductor”) having different Al compositions. For example, the electron transit layer 14 may be composed of a GaN layer, and the thickness thereof may be about 0.5 μm. In the present embodiment, the electron supply layer 15 is composed of an Al _x Ga _1-x N layer (0 <x <1), and has a thickness of, for example, 5 nm to 30 nm (more specifically, about 20 nm). is there.

  Thus, the electron transit layer 14 and the electron supply layer 15 are made of nitride semiconductors having different Al compositions, form a heterojunction, and have a lattice mismatch between them. Then, due to polarization caused by the heterojunction and lattice mismatch, the two-dimensional electron gas is located at a position close to the interface between the electron transit layer 14 and the electron supply layer 15 (for example, a position about several kilometers away from the interface). 20 is spreading.

With respect to the energy band structure of the electron transit layer 14, a shallow donor level E _D , a deep donor level E _DD , a shallow acceptor level E _A , and a deep acceptor level E _DA may be formed.
The shallow donor level E _D is, for example, an energy level at a position separated by 0.025 eV or less from the energy level E _{C at} the lower end (bottom) of the conduction band of the electron transit layer 14, and the deep donor level E If it can be distinguished from _DD , it may be simply referred to as “donor level E _D ”. Normally, donor electrons doped at this position are excited to the conduction band at room temperature (thermal energy kT = about 0.025 eV) and become free electrons. As an impurity to be doped into GaN channel layer 14 to form a shallow donor level E _D, for example, Si, at least one can be mentioned is selected from the group consisting of O. On the other hand, the deep donor level E _DD is, for example, an energy level at a position separated by 0.025 eV or more from the energy level E _{C at} the lower end (bottom) of the conduction band of the electron transit layer 14. That is, the deep donor level E _DD is formed by doping a donor whose ionization energy required for excitation is larger than the thermal energy at room temperature. Therefore, usually, the donor electron doped at this position is not excited by the conduction band at room temperature and is captured by the donor.

Shallow acceptor level E _A is, for example, energy level at a position below the distant 0.025eV from the energy level E _V of the valence of the upper end of the electron transit layer 14 (top), a deep acceptor level E If it can be distinguished from _DA , it may be simply called “acceptor level E _A ”. Normally, acceptor holes doped in this position are excited to valence band at room temperature (thermal energy kT = about 0.025 eV) and become free holes. On the other hand, a deep acceptor level _{E DA} is, for example, the energy level at remote location over 0.025eV from energy level _{E V} of the valence of the upper end of the electron transit layer 14 (top). In other words, the deep acceptor level E _DA is formed by acceptor doping in which the ionization energy necessary for excitation is larger than the thermal energy at room temperature. Therefore, the acceptor hole doped at this position is not normally excited to the valence band at room temperature and is captured by the acceptor. Mg is known as an impurity that generates holes at room temperature, but its activation rate (ratio of holes generated with respect to the doped amount) is 1/10 or less, and Mg is a shallow acceptor. Although it can be interpreted as a deep acceptor, in the present invention, N _A + N _DA is an important value, so it can be interpreted as either. Impurities doped in the electron transit layer 14 made of GaN to form the deep acceptor level E _DA include, for example, C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K And at least one selected from the group consisting of Sc, Zr, Fe, Co, Ni, Mg, Ar and He.

In this embodiment, the concentrations of impurities (dopants) that form the shallow donor level E _D , the deep donor level E _DD , the shallow acceptor level E _A, and the deep acceptor level E _DA described above are respectively set. These are referred to as a shallow donor concentration N _D , a deep donor concentration N _{DD, a} shallow acceptor concentration N _A , and a deep acceptor concentration N _DA .
The impurity concentration of the whole electron transit layer 14 _is preferably _{N A + N DA -N D -N} DD> 0. This inequality captures the emitted electrons rather than the sum of the impurity concentrations of donor atoms that can emit electrons (N _D + N _DD , and this sum is sometimes referred to as donor concentration N _d ). (a N a ₊ N _DA, hereinafter it may. call this sum the trap density N _t) the sum of the impurity concentration of the acceptor atom capable of means that large. That is, in the electron transit layer 14, almost all of the electrons emitted from the shallow donor atoms and the deep donor atoms are captured by the shallow acceptor atoms or the deep acceptor atoms without being excited by the conduction band. Semi-insulating i-type GaN.

However, at least one selected from the group consisting of C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, Mg, Ar, and He Even if the impurities are doped, not all the impurities function as deep acceptors. For example, in the case of C (carbon), it functions as a deep acceptor by replacing the N (nitrogen) site in the group III nitride semiconductor crystal. However, it functions as a shallow donor by replacing the group III element site. The rate of replacement for each site depends on the doped carbon concentration. In addition, crystal defects are generated by doping impurities, and it is unclear which crystal defect functions as a shallow donor, a deep donor, a shallow acceptor, or a deep acceptor. Therefore, SIMs (Secondary Ion Mass Spectrometry: secondary ion mass spectrometry) _N A _{+ N DA} is not possible to know the value of -N D _{-N DD} impurity concentration measurement by.

Measurement of the value of _{N A + N DA -N D -N} DD has been found that it is possible to carry out the measurement of the longitudinal leakage current of semi-insulating layer as shown in Figure 3A. As described above, the electron transit layer is a semi-insulating layer in which electrons emitted from a shallow donor and a deep donor are captured by a shallow acceptor and a deep acceptor. As shown in FIG. 10A, when these layers are not biased, there are deep acceptor levels that do not capture electrons, and vacant seats exist in the deep acceptors. At this time, the GaN layer is electrically neutral. As shown in FIG. 10B, under an external voltage below a certain level, electrons are captured by a deep acceptor that has not captured electrons under no bias, and the positive bias side is negatively charged and cancels the electric field. It is minute. In this case, a partial area of the positive bias side of the semi-insulating layer is negatively charged, the charge density is _{N A + N DA -N D -N} DD. When a voltage higher than a certain level is applied, electrons are trapped in all deep acceptor levels, and the electric field beyond that cannot be canceled, and the current starts to increase. At this time, the semi-insulating layer is negatively charged in all areas, the charge density is _{N A + N DA -N D -N} DD. Thus, when _{N A + N DA -N D -N} DD distribution of the semi-insulating layer is uniform, the elementary electric charge of the thickness of the q semi-insulating layer d, When voltage _{V TH} which current begins to increase Using the Poisson equation,
N _A + N _DA −N _D −N _DD = 2εε ₀ V _TH / qd ²
Can be obtained.

In this measurement, an electrode may be formed on the semi-insulating layer through a conductive layer and a conductive substrate as shown in FIGS. 3B and 3C.
When GaN is grown on a different substrate, it is necessary to introduce a buffer layer between the GaN and the substrate. For example, in the case of semi-insulating GaN on a Si substrate, a semi-insulating buffer layer composed of a stack of AlN and AlGaN is included between the conductive substrate and the semi-insulating GaN layer to be measured. Since these buffer layers that are expected to have different _{N A + N DA -N D -N} DD is a semi-insulating GaN layer, to measure the _{N A + N DA -N D -N} DD of semi-insulating GaN layer 4A and 4B, a sample grown to the buffer layer and a sample grown to the semi-insulating GaN layer are prepared, and a positive bias is applied to the substrate side electrode. The difference of [Delta] V _TH of _{V TH} of each sample, the semi-insulating GaN layer thickness _{d GaN,} a buffer layer thickness and _{d buffer, N A + N DA} -N D -N DD of semi-insulating GaN layer,
_{N A + N DA -N D -N} DD = 2εε 0 ΔV TH / q (d GaN 2 + 2d GaN d buffer)
Can be obtained.

For example, when the thickness of the semi-insulating GaN layer grown under a certain condition is 1.5 μm and the thickness of the buffer layer is 0.2 μm, the IV characteristic shown in FIG. 5 is obtained. _a + _N DA _-N D _{-N DD} can be determined as 3.2 × ^{10 16} / cm ^3.
The electron supply layer 15 may have an AlN layer having a thickness of about several atoms (5 nm or less, preferably 1 nm to 5 nm, more preferably 1 nm to 3 nm) at the interface with the electron transit layer 14. Such an AlN layer suppresses electron scattering and contributes to an improvement in electron mobility.

  The gate electrode 19 may be composed of a laminated electrode film having a lower layer in contact with the gate insulating film 16 and an upper layer laminated on the lower layer. The lower layer may be made of Ni, Pt, Mo, W or TiN, and the upper layer may be made of Au or Al. The gate electrode 19 is biased toward the source electrode 17, and thus has an asymmetric structure in which the gate-drain distance is longer than the gate-source distance. This asymmetric structure alleviates a high electric field generated between the gate and the drain and contributes to an improvement in breakdown voltage.

The gate electrode 19 includes a gate main body 191 that enters a recess 162a formed in the second insulating layer 162 between the source electrode 17 and the drain electrode 18, and a gate main body 191 that is continuous with the gate main body 191 and outside the opening 161a. 16 has a field plate portion 192 extending toward the drain electrode 18. The distance L _fp from the drain end 191a that is the end on the drain electrode 18 side at the interface between the gate body 191 and the second insulating layer 162 to the end on the drain electrode 18 side of the field plate portion 192 is the field plate length be called. On the other hand, the distance _{L g} of the drain terminal 191a at the interface between the gate body portion 191 and the second insulating layer 162 to the source terminal 191b which is an end portion of the source electrode 17 side is referred to as the gate length. That is, the width of the effective gate region (region in the recess 162a) Ga that is a contact region between the gate electrode 19 and the bottom surface of the recess 162a of the second insulating layer 162 is called a gate length. Further, in this specification, the distance between the gate body 191 and the drain electrode 18 is represented as L _gd .

Field plate length L _fp is preferably 1/10 or more and 1/2 or less of gate-drain distance L _gd . Specifically, it may be 0.1 μm or more and 0.5 μm or less. On the other hand, the gate length _{L g} is preferably 0.1μm or more 1.0μm or less. Specifically, it may be 0.2 μm or more and 0.5 μm or less.
The source electrode 17 and the drain electrode 18 are, for example, ohmic electrodes containing Ti and Al, and are electrically connected to the two-dimensional electron gas 20 via the electron supply layer 15.

  Bonding wires 9 to 11 shown in FIG. 1 are connected to the drain electrode 18, the source electrode 17, and the gate electrode 19, respectively. A back electrode 21 is formed on the back surface of the substrate 12, and the substrate 12 is connected to the base portion 5 through the back electrode 21. Therefore, in the present embodiment, the substrate 12 is electrically connected to the drain electrode 18 via the bonding wire 9 and has a drain potential.

  In the nitride semiconductor device 3, the electron supply layer 15 having a different Al composition is formed on the electron transit layer 14 to form a heterojunction. As a result, a two-dimensional electron gas 20 is formed in the electron transit layer 14 near the interface between the electron transit layer 14 and the electron supply layer 15, and a HEMT using the two-dimensional electron gas 20 as a channel is formed. The gate electrode 19 faces the electron supply layer 15 with the gate insulating film 16 interposed therebetween. When an appropriate negative voltage is applied to the gate electrode 19, the channel formed by the two-dimensional electron gas 20 can be cut off. Therefore, by applying a control voltage to the gate electrode 19, the source-drain can be turned on / off.

In use, for example, a predetermined voltage (for example, 200 V to 600 V) that is positive on the drain electrode 18 side is applied between the source electrode 17 and the drain electrode 18. In this state, an off voltage (for example, −5 V) or an on voltage (for example, 0 V) is applied to the gate electrode 19 with the source electrode 17 as the reference potential (0 V).
In the nitride semiconductor device 3 operating as described above, the nitride semiconductor device 3 satisfies the following formula (1) or (5) in order to improve the breakdown voltage.

V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
In the above formulas (1) and (5), ε ₀ is the vacuum dielectric constant, and ε is the relative dielectric constant of the electron transit layer 14 (GaN). V _{1 on} each left side of the expressions (1) and (5) indicates a voltage when the electron traveling layer 14 under the field plate portion 192 is depleted and the two-dimensional electron gas 20 is depleted in the region. . On the other hand, each right side of the equations (1) and (5) indicates a voltage when punch-through occurs under the gate and a leak current starts to flow. In other words, the inequalities expressed by the equations (1) and (5) indicate that the electron traveling layer 14 does not punch through under the gate until the electron traveling layer 14 is depleted under the field plate portion 192, thereby causing leakage current under the gate. It can be reduced. Next, how to obtain the left side and the right side of Equations (1) and (5) will be described.

First, with respect to the left side of the expressions (1) and (5), V ₁ indicates a drain voltage value that decreases to 1/2 of the value when the value of C _oss is the drain voltage 0 V, and the drain voltage V _D When the relationship with the output capacitance C _{oss of the} device is shown in a graph, the drain voltage V ₁ shown in FIG. 6 is obtained. The voltage V _1, the field plate portion 192 electron transit layer 14 below is depleted, defined as the voltage at which the two-dimensional electron gas 20 in the region disappears.

For example, as shown in the right diagram of FIG. 7, when an appropriate negative voltage is applied to the gate electrode, the two-dimensional electron gas is depleted under the field plate (FP) connected to the gate electrode. Polarization occurs between the GaN negatively charged layer (a part of the electron transit layer 14 of the present embodiment) and the AlGaN layer (electron supply layer 15 of the present embodiment) thereon. At this time, an electric flux is generated in the upward direction from the AlGaN layer toward the field plate FP. The electric flux density D is equal to the sum of charges in the GaN negatively charged layer, which is a closed space facing the AlGaN layer, based on Gauss's theorem (divD = ρ). The thickness of the GaN negatively charged layer is W, the sheet carrier density of the two-dimensional electron gas in the GaN negatively charged layer to _{N s, D = q {N} s -W (N t -N d)} is derived. Since D = εE (ε is the relative dielectric constant of GaN) and V ₁ = ∫Edz (z is the thickness direction of the GaN negatively charged layer), V ₁ = ∫q {N _s −W ( N _t −N _d )} / εdz is obtained. Depletion of the two-dimensional electron gas under the field plate FP is calculated by substituting a value designed for each device into V ₁ = ∫q {N _s −W (N _t −N _d )} / εdz. it can be obtained a voltage _{V 1.} A smaller depletion voltage V ₁ is preferable because depletion is easier. For this purpose, for example, the insulating film under the field plate (in this embodiment, the gate insulating film 16) is thinned, or the insulating film is reduced. It may be made of a material having a high dielectric constant. 7 shows the distribution of potential Φ and the distribution of electric flux density D when the two-dimensional electron gas is depleted.

For reference, a method of obtaining the depletion voltage V ₃ of the two-dimensional electron gas from the end of the field plate 192 on the drain electrode 18 side to the drain electrode 18 will be described with reference to FIG. 7 can be considered, for example, in a state where the GAN negative charge layer is depleted, q {N _s −W (N _t −N _d )} is contained in the GaN negative charge layer which is a closed space. Although there is an electric charge, the field plate FP is not provided above the GaN negatively charged layer in this region, so that no upward electric flux is generated from the AlGaN layer. Therefore, D = q {N _s −W (N _t −N _d )} = 0, and W = N _s / (N _t −N _d ) is derived from this equation. The depletion voltage _{V 3} in the region, derived from Poisson's _equation, and _{V 3 = q (N t -N} d) W 2 / 2ε. Since W = N _s / (N _t −N _d ), the depletion voltage V ₃ can be defined by the trap concentration N _t and the donor concentration N _d regardless of the thickness W of the GaN negatively charged layer. .

Next, the right side of Expressions (1) and (5) will be described with reference to FIGS. 9 and 10A to 10C. As shown in FIG. 9, a GaN layer having a thickness W = 5 μm, a shallow donor concentration N _D = 0.5 × 10 ¹⁶ cm ⁻³ , and a deep acceptor level E _DA = 0.7 eV as a sample configuration for simulation. Set. When the went increasing voltage (bias) between the electrodes of the front and back surfaces of the GaN layer was examined whether the rise of the current is how to vary with the deep acceptor concentration N _DA. Then, as apparent from the graph of FIG. 9, although the rising voltages were different, graphs having substantially the same waveform were obtained. That is, FIG. 9 indicates that the voltage at which current starts to flow in GaN depends on the trap concentration (in this simulation, the deep acceptor concentration N _DA ).

More specifically, as shown in FIG. 10A, first, when no voltage is applied between the two electrodes (when no bias is applied), the acceptor and the deep acceptor emit electrons emitted from the donor and the deep donor. To capture. At this time, since the number of positive charges due to the donor that emitted electrons and the deep donor is equal to the number of negative charges due to the acceptor that captured electrons and the deep acceptor, the GaN layer as a whole becomes electrically neutral. Next, when a voltage is applied as shown in FIG. 10B, electrons are captured from the valence band (E _V ) to the deep acceptor on the positive bias side, and are negatively charged. Since the electric flux generated by applying the voltage is canceled by the negatively charged region, the flowing current is extremely small. As shown in FIG. 10C, when a voltage higher than a certain level is applied, electron capture occurs in deep acceptors in all regions. Even if a voltage higher than this is applied, electron capture does not occur, and the electric flux cannot be canceled out, so that current flows out. The equation including the voltage V at this time is derived from the Poisson equation as N _A + N _DA −N _D −N _DD = 2Vε ₀ ε / qW ^2, and as a result, V = q (N _A + N _DA −N _D −N _DD ) · W ² / 2ε ₀ ε. When this is applied to this embodiment, when leak current flows under the gate, punch-through occurs in the lateral direction from the drain side to the source side in the region under the gate. Therefore, instead of the thickness W of the GaN layer, the gate length L _g may be used. Thus, a right side of the equation _{(5) q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε is derived. On the other hand, the right side of the equation (1) is different from the formula (5) in that Equation (5) of the _{(N A + N DA -N D} -N DD) is in the _(N A _{+ N DA),} N _A + N _DA is the minimum amount necessary to cancel the electric flux, and it is sufficient to satisfy the right side of Equation (1). However, in consideration of the presence of residual donors in GaN, the equation (5) N _A + N _DA −N _D −N _DD is more preferable. In addition, the nitride semiconductor device 3 satisfies the following formula (2) or (6) in order to further improve the reliability regarding the breakdown voltage. Yes.

_{V 2 <q (N A +} N DA) · (L g + L fp) 2 / 2ε 0 ε ··· (2)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6)
In the above formulas (2) and (6), V ₂ is the breakdown voltage or maximum rated voltage of the device, ε ₀ is the vacuum dielectric constant, and ε is the relative dielectric constant of the electron transit layer 14 (GaN). . Since V _{2 on} each left side of the expressions (2) and (6) is the breakdown voltage or the maximum rated voltage of the device, it is a value determined according to each device. On the other hand, the right sides of the equations (2) and (6) indicate the voltages at which punch-through occurs under the field plate and the gate and the leakage current begins to flow. In other words, the inequalities expressed by the equations (2) and (6) indicate that the breakdown voltage or the maximum of the nitride semiconductor device 3 is higher than the applied voltage when the leak current starts to flow under the field plate and the gate. The rated voltage is exceeded, which indicates that the breakdown voltage and maximum rated voltage specified for each device are highly reliable.

The dielectric breakdown voltage is a voltage at which the element itself is destroyed and cannot be used, or the off-leakage current increases rapidly. On the other hand, the maximum rated voltage is a voltage that must not be exceeded in order to maintain the reliability of the element.
The method for obtaining the right side of the equations (2) and (6) can be considered in the same manner as the right sides of the above equations (1) and (5). Because when the leakage current flows under the field plate and the gate punch through occurs in the transverse direction to the source side from the drain side area below the field plate and gate, the aforementioned _{V = q (N A + N} DA -N D -N _DD ) · W ² / 2ε _{0 In} place of the thickness W of the εGaN layer, the sum of the gate length and the field plate length (L _g + L _fp ) may be used. Thus, equation (2) and a right-hand side _q of _{(6) (N A + N} DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε is derived.

The nitride semiconductor device 3 satisfies the above formulas (1), (2), (5) and (6), but more preferably, the following formula (3), (4), (7) or (8) is satisfied. Fulfill.
_{q (N A + N DA)} · L g 2 / 2ε 0 ε <1.2V 1 ··· (3)
_{q (N A + N DA)} · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (4)
_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8)
By satisfying the formula (3), (4), (7) or (8), the parasitic capacitance can be made extremely small while maintaining the withstand voltage and reliability, and the high-speed switching operation can be performed.

Next, simulations of potential distribution, current density, and trap occupancy for devices that satisfy and do not satisfy the above formulas (1), (2), (5), and (6) are shown in FIGS. The result was obtained.
11 to 13 are simulation results of the nitride semiconductor device according to the reference example (not satisfying the above formulas (1), (2), (5) and (6)), FIG. 11 is a potential distribution, and FIG. Indicates the current density, and FIG. 13 indicates the trap occupation ratio. On the other hand, FIGS. 14 to 16 are simulation results of the nitride semiconductor device according to the present embodiment (the above expressions (1), (2), (5), and (6) are satisfied), and FIG. FIG. 15 shows the current density, and FIG. 16 shows the trap occupation ratio.

First, a device according to a reference example is verified with reference to FIGS. Verification, the drain voltage = 20V, GaN donor concentration ^{_{N D = 1 × 10 16 cm}} -3, the deep acceptor concentration of _{^{GaN N DA = 0.5 × 10 16}} cm -3, the field plate of a dielectric film: SiO ₂ The measurement was performed under the conditions of (thickness 100 nm). As a result of the verification, in the reference example, as shown in FIG. 11, no voltage drop was observed under the field plate, and a voltage drop occurred at the end of the gate. As a result, as shown in FIG. 12, a leakage current is generated from the drain side to the source side across the gate. Referring to FIG. 13, it can be seen that the traps (deep acceptors) under the gate are all filled with electrons, and that punch-through occurs under the gate.

On the other hand, in the device of this embodiment verified under the same conditions as in the reference example except that the thickness of the insulating film under the field plate is 10 nm and the depletion voltage V ₁ is lowered, as shown in FIG. A voltage drop occurred at the end of the field plate, and as a result, almost no leakage current flowed under the gate as shown in FIG. Moreover, when the trap occupation rate was confirmed in FIG. 16, it was found that the trap under the gate still had room for capturing electrons.

FIG. 17 shows a comparison of leakage current between the device of this embodiment and the device of the reference example. As shown in FIG. 17, a device satisfying the above formulas (1), (2), (5), and (6) has almost no leakage current when the gate is turned off. It was found that can be improved. Then, the breakdown voltage and the effect of improving the reliability as described above, as is apparent from the equation, even with a shorter gate length L _g, term calculated (shallow acceptors other than the gate length L _g of each formula it can be achieved by adjusting the concentration N _a, the deep acceptor concentration N _DA, etc.). Therefore, by designing the gate length _Lg to a desired length, the switching speed of the device can be improved while maintaining the breakdown voltage.

Next, the relationship between the impurity concentration of carbon and N _A + N _DA −N _D −N _DD when C (carbon) is doped as an impurity in the electron transit layer 14 will be described.
Figure 18 is a diagram showing the relationship between the carbon concentration and the _{N A + N DA -N D -N} DD. First, the above inequality (5) is referred to.
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
This equation (5) indicates that the electron transit layer 14 does not punch through under the gate until it is depleted under the field plate portion 192, thereby reducing the leakage current under the gate. Therefore, in order to reduce the on-resistance during the operation of the nitride semiconductor device 3 while satisfying the formula (5), the gate length _Lg is shortened to reduce the gate resistance component, and N _A + N _DA −N _D it is preferred to maximize the value of -N _DD.

In this regard, referring to FIG. 18, even if a large amount of carbon is doped as an impurity, the carbon concentration is about 1 × 10 ¹⁹ cm ⁻³ and the value of N _A + N _DA −N _D −N _DD is saturated. . On the other hand, doping carbon with a concentration of 1 × 10 ¹⁹ cm ⁻³ is not preferable because the crystal quality of the electron transit layer 14 is lowered. That is, it can be seen from FIG. 18 that the carbon concentration is preferably in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . Within this range, even if the gate length _Lg is shortened and the gate resistance component is reduced, the value of N _A + N _DA −N _D −N _DD can be increased within a range that does not affect the crystal quality. The expression (5) can be satisfied while reducing the on-resistance of the nitride semiconductor device 3.

The carbon concentration in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ may be applied to the entire electron transit layer 14, but preferably from the interface with the electron supply layer 15. It is preferable that a carbon concentration lower than the above range is applied to an interface portion with the electron supply layer 15 that is applied to a remote region. This is evidenced by FIGS. 19A, 19B, 20A, 20B and 20C.

19A and 19B are diagrams showing a reference structure 1 and a reference structure 2 set for simulation, respectively. In FIG. 19A and FIG. 19B, among the reference symbols shown in FIG. 2, only the symbols necessary for the following description are shown, and the other corresponding portions are omitted.
19A and 19B, the difference between reference structure 1 and reference structure 2 is that the first region in which electron transit layer 14 of reference structure 1 forms the interface between electron transit layer 14 and electron supply layer 15. 141 and a second region 142 formed in a portion away from the interface (in this embodiment, 0.3 μm = 300 nm). Common to both structures, the pressure unit written to the left of “GaN” in the electron transit layer 14 indicates the growth pressure when GaN is grown. When growing GaN using MOCVD, the amount of carbon contained in TMG, which is a Ga (gallium) source, can be increased in the GaN crystal by lowering the growth pressure and growth temperature when growing GaN. it can. Therefore, in the reference structure 1 of FIG. 19A, the carbon concentration of the second region 142 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ , while the carbon concentration of the first region 141 is 1 × 10 ¹⁷ cm. ^-3 or less. Moreover, in the reference structure 2 of FIG. 19B, the carbon concentration of the whole electron transit layer 14 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

For each structure, FIG. 20A shows the relationship between the carbon concentration and the sheet resistance of the two-dimensional electron gas, and FIG. 20B shows the relationship between the carbon concentration and the mobility of the two-dimensional electron gas. FIG. 20C shows the relationship between the carbon concentration and the sheet carrier density of the two-dimensional electron gas.
As shown in FIGS. 20A to 20C, in the reference structure 2, as a result of uniformly increasing the carbon concentration of the electron transit layer 14, the sheet resistance of the two-dimensional electron gas is increased and the mobility of the two-dimensional electron gas is increased. And the sheet carrier density was lowered. On the other hand, in Reference Structure 1, the carbon concentration at the interface with the electron supply layer 15 is suppressed to a low level of 1 × 10 ¹⁷ cm ⁻³ or less, so that the sheet resistance, mobility, and sheet carrier of the two-dimensional electron gas are reduced. There was little change in density.

On the other hand, as shown in FIG. 21, in the AlGaN / GaN junction, the mobility of the two-dimensional electron gas depends on the sheet carrier density N _s , and is generally N _s = 8 × 10 ¹² cm ⁻² to 1 ×. It has been found that the maximum value is in the range of 10 ¹³ cm ⁻² . Therefore, in the following, on the premise that N _s = 8 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² , a preferable gate length L _g is calculated, and the gate length L _g and the thickness of the gate insulating film 16 are calculated. Sought the relationship.

First, between the gate and the drain, as shown in FIG. 22A, the two-dimensional electron gas (2DEG) spreads at the AlGaN / GaN interface due to polarization caused by these heterojunctions and lattice mismatch. Here, when the mobility of the two-dimensional electron gas is calculated based on the precondition N _s = 8 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² , the mobility μ = about 1500 cm ² / Vs. . When the sheet resistance at the AlGaN / GaN interface is determined from these, the sheet resistance Rs = 400Ω to 500Ω / sq.

On the other hand, for the gate portion, as shown in FIG. 22B, consider a case where the gate insulating film has a single layer structure of SiO ₂ (film thickness = 40 nm) and a gate voltage of 5 V is applied. The sheet carrier density N _s of the two-dimensional electron gas generated when this gate voltage is applied is about 6 × 10 ¹² cm ^−2, and the mobility μ and the sheet resistance Rs required from this are μ = 100 to ²⁰⁰ cm ² , respectively. / Vs and Rs = 5000Ω-10000Ω / sq.

Here, in a device having a gate-drain breakdown voltage of 200 V, a distance of at least about 6 μm is required between the gate and the drain. In this case, the sheet resistance Rs of the gate portion as described above the gate - Considering that approximately 10 times the sheet resistance Rs of the drain, the gate length L _g is the gate - drain distance of (6 [mu] m) to about Unless 1/10, the resistance cannot be equalized, and most of the on-resistance becomes the resistance of the gate portion. Accordingly, the gate length _{L g,} it is preferable that in the 0.6μm or less.

_{23, N A + N DA -N D} -N DD is, the lower limit of the preferred carbon concentration in the range ^{(1 × 10 18 cm -3 ~1} × 10 19 cm -3) of Figure 18 (about 4 × ^{10 16} The relationship between the gate length _Lg and the gate breakdown voltage when cm ⁻³ ) is shown.
As shown in FIG. 23, when the gate length _{L g} is 0.6 .mu.m, the gate breakdown voltage of about 15V. That is, when a voltage of 15 V is applied to the gate, a leak current due to punch-through occurs under the gate as shown in FIG. Therefore, in order not to generate such a leakage current, it is necessary to deplete the field plate portion 192 below with a voltage lower than the voltage value of the gate breakdown voltage.

Figure 24 _is a diagram showing the relationship between _{N A + N DA -N D -N} DD and depletion voltage under the field plate. FIG. 24 shows the relationship when the thickness of the gate insulating film (SiN) is the thickness d = 100 nm, d = 200 nm, and d = 300 nm.
As shown in FIG. 24, the depletion voltage when N _A + N _DA −N _D −N _DD = 4 × 10 ¹⁶ cm ⁻³ is 14 V when d = 100 nm and 26 V when d = 200 nm, respectively. It was found that the voltage was 34 V when d = 300 nm, and the depletion voltage <the gate breakdown voltage (15 V) was satisfied only when d = 100 nm. In other words, when the relative permittivity ε of SiN is 7, when d / ε is 14 or less, before the punch-through occurs under the gate, the field plate portion 192 is depleted to suppress the leakage current. Can do.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, the field plate portion 192 does not need to be formed integrally with the gate main body portion 191, and may be formed as a field plate separated from the gate main body portion 191. In this case, the field plate may be electrically connected to the source electrode 17.

In the nitride semiconductor device 3, the breakdown voltage can be improved even if the following formula (9) or (11), more preferably the following formula (10) or (12) is satisfied.
^{_{N s 2 / (N A +}} N DA -N D -N DD) <(N A + N DA -N D -N DD) · (L g + L fp) 2 ··· (9)
^{_{N s 2 / (N A +}} N DA) <(N A + N DA) · (L g + L fp) 2 ··· (11)
_{(N A + N DA -N D} -N DD) · (L g + L fp) 2 <1.2N s 2 / (N A + N DA -N D -N DD) ··· (10)
_{(N A + N DA) ·} (L g + L fp) 2 <1.2N s 2 / (N A + N DA) ··· (12)
Left side of the _N ^s 2 _/ of formula _{(9) (N A + N} DA -N D -N DD) , in FIG. 2, two-dimensional electrons from the edge of the drain electrode 18 side of the field plate portion 192 to the drain electrode 18 A voltage V ₃ (described in FIG. 8) at which the gas is depleted is shown. On the other hand, the right-hand side of _{(N A + N DA -N D} -N DD) · (L g + L fp) 2 of formula (9) shows the breakdown voltage can be held in the gate electrode 19 (gate body portion 191Tasu field plate portion 192) ing.

  Until the two-dimensional electron gas from the end on the drain electrode 18 side of the field plate portion 192 to the drain electrode 18 is depleted, a voltage drop occurs in the gate main body portion 191 and the field plate portion 192, but the field plate portion 192 is concerned. When the space from the end of the gate electrode to the drain electrode 18 is depleted, a voltage drop occurs from the gate body 191 to the drain electrode 18. That is, the breakdown voltage is held in the section A of FIG. 2 at the low drain voltage, but the breakdown voltage is held in the section B at the high drain voltage. Therefore, the expressions (9) and (11) indicate that at least the gate electrode 19 (gate body portion 191+) until the two-dimensional electron gas from the end of the field plate portion 192 on the drain electrode 18 side to the drain electrode 18 is depleted. This means that the field plate portion 192) holds the breakdown voltage.

  In the above-described embodiment, the example in which the electron transit layer 14 is made of a GaN layer and the electron supply layer 15 is made of AlGaN has been described. However, the electron transit layer 14 and the electron supply layer 15 have different Al compositions. Well, other combinations are possible. The combination of the electron supply layer / electron transit layer includes AlGaN layer / GaN layer, AlGaN layer / AlGaN layer (although different Al compositions), AlInN layer / AlGaN layer, AlInN layer / GaN layer, AlN layer / GaN layer, AlN Any of layer / AlGaN layer may be used. More generally, the electron supply layer contains Al and N in the composition. The electron transit layer contains Ga and N in the composition, and the Al composition is different from that of the electron supply layer. Due to the difference in Al composition between the electron supply layer and the electron transit layer, lattice mismatch occurs between them, whereby carriers due to polarization contribute to the formation of a two-dimensional electron gas.

In the above-described embodiment, silicon is exemplified as a material example of the substrate 12, but any other substrate material such as a sapphire substrate or a GaN substrate can be applied.
In addition, various design changes can be made within the scope of matters described in the claims.

3 Nitride Semiconductor Device 12 Substrate 13 Buffer Layer 131 First Buffer Layer 132 Second Buffer Layer 14 Electron Traveling Layer 141 First Region 142 Second Region 15 Electron Supply Layer 16 Gate Insulating Film 161 First Insulating Layer 162 Second Insulating Layer 17 Source electrode 18 Drain electrode 19 Gate electrode 191 Gate body portion 191a Gate electrode drain end 191b Gate electrode source end 192 Field plate portion 20 Two-dimensional electron gas L _g gate length L _fp field plate length L _gd gate-drain distance

Claims (18)

A nitride semiconductor layer having a gate, a source and a drain;
A field plate on the nitride semiconductor layer electrically connected to the gate or the source;
The drain voltage value that decreases to 1/2 of the value when the C _oss value is 0 V is V ₁ (V), the device breakdown voltage is V ₂ (V), and the gate length is L _g (cm). The field plate length is L _fp (cm), the shallow acceptor concentration is N _A (/ cm ³ ), the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum dielectric constant is ε ₀ , and the relative dielectric constant of the nitride semiconductor layer A nitride semiconductor device that satisfies the following formulas (1) and (2) when the rate is ε.
V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
_{V 2 <q (N A +} N DA) · (L g + L fp) 2 / 2ε 0 ε ··· (2) The nitride semiconductor device of Claim 1 which satisfy | fills following formula (3) and (4).
_{q (N A + N DA)} · L g 2 / 2ε 0 ε <1.2V 1 ··· (3)
_{q (N A + N DA)} · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (4) A nitride semiconductor layer having a gate, a source and a drain;
A field plate on the nitride semiconductor layer electrically connected to the gate or the source;
The drain voltage value that decreases to 1/2 of the value when the C _oss value is 0 V is V ₁ (V), the device breakdown voltage is V ₂ (V), and the gate length is L _g (cm). , Field plate length is L _fp (cm), shallow donor concentration is N _D (/ cm ³ ), deep donor concentration is N _DD (/ cm ³ ) _, shallow acceptor concentration is N _A (/ cm ³ ), and deep acceptor concentration. Is a _NDA (/ cm ³ ), a vacuum dielectric constant is ε ₀ , and a relative dielectric constant of the nitride semiconductor layer is ε, a nitride semiconductor device that satisfies the following formulas (5) and (6).
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6) The nitride semiconductor device of Claim 3 which satisfy | fills following formula (7) and (8).
_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8) A nitride semiconductor layer having a gate, a source and a drain;
A field plate on the nitride semiconductor layer electrically connected to the gate or the source;
The drain voltage value that decreases to 1/2 of the value when the C _oss value is 0 V is V ₁ (V), the maximum rated voltage of the device is V ₂ (V), and the gate length is L _g (cm). The field plate length is L _fp (cm), the shallow acceptor concentration is N _A (/ cm ³ ), the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum dielectric constant is ε ₀ , and the relative dielectric constant of the nitride semiconductor layer A nitride semiconductor device that satisfies the following formulas (1) and (2) when the rate is ε.
V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
_{V 2 <q (N A +} N DA) · (L g + L fp) 2 / 2ε 0 ε ··· (2) The nitride semiconductor device according to claim 5, which satisfies the following formulas (3) and (4).
_{q (N A + N DA)} · L g 2 / 2ε 0 ε <1.2V 1 ··· (3)
_{q (N A + N DA)} · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (4) A nitride semiconductor layer having a gate, a source and a drain;
A field plate on the nitride semiconductor layer electrically connected to the gate or the source;
The drain voltage value that decreases to 1/2 of the value when the C _oss value is 0 V is V ₁ (V), the maximum rated voltage of the device is V ₂ (V), and the gate length is L _g (cm). , Field plate length is L _fp (cm), shallow donor concentration is N _D (/ cm ³ ), deep donor concentration is N _DD (/ cm ³ ) _, shallow acceptor concentration is N _A (/ cm ³ ), and deep acceptor concentration. Is a _NDA (/ cm ³ ), a vacuum dielectric constant is ε ₀ , and a relative dielectric constant of the nitride semiconductor layer is ε, a nitride semiconductor device that satisfies the following formulas (5) and (6).
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6) The nitride semiconductor device of Claim 7 which satisfy | fills following formula (7) and (8).
_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8) A nitride semiconductor layer having a gate, a source and a drain;
A field plate on the nitride semiconductor layer electrically connected to the gate or the source;
The drain voltage value that decreases to 1/2 of the value when the C _oss value is 0 V is V ₁ (V), the sheet carrier density of the two-dimensional electron gas is N _s (/ cm ² ), and the gate length is L _g (cm), field plate length is L _fp (cm), shallow donor concentration is N _D (/ cm ³ ), deep donor concentration is N _DD (/ cm ³ ) _{, and} shallow acceptor concentration is N _A (/ cm ^3). ), A nitride that satisfies the following formulas (5) and (9), where N _DA (/ cm ³ ) is the deep acceptor concentration, ε _{0 is the} vacuum dielectric constant, and ε is the relative dielectric constant of the nitride semiconductor layer. Semiconductor device.
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
^{_{N s 2 / (N A +}} N DA -N D -N DD) <(N A + N DA -N D -N DD) · (L g + L fp) 2 ··· (9) The nitride semiconductor device of Claim 9 which satisfy | fills following formula (7) and (10).
_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{(N A + N DA -N D} -N DD) · (L g + L fp) 2 <1.2N s 2 / (N A + N DA -N D -N DD) ··· (10) A nitride semiconductor layer having a gate, a source and a drain;
A field plate on the nitride semiconductor layer electrically connected to the gate or the source;
The drain voltage value that decreases to 1/2 of the value when the C _oss value is 0 V is V ₁ (V), the sheet carrier density of the two-dimensional electron gas is N _s (/ cm ² ), and the gate length is L _g (cm), field plate length L _fp (cm), shallow acceptor concentration N _A (/ cm ³ ), deep acceptor concentration N _DA (/ cm ³ ), vacuum dielectric constant ε ₀ , nitride A nitride semiconductor device that satisfies the following formulas (1) and (11) when the relative dielectric constant of the semiconductor layer is ε.
V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
^{_{N s 2 / (N A +}} N DA) <(N A + N DA) · (L g + L fp) 2 ··· (11) The nitride semiconductor device according to claim 11, wherein the following formulas (3) and (12) are satisfied.
_{q (N A + N DA)} · L g 2 / 2ε 0 ε <1.2V 1 ··· (3)
_{(N A + N DA) ·} (L g + L fp) 2 <1.2N s 2 / (N A + N DA) ··· (12) The gate length _{L g} is at 0.5μm or less, said field plate length _{L fp} is not less 0.5μm or less, the maximum rated voltage of the device is the higher than 50V, according to any one of claims 1 to 12 Nitride semiconductor devices.   The nitride semiconductor layer is made of C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, Mg, Ar, and He. The nitride semiconductor device according to claim 1, wherein a deep acceptor level is formed by doping at least one impurity selected from the group consisting of: A nitride semiconductor layer including an electron transit layer and an electron supply layer in contact with the electron transit layer and having a composition different from that of the electron transit layer;
A gate, a source and a drain on the nitride semiconductor layer;
A field plate on the nitride semiconductor layer electrically connected to the gate or the source;
A nitride semiconductor device, wherein carbon is contained in at least a part of the electron transit layer, and the concentration of the carbon is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . The electron transit layer includes a first region that forms an interface between the electron transit layer and the electron supply layer, and a second region that is formed in a portion separated by 50 nm or more from the interface,
The carbon concentration of the second region is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ , and the carbon concentration of the first region is 1 × 10 ¹⁷ cm ⁻³ or less. Nitride semiconductor devices. When the shallow donor concentration is N _D (/ cm ³ ), the deep donor concentration is N _DD (/ cm ³ ) _{, the} shallow acceptor concentration is N _A (/ cm ³ ), and the deep acceptor concentration is N _DA (/ cm ³ ). ,
_{N A + N DA -N D -N} DD of the second region of the electron transit layer is ^{4 × 10 16 cm -3 ~8 ×} 10 16 cm -3, the nitride semiconductor device according to claim 16 . A nitride semiconductor layer including an electron transit layer and an electron supply layer in contact with the electron transit layer and having a composition different from that of the electron transit layer;
A gate, a source and a drain on the nitride semiconductor layer;
A field plate electrically connected to the gate or the source and disposed on the nitride semiconductor layer through an insulating film;
The gate length _{L g} is at 0.6μm or less,
Carbon is contained in at least a part of the electron transit layer, and the concentration of the carbon is 1 × 10 ¹⁸ cm ⁻³ or more,
A nitride semiconductor device that satisfies d / ε ≦ 14, where d (nm) is the thickness of the insulating film under the field plate and ε is the relative dielectric constant of the insulating film.

Images