CN101106158A - Germanium silicon heterogeneous crystal transistor with elevated external base area and its making technology - Google Patents
Germanium silicon heterogeneous crystal transistor with elevated external base area and its making technology Download PDFInfo
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- CN101106158A CN101106158A CNA2007101181964A CN200710118196A CN101106158A CN 101106158 A CN101106158 A CN 101106158A CN A2007101181964 A CNA2007101181964 A CN A2007101181964A CN 200710118196 A CN200710118196 A CN 200710118196A CN 101106158 A CN101106158 A CN 101106158A
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Abstract
The invention discloses a Ge-Si heterojunction transistor with an elevated external base and the preparation technique thereof, pertaining to the field of semiconductor devices and the preparation technology thereof. The heterojunction transistor comprises a collector formed with silicon substrate, a SiGe layer base and an external base, and a polysilicon emitter. A sidewall structure layer is equipped between the emitter and the base electrode, the external base is elevated, and the sidewall structure layer thereof prevents the emitter and the base electrode leaking. By using the technique of elevating the external base and the epitaxial growth technology of the external base, the invention overcomes the drawbacks that the prior injection technique of the external base in the Ge-Si heterojunction transistor technology leads to the serious Boron enhanced diffusion of the intrinsic base under the window of the emitting region, and thereby the invention makes the base wider and the doping changed, and reduces the fT and fmax parameters of devices. Therefore, the direct current and high frequency characteristics of devices are improved greatly.
Description
Technical field
The invention belongs to semiconductor device and preparing technical field thereof, particularly a kind of germanium silicon heterogeneous crystal transistor with elevated external base area and preparation technology thereof.
Background technology
The SiGe heterojunction transistor is applied to the microwave circuit field gradually because of its excellent high frequency performance and lower cost advantage.The SiGe heterojunction transistor has reduced the band gap width of base because of introduce the epitaxial Germanium silicon alloy in the base, thereby makes the direct current of device and high frequency characteristics that very big lifting be arranged.
In original Ge-Si heterojunction transistor technology, outer base area adopts injection technology, injects the defective that produces and can cause the boron enhancing diffusion of the intrinsic base region under the emitter window serious, thereby cause that the base broadens, and mixing changes, and the f of reduction device
TAnd f
MaxEtc. parameter.If address this problem fully, just need to change outer base area and form technology.Of the present inventionly raise outer base area technology is avoided intrinsic base region boron fully with extensional mode growth outer base area enhancing diffusion effect.
Summary of the invention
The purpose of this invention is to provide a kind of germanium silicon heterogeneous crystal transistor with elevated external base area and preparation technology, it is characterized in that described germanium silicon heterogeneous crystal transistor with elevated external base area comprises the collector electrode that Si substrate 12 forms, base SiGe layer 14, outer base area conductive layer 22, and the polysilicon layer 34 of making emitter.This transistorized structure is an epitaxial growth SiGe layer 14 on substrate 12, deposition outer base area conductive layer 22 on SiGe layer 14, what be right after dielectric layer 28 for dielectric layer 28 on one side by polysilicon layer 34 on outer base area conductive layer 22 is silicide structural layer 42, is provided with the wedge shape sidewall structure of film dielectric layer 16, dielectric layer 32 formations between the perpendicular arm of polysilicon layer 34 and outer base area conductive layer 22 and dielectric layer 28; Guarantee the isolation between polysilicon layer 34 and the outer base area conductive layer 22.In the horizontal arm side of polysilicon layer 34 similar right-angled triangle sidewall structure 40 is set; horizontal arm upper surface depositing silicide layer 42 at polysilicon layer 34; at integrally-built upper surface covering protection dielectric layer 43, face toward the silicide layer 42 porose 44 on outer base area conductive layer 22 and polysilicon layer 34 surfaces on the protective dielectric layer 43 at last.
Described substrate is silicon or silicon nitride.
Described dielectric layer is silicon, silica or silicon nitride.
Described silicide is Titanium silicide, cobalt silicide or nickel silicide.
The step of preparation process of described germanium silicon heterogeneous crystal transistor with elevated external base area is as follows:
1) epitaxial growth SiGe layer 14 on the substrate 12 of Si, growing silicon oxide dielectric layer 16 and silicon nitride medium layer 18 then, setting the two layer medium gross thickness is t, exposure forms column litho pattern 20 then;
2) on the litho pattern basis of step 1, form and the identical shaped silica medium layer 16 of column litho pattern 20 and the dual dielectric layer of silicon nitride medium layer 18 through etching, selective epitaxial growth Si or SiGe layer 22 then, its thickness should≤t/2; Deposit one deck dielectric layer 24 then, thickness of dielectric layers is wanted 〉=t/2, and Si or SiGe layer 22 are used to form the outer base area structure, and its doping can be adopted in-situ doped or the ion implantation doping mode;
3) deposit or coating one deck dielectric layer 26 on dielectric layer 24, make the upper surface of dielectric layer 26 smooth, and adjustment dry etch process, make the etch rate of dielectric layer 24 and dielectric layer 26 be about 1: 1, the selective etching time, form the dielectric layer 28 that flushes with dual dielectric layer after the etching on Si or SiGe layer 22, its effect is to prevent that emitter from contacting with base stage;
4) adopt dry method or wet processing, selective etch is removed dielectric layer 18;
5) on the structure of step 4, evenly cover one deck dielectric layer 31;
6) adopt anisotropic etching dielectric layer 31, form sidewall structure 32;
7) adopt dry method or wet-etching technology that the silica medium layer 16 of opening portion is etched away then, need to keep side direction corroding loss minimum in the etching process, finally form emitter-window 30, adopt this kind sidewall structure, can dwindle the photoetching lines;
8) growth one deck polysilicon adopts dry method or wet etching to form emitter structure 34 after photoetching, and forms polysilicon doping with the method for in-situ doped or ion implantation doping;
9) deposit afterwards covers layer of even dielectric layer 36, adopts anisotropic etching dielectric layer 36, forms sidewall structure 40 in emitter structure 34 outsides, emitter and base stage short circuit in the process that silicide generated after the effect of sidewall structure 40 was to prevent; Afterwards with side wall 40 as masking layer, the part dielectric layer 28 beyond the side wall 40 is etched away;
10) on base silica medium layer 16 and the emitter structure 34 depositing silicide structures 42 of emitter region, the effect of silicide is to reduce the electrode contact resistance;
11) at last at the structure upper surface covering protection dielectric layer 43 of step 10, face toward the silicide layer 42 porose 44 on outer base area conductive layer 22 and polysilicon layer 34 surfaces on the protective dielectric layer 43.
Described silicide is Titanium silicide, cobalt silicide or nickel silicide.
Described dielectric layer is silica or silicon nitride.
The invention has the beneficial effects as follows and adopt the technology of outer base area technology of raising, preparation germanium silicon heterogeneous crystal transistor with elevated external base area with extensional mode growth outer base area.Overcoming boron that outer base area injection technology in original Ge-Si heterojunction transistor technology causes the intrinsic base region under the emitter window, to strengthen diffusion serious, thereby cause that the base broadens, and mixing changes, and reduces the f of device
TAnd f
MaxIsoparametric deficiency makes the direct current of device and high frequency characteristics that very big lifting be arranged.
Description of drawings
Fig. 1～Figure 14 is preparation technology's flow chart of germanium silicon heterogeneous crystal transistor with elevated external base area.
Embodiment
The invention provides a kind of germanium silicon heterogeneous crystal transistor with elevated external base area and preparation technology.In the structural representation of germanium silicon heterogeneous crystal transistor with elevated external base area shown in Figure 14, transistorized structure comprises the collector electrode that Si substrate 12 forms, base SiGe layer 14, outer base area conductive layer 22, and the polysilicon layer 34 of making emitter.This transistorized structure is an epitaxial growth SiGe layer 14 on substrate 12, deposition outer base area conductive layer 22 on SiGe layer 14, what be right after dielectric layer 28 for dielectric layer 28 on one side by polysilicon layer 34 on outer base area conductive layer 22 is silicide structural layer 42, is provided with the wedge shape sidewall structure of film dielectric layer 16, dielectric layer 32 formations between the perpendicular arm of polysilicon layer 34 and outer base area conductive layer 22 and dielectric layer 28; Guarantee the isolation between polysilicon layer 34 and the outer base area conductive layer 22.In the horizontal arm side of polysilicon layer 34 similar right-angled triangle sidewall structure 40 is set; horizontal arm upper surface depositing silicide layer 42 at polysilicon layer 34; at integrally-built upper surface covering protection dielectric layer 43, face toward the silicide layer 42 porose 44 on outer base area conductive layer 22 and polysilicon layer 34 surfaces on the protective dielectric layer 43 at last.
Step of preparation process figure below in conjunction with the germanium silicon heterogeneous crystal transistor with elevated external base area of Fig. 1～shown in Figure 14 specifies as follows:
1) epitaxial growth SiGe layer 14 on the substrate 12 of Si, growing silicon oxide dielectric layer 16 and silicon nitride medium layer 18 then, setting the two layer medium gross thickness is t, exposure forms 20 (as shown in Figure 1) of column litho pattern then.
2) on litho pattern basis shown in Figure 1, form silica medium layer 16 and the dual dielectric layer (as shown in Figure 2) of silicon nitride medium layer 18, then selective epitaxial growth Si or the SiGe layer 22 identical shaped through etching again with column litho pattern 20.Its thickness is answered≤t/2.Deposit one deck dielectric layer 24 then, thickness of dielectric layers is wanted 〉=t/2.Si or SiGe layer 22 are used to form the outer base area structure, and its doping can be adopted in-situ doped or inject doping way (as shown in Figure 3).
3) deposit or 26 (as shown in Figure 4) of coating one deck dielectric layer on dielectric layer 24, make the upper surface of dielectric layer 26 smooth, and adjustment dry etch process, make the etch rate of dielectric layer 24 and dielectric layer 26 be about 1: 1, the selective etching time, the dielectric layer that flushes with dual dielectric layer 28 (as shown in Figure 5) that on Si or SiGe layer 22, forms after the etching.Its effect is to prevent that emitter from contacting with base stage.Or adopt CMP technology directly to form Fig. 5 structure from Fig. 3 or Fig. 4.
4) adopt dry method or wet processing, selective etch is removed dielectric layer 18 (as shown in Figure 6),
5) on the structure of step 4, evenly cover 31 (as shown in Figure 7) of one deck dielectric layer.
6) adopt anisotropic etching dielectric layer 31, form sidewall structure 32 (as shown in Figure 8).
7) adopt dry method or wet-etching technology that the silica medium layer 16 of opening portion is etched away then, need to keep side direction corroding loss minimum in the etching process, the final emitter-window 30 (as shown in Figure 9) that forms adopts this kind sidewall structure, can dwindle the photoetching lines.
8) growth one deck polysilicon adopts dry method or wet etching to form emitter structure 34 after photoetching, and forms polysilicon doping with the method for in-situ doped or ion implantation doping;
9) deposit afterwards covers layer of even dielectric layer 36 (shown in Figure 10,11), adopt anisotropic etching dielectric layer 36, form sidewall structure 40 in emitter structure 34 outsides, emitter and base stage short circuit in the process that silicide generated after the effect of sidewall structure 40 was to prevent.Afterwards with side wall 40 as masking layer, the part dielectric layer 28 beyond the side wall 40 is etched away (as shown in figure 12).
10) on base silica medium layer 16 and the emitter structure 34 depositing silicide structures 42 of emitter region, the effect of silicide is to reduce electrode contact resistance (as shown in figure 13).
11) at last at the structure upper surface covering protection dielectric layer 43 of step 10, face toward 42 porose 44 (as shown in figure 14) of silicide layer on outer base area conductive layer 22 and polysilicon layer 34 surfaces on the protective dielectric layer 43.
Described silicide is Titanium silicide, cobalt silicide or nickel silicide.
Described dielectric layer is silica or silicon nitride.
Described in-situ doped finger directly mixes to polycrystalline or monocrystalline by introducing dopant gas source in polycrystalline or crystal formation process.
Described ion implantation doping is after polycrystalline or crystal growth form, and it is carried out the ion injection after the doping process that annealing activates.
Described selective etch is meant that etching phase etch rate to other materials for a kind of material is lower.
Described anisotropic etching is meant that the side direction etch amount in the etching is less than vertical etch amount.
Claims (5)
1. germanium silicon heterogeneous crystal transistor with elevated external base area, it is characterized in that, described germanium silicon heterogeneous crystal transistor with elevated external base area comprises the collector electrode that Si substrate (12) forms, base SiGe layer (14), outer base area conductive layer (22), and the polysilicon layer (34) of making emitter, this transistorized structure is to go up epitaxial growth SiGe layer (14) at substrate (12), deposition outer base area conductive layer (22) on SiGe layer (14), going up what be right after dielectric layer (28) for dielectric layer (28) on one side by polysilicon layer (34) at outer base area conductive layer (22) is silicide structural layer (42), is provided with film dielectric layer (16) between the perpendicular arm of polysilicon layer (34) and outer base area conductive layer (22) and dielectric layer (28), the wedge shape sidewall structure that dielectric layer (32) constitutes; Guarantee the isolation between polysilicon layer (34) and the outer base area conductive layer (22); in the horizontal arm side of polysilicon layer (34) similar right-angled triangle sidewall structure (40) is set; horizontal arm upper surface depositing silicide layer (42) at polysilicon layer (34); at integrally-built upper surface covering protection dielectric layer (43), protective dielectric layer (43) is gone up the silicide layer (42) porose (44) facing to outer base area conductive layer (22) and polysilicon layer (34) surface at last.
2. according to the described germanium silicon heterogeneous crystal transistor with elevated external base area of claim 1, it is characterized in that described substrate is silicon or silicon nitride.
3. according to the described germanium silicon heterogeneous crystal transistor with elevated external base area of claim 1, it is characterized in that described dielectric layer is silicon, silica or silicon nitride.
4. according to the described germanium silicon heterogeneous crystal transistor with elevated external base area of claim 1, it is characterized in that described silicide is Titanium silicide, cobalt silicide or nickel silicide.
5. the preparation technology of a germanium silicon heterogeneous crystal transistor with elevated external base area is characterized in that, the step of preparation process of described germanium silicon heterogeneous crystal transistor with elevated external base area is as follows:
1) go up epitaxial growth SiGe layer (14) at the substrate (12) of Si, growing silicon oxide dielectric layer (16) and silicon nitride medium layer (18) then, setting the two layer medium gross thickness is t, exposure forms column litho pattern (20) then;
2) on the litho pattern basis of step 1, through etching form the silica medium layer identical shaped with column litho pattern (20) (16 and the silicon nitride medium layer (18 dual dielectric layer, selective epitaxial growth Si or SiGe layer (22) then, its thickness should≤t/2; Deposit one deck dielectric layer (24) then, thickness of dielectric layers is wanted 〉=t/2, and Si or SiGe layer (22) are used to form the outer base area structure, and its doping can be adopted in-situ doped or the ion implantation doping mode;
3) go up deposit or coating one deck dielectric layer (26) at dielectric layer (24), make the upper surface of dielectric layer (26) smooth, and adjustment dry etch process, make the etch rate of dielectric layer (24) and dielectric layer (26) be about 1: 1, the selective etching time, go up the dielectric layer (28) that formation flushes with dual dielectric layer at Si or SiGe layer (22) after the etching, its effect is to prevent that emitter from contacting with base stage;
4) be used in method or wet processing, selective etch is removed dielectric layer (18);
5) on the structure of step 4, evenly cover one deck dielectric layer (31);
6) adopt anisotropic etching dielectric layer (31), form sidewall structure (32);
7) adopt dry method or wet-etching technology that the silica medium layer (16) of opening portion is etched away then, need to keep side direction corroding loss minimum in the etching process, finally form emitter-window (30), adopt this kind sidewall structure, can dwindle the photoetching lines;
8) growth one deck polysilicon adopts dry method or wet etching to form emitter structure (34) after photoetching, and forms polysilicon doping with the method for in-situ doped or ion implantation doping;
9) deposit afterwards covers layer of even dielectric layer (36), adopt anisotropic etching dielectric layer (36), form sidewall structure (40) in emitter structure (34) outside, emitter and base stage short circuit in the process that silicide generated after the effect of sidewall structure (40) was to prevent; Afterwards with side wall (40) as masking layer, side wall (40) part dielectric layer (28) is in addition etched away;
10) go up and emitter structure (34) the depositing silicide structure (42) of emitter region at base silica medium layer (16), the effect of silicide is a reduction electrode contact resistance;
11) at last at the structure upper surface covering protection dielectric layer (43) of step 10, protective dielectric layer (43) is gone up the silicide layer (42) porose (44) facing to outer base area conductive layer (22) and polysilicon layer (34) surface.
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| CN102034706B (en) * | 2009-09-29 | 2012-03-21 | 上海华虹Nec电子有限公司 | Method for controlling growth effect of facet of silicon-germanium (Si-Ge) alloy |
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| CN102664190A (en) * | 2012-05-16 | 2012-09-12 | 清华大学 | Embedded epitaxial external base region bipolar transistor and manufacturing method thereof |
| CN102664190B (en) * | 2012-05-16 | 2014-12-17 | 清华大学 | Embedded epitaxial external base region bipolar transistor and manufacturing method thereof |
| CN102651390B (en) * | 2012-05-16 | 2015-09-30 | 清华大学 | Embedded epitaxial external base region bipolar transistor and preparation method thereof |
| CN102651390A (en) * | 2012-05-16 | 2012-08-29 | 清华大学 | Bipolar transistor with embedded epitaxial outer base region and fabrication method of bipolar transistor |
| CN102683395A (en) * | 2012-05-22 | 2012-09-19 | 清华大学 | Self-alignment lifting outer base region germanium silicon heterojunction bipolar transistor and preparation method thereof |
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