CN102157549B - PN junction and manufacture method thereof - Google Patents
PN junction and manufacture method thereof Download PDFInfo
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- CN102157549B CN102157549B CN201110028613.2A CN201110028613A CN102157549B CN 102157549 B CN102157549 B CN 102157549B CN 201110028613 A CN201110028613 A CN 201110028613A CN 102157549 B CN102157549 B CN 102157549B
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Abstract
A kind of PN junction and manufacture method thereof, described PN junction comprises: the first semiconductor layer of the first doping; Be positioned at the dielectric layer on the first semiconductor layer, be provided with opening in described dielectric layer, described opening exposes described first semiconductor layer, and the cross section of described dielectric layer is the wedge shape that openend thickness is less; Be filled in described opening and be covered on described dielectric layer second doping the second semiconductor layer.Correspondingly, the present invention also provides a kind of manufacture method of PN junction.The problem that the present invention can avoid the leakage current that causes because PN junction is more shallow larger.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of PN junction and manufacture method thereof.
Background technology
BiCMOS integrated circuit is the integrated circuit be made up of ambipolar gate circuit and CMOS gate circuit, be characterized in bipolar process and CMOS technology compatibility, with certain circuit form, bipolar circuitry and cmos circuit are integrated on the same chip, have the features such as high density, low-power consumption and the large driving force of high speed concurrently.
Manufacture in process at BiCMOS, usually can form PN junction structure, be disclose a kind of PN junction structure in the Chinese patent application of CN101252151C at notification number.
The schematic diagram of prior art PN junction one embodiment is shown with reference to figure 1.Described PN junction comprises base stage 101, is positioned at dielectric layer base stage 101 being provided with emitter-window, the emitter 104 being filled in emitter-window.The semiconductor layer that described base stage 101 is adulterated for N-type, the semiconductor layer that described emitter 104 adulterates for P type, PN junction 105 is formed between base stage 101 and emitter 104, wherein, described dielectric layer comprises the silica 102 be positioned at successively in base stage 101, silicon nitride layer 103, that is, described emitter-window is surrounded by silica 102 and silicon nitride layer 103.
In prior art, the manufacture method of PN junction shown in Fig. 1 comprises the following steps: provide substrate; Substrate forms base stage, silica, silicon nitride layer successively; Etch described silicon nitride layer, silica forms the emitter-window exposing described base stage; By described emitter-window, N-type doping is carried out to base stage; Fill emitter material to emitter-window, form emitter; The doping of P type is carried out to described emitter.When base stage being adulterated by described emitter-window, the base stage that emitter-window is exposed forms darker doped region, and there is certain thickness due to described silica and silicon nitride layer, the doped region formed below silica and silicon nitride layer is more shallow, thus causes the formation (as shown in phantom in Figure 1) of the PN junction of connector shape.
The doped region be positioned in PN junction due to connector shape below silica and silicon nitride layer is more shallow, when loading bias voltage to PN junction, at depletion layer near emitter, easily produces leakage current.
Summary of the invention
The problem that the present invention solves is to provide a kind of PN junction and manufacture method thereof, avoids the generation of leakage current.For solving the problem, the invention provides a kind of PN junction, comprising: the first semiconductor layer of the first doping; Be positioned at the dielectric layer on the first semiconductor layer, be provided with opening in described dielectric layer, described opening exposes described first semiconductor layer, and the cross section of described dielectric layer is the wedge shape that openend thickness is less; Be filled in described opening and be covered on described dielectric layer second doping the second semiconductor layer.
Described dielectric layer is silica.
Described first is doped to N-type doping, and described second is doped to the doping of P type.
Described first semiconductor layer is base stage, and described second semiconductor layer is emitter.
The material of described base stage adopts the silicon mixing germanium, and the material of described emitter is silicon.
Described silica at openend thickness 200 ~
scope in.
Correspondingly, the present invention also provides a kind of manufacture method of PN junction, comprising: provide substrate, forms the first semiconductor layer over the substrate, and described first semiconductor layer is the semiconductor layer of the first doping; Described first semiconductor layer forms dielectric layer, and graphical described dielectric layer, forms opening in described dielectric layer, thinning described dielectric layer in the process forming opening, forms the wedge-shaped medium layer that openend thickness is less; Filling semiconductor material in described opening, forms the second semiconductor layer be covered on dielectric layer; Second doping is carried out to described second semiconductor layer.
Described dielectric layer is silica, and the step of described graphical described dielectric layer comprises by the graphical described silica of wet etching, and the solution used in described wet etching is hydrofluoric acid.
Described first semiconductor layer is formed in the step of dielectric layer, the thickness of described dielectric layer 800 ~
scope in.
Described graphical described dielectric layer, form the step of opening in described dielectric layer after, the thickness of the dielectric layer of described openend 200 ~
scope in.
Described the step that described second semiconductor layer carries out the second doping to be comprised, by ion implantation mode, the second doping is carried out to the second semiconductor layer.
Compared with prior art, the present invention has the following advantages:
1. PN junction described in can avoid the formation of the doped region of connector shape, while other electrical parameters of maintenance are constant, can avoid the problem that the leakage current that causes because PN junction is more shallow is larger;
2., in PN junction manufacture method provided by the invention, without the need to deposited silicon nitride on silica, simplify manufacturing process.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of prior art PN junction one embodiment;
Fig. 2 is the schematic diagram of PN junction one embodiment of the present invention;
Fig. 3 is the schematic flow sheet of PN junction manufacture method one execution mode of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
For the problem described in background technology, the invention provides a kind of PN junction, with reference to figure 2, show the schematic diagram of PN junction one embodiment of the present invention.The present embodiment, for the SiGe PN junction bipolar transistor of positive-negative-positive, as shown in Figure 2, comprising: substrate; Be positioned at the collector 206 on substrate, base stage 201, dielectric layer 202, emitter 204 successively, wherein,
The semiconductor layer that collector 206 is adulterated for P type, particularly, described collector 206 can be boron doped silicon;
The semiconductor layer that base stage 201 is adulterated for N-type, particularly, the material of described base stage 201 is the silicon mixing germanium, and described N-type doping can be arsenic doping or phosphorus doping;
Described dielectric layer 202 is single-layer medium layer, the opening as emitter-window is provided with in described dielectric layer 202, the wedge-shaped in cross-section of described dielectric layer, wherein, thickness of dielectric layers near emitter-window is thinner, particularly, the material of described dielectric layer 202 is silica, described silica at the thickness of openend 200 ~
scope in;
Described emitter 204 is for being filled in opening and being covered in the semiconductor layer on described dielectric layer 202, and described emitter 204 is the doping of P type;
PN junction 205 is formed between described base stage 201 and emitter 204, described PN junction 205 is formed at base stage 201 surface that emitter-window is exposed, also be formed at base stage 201 surface below the dielectric layer 202 at emitter-window place, the PN junction 205 being formed at zones of different has identical thickness, and the junction depth of described PN junction 205 is comparatively dark, there will not be doped region more shallow and problem that leakage current that is that cause is larger.
Correspondingly, the present invention also provides a kind of manufacture method of PN junction, and show the schematic flow sheet of PN junction manufacture method one execution mode of the present invention with reference to figure 3, described manufacture method comprises the following steps:
S1, provides substrate;
S2, forms the first semiconductor layer over the substrate, and described first semiconductor layer is the semiconductor layer of the first doping;
S3, described first semiconductor layer forms dielectric layer, and graphical described dielectric layer, forms opening in described dielectric layer, and in the process forming opening, thinning described dielectric layer, forms the wedge-shaped medium layer that openend thickness is less;
S4, filling semiconductor material in described opening, forms the second semiconductor layer be covered on dielectric layer;
S5, carries out the second doping to described second semiconductor layer.
Be described in detail above steps below in conjunction with specific embodiment, the present embodiment is for the SiGe PN junction bipolar transistor of positive-negative-positive.
For step S1, described substrate is silicon or silicon-on-insulator (Silicon-On-Insulator, SOI) particularly.
For step S2, by epitaxy technique depositing silicon and germanium over the substrate, form the silicon mixing germanium, as base stage, particularly, described epitaxy technique is molecular number extension (MolecularBeamEpitaxy, or metallorganic chemical vapor deposition (Metal-organicChemicalVaporDeposition MBE), MOCVD), when deposited on substrates Si and Ge, the ratio of the Ge mixed in the Si of deposition can be regulated by the size of the molecular beam regulating Si and Ge.
Described base stage is the semiconductor layer of N-type doping, particularly, can carry out N-type doping by phosphonium ion, to form the semiconductor layer of N-type doping.
For step S3, in the present embodiment, described dielectric layer is silica, and (method of ChemicalVaporDeposition, CVD deposits certain thickness silicon oxide layer in base stage can to pass through chemical vapor deposition;
If wedge shape silica is too thin at the thickness of openend, then formed in the process of opening wayward at subsequent etch process, if the too thick increase causing manufacturing cost, therefore, preferably, in the present embodiment, the thickness of described silica 800 ~
scope in;
Silica covers photoetching offset plate figure, the silica that etching photoresist exposes, with graphical described silica.
Particularly, can pass through the graphical described silica of wet etching, silica forms opening, until described opening dew base stage, the solution that described wet etching uses is the lower hydrofluoric acid of concentration;
Be noted that, due in described wet etching process, chemical solution can isotropically corrode described silica, the etching extent of described wet etching step to the silica near opening (chemical solution region) is larger, less to the etching extent of the silica away from opening, thus formed on silica in the process of opening, described silica is etched into the silica figure that cross section is wedge shape, further, described wedge shape silica is less at the thickness of openend.
Thickness 800 ~
oxide layer in scope after wet etching process, the wedge shape silica formed at the thickness of openend 200 ~
scope in.
S4, fills silicon in described opening, until fill up described opening, form the silicon layer be covered on described silicon oxide dielectric layer, described silicon layer is filled in opening, and the contact-making surface of described silicon layer and base stage is subject to the restriction of opening size.
Step S5, carries out the doping of P type to described silicon layer, and particularly, described P type is doped to boron doping;
Base stage is the semiconductor layer of N-type doping, and collector is the semiconductor layer of P type doping, and at described base stage and collector intersection, the base surface that namely opening exposes forms PN junction, thus completes the manufacture process of PN junction.
In practical application, ion implantation mode can be adopted to carry out the doping of described P type, and when adopting ion implantation mode to adulterate, because the thickness of dielectric layers near open side is less, therefore inject ion and can pass the less dielectric layer of described thickness and arrive base surface.
Need illustrate time, when ion implantation, the injection ion concentration of the base surface that opening exposes is larger, ion diffuse can be carried out to the base stage under dielectric layer covering, inject the ion dielectric layer that have passed through near opening due to part simultaneously and arrive actively surface, so, the base surface exposed at described opening, and opening near the ion concentration differences that formed of base surface below dielectric layer little.It is close that the base surface exposed due to opening, base surface below the dielectric layer of opening part form N-type ion concentration, P type ion in collector spreads in base stage, thus the base surface exposed at opening, base surface below the dielectric layer of opening part all form PN junction, the thickness of the PN junction of described zones of different is substantially identical, and the thickness of described PN junction is comparatively dark, and then avoid the larger problem of the leakage current that causes because doped region is more shallow.
Inventor found through experiments, and other electrical parameters (such as current gain etc.) of PN junction provided by the invention do not change with the change of structure.
It should be noted that, the present invention is for the SiGe PN junction bipolar transistor of positive-negative-positive, but the present invention is not restricted to this, it can also be the transistor etc. of NPN type, all applicable for the semiconductor device the present invention comprising PN junction, those skilled in the art can modify to the present invention according to above-described embodiment, replace or be out of shape.
To sum up, the invention provides a kind of PN junction and manufacture method thereof, the doped region of connector shape can be avoided the formation of, while other electrical parameters of maintenance are constant, the problem that the leakage current that causes because doped region is more shallow is larger can be avoided;
In addition, in PN junction manufacture method provided by the invention, without the need to deposited silicon nitride on silica, save material, decrease processing step, simplify processing procedure.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (4)
1. a manufacture method for PN junction, is characterized in that, comprising: provide substrate, forms the first semiconductor layer over the substrate, and described first semiconductor layer is the semiconductor layer of the first doping; Described first semiconductor layer forms dielectric layer, and graphical described dielectric layer, forms opening in described dielectric layer, thinning described dielectric layer in the process forming opening, forms the wedge-shaped medium layer that openend thickness is less; Filling semiconductor material in described opening, forms the second semiconductor layer be covered on dielectric layer; By ion implantation mode, the second doping is carried out to described second semiconductor layer.
2. the manufacture method of PN junction as claimed in claim 1, it is characterized in that, described dielectric layer is silica, and the step of described graphical described dielectric layer comprises by the graphical described silica of wet etching, and the solution used in described wet etching is hydrofluoric acid.
3., as power requires the manufacture method of the PN junction as described in 1, it is characterized in that, described first semiconductor layer is formed in the step of dielectric layer, and the thickness of described dielectric layer exists
scope in.
4. the manufacture method of PN junction as claimed in claim 3, it is characterized in that, described graphical described dielectric layer, form the step of opening in described dielectric layer after, the thickness of the dielectric layer of described openend exists
scope in.
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| CN201110028613.2A CN102157549B (en) | 2011-01-26 | 2011-01-26 | PN junction and manufacture method thereof |
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| CN201110028613.2A CN102157549B (en) | 2011-01-26 | 2011-01-26 | PN junction and manufacture method thereof |
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| CN102157549B true CN102157549B (en) | 2016-02-03 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5286661A (en) * | 1992-08-26 | 1994-02-15 | Motorola, Inc. | Method of forming a bipolar transistor having an emitter overhang |
| CN101106158A (en) * | 2007-07-02 | 2008-01-16 | 中电华清微电子工程中心有限公司 | Germanium silicon heterogeneous crystal transistor with elevated external base area and its making technology |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52127752A (en) * | 1976-04-19 | 1977-10-26 | Mitsubishi Electric Corp | Pduction of semiconductor unit |
| JP2002343801A (en) * | 2001-05-11 | 2002-11-29 | Sanyo Electric Co Ltd | Very high frequency semiconductor device and manufacturing method therefor |
| US6759731B2 (en) * | 2002-06-05 | 2004-07-06 | United Microelectronics Corp. | Bipolar junction transistor and fabricating method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5286661A (en) * | 1992-08-26 | 1994-02-15 | Motorola, Inc. | Method of forming a bipolar transistor having an emitter overhang |
| CN101106158A (en) * | 2007-07-02 | 2008-01-16 | 中电华清微电子工程中心有限公司 | Germanium silicon heterogeneous crystal transistor with elevated external base area and its making technology |
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