CN103839985A - Lateral parasitic PNP device in germanium-silicon HBT process and manufacturing method thereof - Google Patents

Lateral parasitic PNP device in germanium-silicon HBT process and manufacturing method thereof Download PDF

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CN103839985A
CN103839985A CN201210487432.0A CN201210487432A CN103839985A CN 103839985 A CN103839985 A CN 103839985A CN 201210487432 A CN201210487432 A CN 201210487432A CN 103839985 A CN103839985 A CN 103839985A
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parasitic pnp
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CN103839985B (en
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周正良
陈曦
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors
    • H01L29/0808Emitter regions of bipolar transistors of lateral transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66242Heterojunction transistors [HBT]

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Abstract

The invention discloses a lateral parasitic PNP device in a germanium-silicon HBT process. The lateral parasitic PNP device is provided with a barrier zone formed by an emitter zone window medium and an emitter polysilicon, so as to reduce a base zone diffusion current; an isolation zone is formed by a germanium-silicon window medium and a germanium-silicon polysilicon between the emitter zone and a collector zone; below the isolation zone, an N type epitaxy forms a base zone; and the base zone is provided with a collector sink channel. The top view of the lateral parasitic PNP device in the germanium-silicon HBT process of the invention is a polygon; the center of the emitter forms a polygon ring; the base current is reduced; the germanium-silicon medium layer is used for isolation between the emitter and the collector; the emitter area is improved and the base zone width is reduced; and the DC method multiple of the device is increased. The invention also discloses a manufacturing processing method of the germanium-silicon HBT device.

Description

Horizontal parasitic PNP device and manufacture method in germanium silicium HBT technique
Technical field
The present invention relates to field of semiconductor manufacture, specifically refer to the horizontal parasitic PNP device in a kind of germanium silicium HBT technique, the invention still further relates to the manufacture method of described device.
Background technology
Horizontal parastic PNP triode in conventional germanium silicium HBT technique, its basic device architecture as shown in Figure 1, highly doped annular active area 9 by a P type is emitter, there is a polygonal region (region between emitter region 9) centre, above has dielectric layer 11 and polysilicon 8 to stop P type Implantation; Base stage is the epitaxial region of a N-type, has n type buried layer 2 below for low-resistance passage, and is connected to silicon face by the N-type electricity sinking passage 5 of outer ring; Current collection is a P type light doping section 6 very; Between emitter region 9 and collector region 6, be isolation by field oxygen 4 or shallow trench.The emitter region 9 of the device forming is like this polygonal outer shroud, its effective emitter area is the part that in Fig. 1, region 9 exceedes isolation from oxygen SiClx, base is L shaped, emitter area is less like this, base is wider, these two factors all can reduce the electric current from emitter diffusion to collector electrode, like this direct current multiplication factor H of lateral PNP fEcan be lower, generally below 25.But to some application, H fEmust be more than 50, intrinsic like this device application can be very limited.
Summary of the invention
Technical problem to be solved by this invention is to provide horizontal parasitic PNP device in a kind of germanium silicium HBT technique, to reduce base current, improves the cut-off frequency of device direct current multiplication factor or device.
Another technical problem to be solved by this invention is to provide the manufacture method of horizontal parasitic PNP device in described germanium silicium HBT technique.
For addressing the above problem, horizontal parasitic PNP device in germanium silicium HBT technique of the present invention, structure is:
Emitter region is a polygon ring that P type is heavily doped on the depression angle of device, is one is stopped by the emitter-window medium of germanium silicium HBT and the polygon forming of polysilicon in the centre of annular emitter region;
Base, is made up of the low-doped N-type epitaxial loayer on n type buried layer, and is drawn by buried regions and base sinking passage;
Collector region, is made up of low-doped P type ion implanted region and heavy doping draw-out area, the silicon face covering metal silicide of top, collector region;
In N-type epi-layer surface, the epitaxial surface between emitter region and collector region has dielectric layer and germanium and silicon epitaxial is done to isolate, and between collector region and base, isolates with shallow trench or an oxygen; The enclosing region of annular emitter region and annular emitter region covers germanium and silicon epitaxial, and the germanium and silicon epitaxial top of annular emitter region enclosing region is coated with dielectric layer, polysilicon and metal silicide successively; The silicon face of sinking passage top, base covers polysilicon and metal silicide successively; Also covering metal silicide on the germanium and silicon epitaxial of emitter region top;
Whole device surface has inter-level dielectric, each contact hole respectively break-through inter-level dielectric touches the metal silicide on described base sinking passage, collector region and top, emitter region germanium and silicon epitaxial, the base of parasitic PNP pipe, collector region and emitter region are drawn, form base stage, collector electrode and the emitter of described parasitic PNP pipe.
Further, described horizontal parasitic PNP device is concentric polygon on depression angle, is preferably octagon.
The manufacture method of the horizontal parasitic PNP device in germanium silicium HBT technique of the present invention, comprises the steps:
The 1st step forms heavily doped n type buried layer on P type silicon substrate, and carries out high temperature and advance for a long time;
The 2nd step, the lightly doped N-type epitaxial loayer of growing on n type buried layer;
The 3rd step, then on N-type epitaxial loayer, form shallow trench or an oxygen isolated area;
The 4th step, the heavily doped N-type sinking of Implantation electrical connecting passage is drawn n type buried layer, and the lightly doped P type of Implantation collector region, then carries out a high temperature and advances;
The 5th step, at N-type epitaxial surface deposit germanium silicon window medium, preferably dielectric material is one deck silica and one deck polysilicon, photoetching and dry quarter are opened germanium silicon window, growth germanium and silicon epitaxial layer, the active area of opening at window forms monocrystalline silicon, and other region forms polysilicon;
The 6th step, photoetching and the dry region of drawing for being connected with contact hole of carving outside emitter region and the active area that forms horizontal parasitic PNP;
The 7th step, photoetching and dry quarter form the Resistance at parasitic PNP emitter center and the polysilicon of base; And before removing, photoresist carries out the P type Implantation of low-yield high dose;
The 8th step, rapid thermal annealing activates the foreign ion injecting, then forms metal silicide, device surface deposit inter-level dielectric, and form successively contact hole and metal connecting line completes the connection to emitter, base stage and collector electrode.
Further, in described the 1st step, the injection ion of n type buried layer is arsenic, and implantation dosage is 10 15~10 16cm -2, energy is 50~100keV; The temperature that described high temperature advances is at 1000~1150 DEG C, and the time was at 30~300 minutes.
Further, in described the 2nd step, the doping ion of N-type extension is phosphorus, and bulk concentration is at 5x10 15~2x10 16cm -3.
Further, in described the 4th step, the injection ion of N-type sinking electrical connecting passage is phosphorus, and implantation dosage is 10 15~10 16cm -2, Implantation Energy is 50~100keV; P type light dope Implantation is boron, and implantation dosage is 5x10 12~5x10 13cm -2, Implantation Energy is 30~200keV; The temperature that high temperature advances is at 950~1050 DEG C, and the time was at 30~60 minutes.
Further, in described the 7th step, the P type Implantation of low-yield high dose is boron, and implantation dosage is 1x10 15cm -2above, Implantation Energy is 5~35KeV.
Further, in described the 8th step rta technique be temperature at 950~1100 DEG C, the time was at 10~60 seconds.
Horizontal parasitic PNP device in germanium silicium HBT technique of the present invention, by being formed centrally in emitter with polygonal ring, reduce base by the dissufion current of emitter region, between emitter region and collector region, replace Chang Yang district as isolation with germanium silicon dielectric layer, improve emitter area and reduce base width, increase collector current, improved the direct current multiplication factor H of described parasitic PNP device fE, also improved the cut-off frequency of device.
Brief description of the drawings
Fig. 1 is the profile of the horizontal parasitic PNP pipe of routine;
Fig. 2~9th, manufacturing technology steps explanation of the present invention;
Figure 10 is the vertical view of device of the present invention;
Figure 11 is manufacturing process flow diagram of the present invention.
Description of reference numerals
The 1st, substrate, the 2nd, buried regions, the 3rd, N-type extension, the 4th, an oxygen, the 5th, base sinking passage, the 6th, collector region, the 7th, germanium and silicon epitaxial, the 8th, polysilicon, the 9th, emitter region, the 10th, metal silicide, the 11st, dielectric layer, the 12nd, inter-level dielectric, the 13rd, contact hole.
Embodiment
In germanium silicium HBT technique of the present invention, horizontal parasitic PNP device accompanying drawings is as follows:
As shown in Figure 9, analysing and observe in angle, between emitter region 9 and collector region 6, done to isolate by the dielectric layer 11 of germanium silicon window, between collector region 6 and base (being N-type extension 3), isolating with shallow trench or an oxygen; Wherein:
Emitter region, it is the injection region 9 shown in Fig. 9, it on the depression angle of device, is a heavily doped polygon ring of P type, wherein active area part is emitter region, it outside active area, is exit, in the centre of annular emitter region be one by the emitter-window medium of germanium silicium HBT and the polygon forming of polysilicon, as stopping of P type Implantation;
Base, is made up of the low-doped N-type epitaxial loayer 3 on n type buried layer, and is drawn by buried regions 2 and base sinking passage 5;
Collector region, is made up of low-doped P type ion implanted region 6, the silicon face covering metal silicide 10 of 6 tops, collector region;
On N-type epitaxial loayer 3 surfaces, the enclosing region of annular emitter region 9 and annular emitter region covers germanium and silicon epitaxial 7, and germanium and silicon epitaxial 7 tops of annular emitter region 9 enclosing region are coated with dielectric layer 11 and polysilicon 8, metal silicide 10 successively; The silicon face of base sinking passage 5 tops covers polysilicon 8 and metal silicide 10 successively; Also covering metal silicide 10 on the germanium and silicon epitaxial 7 of 9 tops, emitter region;
Whole device surface has inter-level dielectric 12, each contact hole 13 respectively break-through inter-level dielectric 12 touches the metal silicide 10 on described base sinking passage 5, collector region 6 and emitter region 9 top germanium and silicon epitaxials 7, the base of parasitic PNP pipe 3, collector region 6 and emitter region 9 are drawn, form base stage, collector electrode and the emitter of described parasitic PNP pipe.
It is more than the structure explanation of PNP pipe of the present invention, on the depression angle of device, the present invention is polygon loop configuration, more is octagon, as shown in figure 10, collector region 6 is positioned at outer ring, is polysilicon isolated area between collector region and emitter region, cover polysilicon 8, the region that annular emitter region 9 surrounds and barrier layer, emitter region.Therefore the structure of annular presents symmetrical structure at analysing and observe shown in Fig. 9 in angle.
The manufacture method of RFLDMOS device of the present invention is first described as follows shown in 2~9 by reference to the accompanying drawings:
The 1st step, please refer to Fig. 2, on lightly doped P type substrate 1, optionally forms n type buried layer 2 by the mode of Implantation, and injection ion is arsenic, and Implantation Energy is 50~100keV, and dosage is 10 15cm -2above, then carry out long-time high temperature propelling, its temperature is at 1000~1150 DEG C, and the time, the bulk concentration of the n type buried layer finally forming was 10 at 30~300 minutes 20cm -3above.
The 2nd step, with reference to figure 3, the lightly doped N-type extension 2 of growing, its doping content is 10 14~10 16cm -3, the epitaxial thickness of deposit is according to the puncture voltage of germanium silicon NPN pipe; In the present embodiment, the device that is 12V to collector electrode-emitter maximum breakdown voltage, epitaxial thickness is 1.5 microns of left and right.
The 3rd step, as shown in Figure 4, forms shallow trench or an oxygen isolated area 4 at epitaxial surface.
The 4th step, the heavily doped N-type sinking of Implantation electrical connecting passage 5 is drawn n type buried layer 2, as shown in Figure 5.Injection ion is phosphorus, and implantation dosage is 10 15~10 16cm -2, energy is 50~100keV; And the lightly doped P type of Implantation collector region 6, injection ion is boron, implantation dosage is 5x10 12~5x10 13cm -2, energy is 30~200keV; Then carry out another high temperature and advance for a long time, temperature is at 950~1050 DEG C, and the time was at 30~60 minutes.
The 5th step, as shown in Figure 6, deposit germanium silicon window medium 11, can be preferably one deck silica and one deck polysilicon, the thickness of silica be at 200~600 dusts, and the thickness of polysilicon is at 300~600 dusts, photoetching and dry quarter are opened emitter window, growth germanium and silicon epitaxial layer 7, the active area of opening at window forms monocrystalline silicon, and other region forms polysilicon.
The 6th step, as shown in Figure 7, photoetching and the dry interior outer base area that forms germanium silicium HBT, the region of drawing for being connected with contact hole outside the emitter region of horizontal parasitic PNP and active area of carving.
The 7th step, as shown in Figure 8, the emitter-window medium 11 of deposit germanium silicium HBT NPN pipe, simultaneously, open the emitter-window of germanium silicium HBT in the active area, base of PNP, the emitter-polysilicon 8 of rear deposit germanium silicium HBT, photoetching and dry quarter form the Resistance polysilicon 8 at PNP emitter center and polysilicon 8 draw-out areas of base, and before photoresist is removed, carry out the P type Implantation of low-yield high dose, the heavy doping that forms emitter region 9 and collector region 6 is drawn.
The 8th step, rapid thermal annealing activates the foreign ion injecting, and temperature is at 950~1100 DEG C, and the time is in 10~60 seconds; Form metal silicide 10, deposit inter-level dielectric also forms successively contact hole 13 and metal connecting line (accompanying drawing is not shown) completes the connection to emitter, base stage and collector electrode again.Resulting devices complete figure as shown in Figure 9, the metal connecting line of device surface is not shown.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (9)

1. the horizontal parasitic PNP device in germanium silicium HBT technique, is characterized in that: comprise:
Emitter region is a polygon ring that P type is heavily doped on the depression angle of device, is one is stopped by the emitter-window medium of germanium silicium HBT and the polygon forming of polysilicon in the centre of annular emitter region;
Base, is made up of the low-doped N-type epitaxial loayer on n type buried layer, and is drawn by buried regions and base sinking passage;
Collector region, is made up of low-doped P type ion implanted region and heavy doping draw-out area, the silicon face covering metal silicide of top, collector region;
In N-type epi-layer surface, the epitaxial surface between emitter region and collector region is done to isolate by dielectric layer and germanium and silicon epitaxial, between collector region and base, isolates with shallow trench or an oxygen; The enclosing region of annular emitter region and annular emitter region covers germanium and silicon epitaxial,, and the germanium and silicon epitaxial of annular emitter region enclosing region top is coated with dielectric layer and polysilicon, covering metal silicide on polysilicon successively; The silicon face of sinking passage top, base covers polysilicon and metal silicide successively; Also covering metal silicide on the germanium and silicon epitaxial of emitter region top;
Whole device surface has inter-level dielectric, each contact hole respectively break-through inter-level dielectric touches the metal silicide on described base sinking passage, collector region and top, emitter region germanium and silicon epitaxial, the base of parasitic PNP pipe, collector region and emitter region are drawn, form base stage, collector electrode and the emitter of described parasitic PNP pipe.
2. the horizontal parasitic PNP device in germanium silicium HBT technique as claimed in claim 1, is characterized in that: described horizontal parasitic PNP device is concentric polygon on depression angle, and common is octagon.
3. the manufacture method of the horizontal parasitic PNP device in germanium silicium HBT technique according to claim 1, is characterized in that, comprises the steps:
The 1st step forms heavily doped n type buried layer on P type silicon substrate, and carries out high temperature and advance for a long time;
The 2nd step, the lightly doped N-type epitaxial loayer of growing on n type buried layer;
The 3rd step, then on N-type epitaxial loayer, form shallow trench or an oxygen isolated area;
The 4th step, the heavily doped N-type sinking of Implantation electrical connecting passage is drawn n type buried layer, and the lightly doped P type of Implantation collector region, then carries out a high temperature and advances;
The 5th step, at N-type epitaxial surface deposit germanium silicon window medium, photoetching and dry quarter are opened germanium silicon window, growth germanium and silicon epitaxial layer, the active area of opening at window forms monocrystalline silicon, and other region forms polysilicon;
The 6th step, photoetching and the dry region of drawing for being connected with contact hole of carving outside emitter region and the active area that forms horizontal parasitic PNP;
The 7th step, photoetching and dry quarter form the Resistance at parasitic PNP emitter center and the polysilicon of base, and before photoresist is removed, carry out the P type Implantation of low-yield high dose;
The 8th step, rapid thermal annealing activates the foreign ion injecting, then forms metal silicide, device surface deposit inter-level dielectric, and form successively contact hole and metal connecting line completes the connection to emitter, base stage and collector electrode.
4. the manufacture method of the horizontal parasitic PNP device in germanium silicium HBT technique according to claim 3, is characterized in that: in described the 1st step, the injection ion of n type buried layer is arsenic, and implantation dosage is 10 15~10 16cm -2, energy is 50~100keV; The temperature that described high temperature advances is at 1000~1150 DEG C, and the time was at 30~300 minutes.
5. the manufacture method of the horizontal parasitic PNP device in germanium silicium HBT technique according to claim 3, is characterized in that: in described the 2nd step, the doping ion of N-type extension is phosphorus, and bulk concentration is at 5x10 15~2x10 16cm -3.
6. the manufacture method of the horizontal parasitic PNP device in germanium silicium HBT technique according to claim 3, is characterized in that: in described the 4th step, the injection ion of N-type sinking electrical connecting passage is phosphorus, and implantation dosage is 10 15~10 16cm -2, Implantation Energy is 50~100keV; P type light dope Implantation is boron, and implantation dosage is 5x10 12~5x10 13cm -2, Implantation Energy is 30~200keV; The temperature that high temperature advances is at 950~1050 DEG C, and the time was at 30~60 minutes.
7. the manufacture method of the horizontal parasitic PNP device in germanium silicium HBT technique according to claim 3, is characterized in that: in described the 5th step, preferably dielectric material is one deck silica and one deck polysilicon.
8. the manufacture method of the horizontal parasitic PNP device in germanium silicium HBT technique according to claim 3, is characterized in that: in described the 7th step, the P type Implantation of low-yield high dose is boron, and implantation dosage is 1x10 15cm -2above, Implantation Energy is 5~35KeV.
9. the manufacture method of the horizontal parasitic PNP device in germanium silicium HBT technique according to claim 3, is characterized in that: in described the 8th step rta technique be temperature at 950~1100 DEG C, the time was at 10~60 seconds.
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CN106158616A (en) * 2014-08-08 2016-11-23 爱思开海力士有限公司 3 D semiconductor IC-components and manufacture method thereof
CN111354776A (en) * 2018-12-21 2020-06-30 瑞能半导体科技股份有限公司 Bipolar triode device and preparation method thereof
CN112951904A (en) * 2021-03-29 2021-06-11 西安微电子技术研究所 NPN transistor with low on-resistance and high amplification factor and preparation method thereof

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CN111354776A (en) * 2018-12-21 2020-06-30 瑞能半导体科技股份有限公司 Bipolar triode device and preparation method thereof
CN112951904A (en) * 2021-03-29 2021-06-11 西安微电子技术研究所 NPN transistor with low on-resistance and high amplification factor and preparation method thereof

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