CN103107186B

CN103107186B - Parasitic N-I-P type PIN device structure and manufacture method thereof in a kind of BiCMOS technique

Info

Publication number: CN103107186B
Application number: CN201110355686.2A
Authority: CN
Inventors: 胡君; 刘冬华; 钱文生; 段文婷; 石晶
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-11
Filing date: 2011-11-11
Publication date: 2016-06-08
Anticipated expiration: 2031-11-11
Also published as: CN103107186A

Abstract

The present invention discloses parasitic N-I-P type PIN device structure in a kind of BiCMOS technique, comprise: P type substrate is formed active area, P type bear buried regions and shallow trench isolation from, shallow trench isolation bears the top of buried regions from being formed at P type, P type bears buried regions and shallow trench isolation to off normal in both sides, active area, and P type bears buried regions to be connected with active area; N-type heavily doped region is formed at active region, and polysilicon layer is formed at above money channel separating zone adjacent with N-type heavily doped region; N-type heavily doped region and P type bear buried regions to draw connection metal line by contact hole respectively. The invention also discloses the manufacture method of parasitic N-I-P type PIN device structure in a kind of BiCMOS technique. The parasitic N-I-P type PIN device structure of the present invention and manufacture method thereof can realize insertion loss at below 2dB, and isolation reaches more than 30dB.

Description

Parasitic N-I-P type PIN device structure and manufacture method thereof in a kind of BiCMOS technique

Technical field

The present invention relates to field of semiconductor manufacture, particularly relate to parasitic N-IP type PIN device architecture in a kind of BiCMOS technique. The present invention also relates to the manufacture method of parasitic N-IP type PIN device architecture in a kind of BiCMOS technique.

Background technology

Conventional Bipolar (insulated gate bipolar transistor npn npn) adopts the collector region buried regions of high doping, to reduce collector region resistance, adopt high density high-energy N type to inject, connect collector region buried regions, form collector terminal (collectorpick-up). The collector region that buried regions upper outside Yanzhong in collector region is low-doped, the extension in the doping of P type forms Ji Qu, and then heavy N-type doped polycrystalline silicon forms emtting electrode, finally completes the making of bipolar.

Summary of the invention

The parasitic N-I-P type PIN device structure that the technical problem to be solved in the present invention is to provide in a kind of BICMOS technique can realize low insertion loss and high-isolation. For this reason, present invention also offers the making method of the parasitic N-I-P type PIN device structure in a kind of BICMOS technique.

For solving the problems of the technologies described above, the parasitic N-I-P type PIN device structure of the present invention, comprise: P type substrate is formed active area, P type bear buried regions and shallow trench isolation from, shallow trench isolation bears the top of buried regions from being formed at P type, P type bears buried regions and shallow trench isolation to off normal in both sides, active area, and P type bears buried regions to be connected with active area; N-type heavily doped region is formed at active region, and polysilicon layer is formed at above money channel separating zone adjacent with N-type heavily doped region; N-type heavily doped region and P type bear buried regions to draw connection metal line by contact hole respectively.

Wherein, described active area has p type impurity.

The manufacture method of the parasitic N-I-P type PIN device structure of the present invention, comprising:

(1) make in P type substrate shallow trench isolation from, shallow trench isolation from bottom inject formed P type bear buried regions;

(2) depositing polysilicon layer;

(3) formation N-type heavily doped region is injected;

(4) remove part polysilicon layer, bear buried regions and N-type heavily doped region to be drawn by contact hole respectively on P type, fill titanium or tin and tungsten in the contact hole, connection metal line.

Improving further, between step (2) and (3), increase step (A) is injected doped with P type impurity and is formed with source region, thermal annealing.

Improving further, time implementation step (1), inject boron or indium impurity, dosage is 1e14cm^-2To 1e16cm^-2, energy is less than 15keV.

Improving further, time implementation step (4), inject phosphorus or arsenic impurities, dosage is 1e14cm^-2To 1e16cm^-2, energy is 2keV to 100keV.

Improving further, time implementation step (A), inject boron or indium impurity, dosage is 1e12cm^-2To 5e13cm^-2, energy is 100keV to 2000keV.

Parasitic its p type island region of N-I-P type PIN device structure of the present invention by carrying out high dosage from bottom at shallow trench isolation, low-yield p type impurity injects and formed; Its I type district carries out P type light dope and injects or do not carry out impurity injection formation in active area; Its N-type region, at area surface depositing polysilicon (and emitter-polysilicon of NPN pipe), carries out heavy doping and injects formation. Control described active area width, ensure to bear the P type heavy doping of buried regions can spread and effectively connect in centre in the past.

The parasitic N-I-P type PIN device structure of the present invention simulates (as shown in Figure 3) from TCAD (Computer-aided Design Technology), for SiGeHBT, base district epi dopant be the result of parasitic PIN of germanium and boron, in (the including area width etc.) situation choosing suitable PIN structural, this PIN device can realize insertion loss at below 2dB, isolation reaches more than 30dB. the parasitic N-I-P type PIN device structure of the present invention and making method thereof can realize low insertion loss and high-isolation.

Accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Fig. 1 is the schematic diagram of a kind of traditional PI N device structure.

Fig. 2 is the schematic diagram of PIN device architecture of the present invention.

Fig. 3 is PIN device architecture of the present invention and traditional PI N device structure forward voltage-current characteristics graphic representation.

Fig. 4 is the schema of PIN device architecture manufacture method of the present invention.

Fig. 5 is the schematic diagram one of PIN device architecture manufacture method of the present invention, the device architecture that its step display (1) is formed.

Fig. 6 is the schematic diagram one of PIN device architecture manufacture method of the present invention, the device architecture that its step display (2) is formed.

Fig. 7 is the schematic diagram two of PIN device architecture manufacture method of the present invention, the device architecture that its step display (3) is formed.

Fig. 8 is the schematic diagram three of PIN device architecture manufacture method of the present invention, the device architecture that its step display (4) is formed.

Embodiment

As shown in Figure 2, the parasitic N-I-P type PIN device structure of the present invention, comprise: P type substrate is formed active area, P type bear buried regions and shallow trench isolation from, shallow trench isolation bears the top of buried regions from being formed at P type, P type bears buried regions and shallow trench isolation to off normal in both sides, active area, and P type bears buried regions to be connected with active area; N-type heavily doped region is formed at active region, and polysilicon layer is formed at above money channel separating zone adjacent with N-type heavily doped region; N-type heavily doped region and P type bear buried regions to draw connection metal line by contact hole respectively; Wherein, described active area has p type impurity.

As shown in Figure 4, the manufacture method of the parasitic N-I-P type PIN device structure of the present invention, comprising:

(1) as shown in Figure 5, P type substrate makes shallow trench isolation from, shallow trench isolation from bottom inject formed P type bear buried regions;

As shown in Figure 6, (2) inject doped with P type impurity and it is formed with source region, thermal annealing.

As shown in Figure 7, (3) depositing polysilicon layer;

As shown in Figure 8, (4) formation N-type heavily doped region is injected;

(5) removing part polysilicon layer, bear buried regions and N-type heavily doped region to be drawn by contact hole respectively on P type, fill titanium or tin and tungsten in the contact hole, connection metal line forms device architecture as shown in Figure 1.

Below through the specific embodiment and the embodiment to invention has been detailed description, but these are not construed as limiting the invention. Without departing from the principles of the present invention, the technician of this area also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. parasitic N-I-P type PIN device structure in a BiCMOS technique, it is characterized in that, comprise: P type substrate has injected by P type light dope or do not carry out the P type that impurity injects the active area that formed, implanting p-type ion is formed bear buried regions and shallow trench isolation from, shallow trench isolation bears the top of buried regions from being formed at P type, P type bears buried regions and shallow trench isolation to off normal in both sides, active area, and P type bears buried regions to be connected with active area; In the polysilicon of area surface deposit, heavy doping is injected and is formed N-type heavily doped region, and N-type heavily doped region is positioned at active region, and polysilicon layer is formed at above shallow channel isolation area adjacent with N-type heavily doped region; N-type heavily doped region and P type bear buried regions to draw connection metal line by contact hole respectively.

2. parasitic N-I-P type PIN device structure as claimed in claim 1, is characterized in that: described active area has p type impurity.

3. the manufacture method of parasitic N-I-P type PIN device structure in BiCMOS technique, is characterized in that, comprising:

(2) depositing polysilicon layer;

(3) formation N-type heavily doped region is injected;

4. manufacture method as claimed in claim 3, is characterized in that: between step (2) and (3), and increase step (A) is injected doped with P type impurity and is formed with source region, thermal annealing.

5. manufacture method as claimed in claim 3, is characterized in that: time implementation step (1), injects boron or indium impurity, and dosage is 1e14cm^-2To 1e16cm^-2, energy is less than 15keV.

6. manufacture method as claimed in claim 3, is characterized in that: time implementation step (4), injects phosphorus or arsenic impurities, and dosage is 1e14cm^-2To 1e16cm^-2, energy is 2keV to 100keV.

7. manufacture method as claimed in claim 4, is characterized in that: time implementation step (A), injects boron or indium impurity, and dosage is 1e12cm^-2To 5e13cm^-2, energy is 100keV to 2000keV.