CN103123931B - Parasitic N-I-P type PIN device structure and manufacture method thereof in a kind of BiCMOS technique - Google Patents
Parasitic N-I-P type PIN device structure and manufacture method thereof in a kind of BiCMOS technique Download PDFInfo
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- CN103123931B CN103123931B CN201110372027.XA CN201110372027A CN103123931B CN 103123931 B CN103123931 B CN 103123931B CN 201110372027 A CN201110372027 A CN 201110372027A CN 103123931 B CN103123931 B CN 103123931B
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Abstract
The invention discloses parasitic N-I-P type PIN device structure in a kind of BiCMOS technique, comprise: above P type substrate, be formed with active area, the counterfeit buried regions of P type is formed in active area, be formed above the counterfeit buried regions of P type multiple shallow trench isolation from, shallow trench isolation is formed with polysilicon layer from putting, active region is formed with emitter region, emitter region and polysilicon layer are alternately arranged, connection metal line is drawn by contact hole in emitter region, the counterfeit buried regions of P type draws connection metal line by dark contact hole, has titanium or tin and tungsten in dark contact hole.The invention also discloses the manufacture method of parasitic N-I-P type PIN device structure in a kind of BiCMOS technique.Parasitic N-I-P type PIN device structure of the present invention and manufacture method thereof can increase the forward conduction electric current of PIN device, increase the effective area of PIN device, reduce the insertion loss of PIN device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to parasitic N-I-P type PIN device structure in a kind of BiCMOS technique.The invention still further relates to the manufacture method of parasitic N-I-P type PIN device structure in a kind of BiCMOS technique.
Background technology
Conventional Bipolar (insulated gate bipolar transistor) adopts highly doped collector region buried regions, to reduce collector region resistance, adopt high concentration high-energy N type to inject, connect collector region buried regions, form collector terminal (collectorpick-up).The collector region that buried regions upper outside Yanzhong in collector region is low-doped, form base in the extension of P type doping, then heavy N-type doped polycrystalline silicon forms emitter, finally completes the making of bipolar.As shown in Figure 1, a kind of its shortcoming of traditional PI N device structure is that forward conduction current capacity is limited, and insertion loss is large.
Summary of the invention
The technical problem to be solved in the present invention is to provide parasitic N-I-P type PIN device structure in a kind of BiCMOS technique can increase the forward conduction electric current of PIN device, increases the effective area of PIN device, reduces the insertion loss of PIN device.For this reason, present invention also offers the manufacture method of parasitic N-I-P type PIN device structure in a kind of BiCMOS technique.
For solving the problems of the technologies described above, the parasitic N-I-P type PIN device structure of the present invention, comprise: above P type substrate, be formed with active area, the counterfeit buried regions of P type is formed in active area, be formed above the counterfeit buried regions of P type multiple shallow trench isolation from, shallow trench isolation is formed with polysilicon layer from putting, active region is formed with emitter region, emitter region and polysilicon layer are alternately arranged, connection metal line is drawn by contact hole in emitter region, the counterfeit buried regions of P type draws connection metal line by dark contact hole, has titanium or tin and tungsten in dark contact hole.
The counterfeit buried regions of described P type has boron or indium impurity.
Described active area has phosphorus or arsenic impurities.
Described emitter region has phosphorus or arsenic impurities.
The manufacture method of the parasitic N-I-P type PIN device structure of the present invention, comprising:
(1) make in P type substrate multiple shallow trench isolation from, to inject from bottom at shallow trench isolation and form P type counterfeit buried regions;
(2) injection is formed with source region, thermal annealing, makes the counterfeit diffusion of buried layer of P type realize overlap each other;
(3) growing polycrystalline silicon layer;
(4) formation emitter region is injected;
(5) connection metal line is drawn by contact hole in emitter region, counterfeit for P type buried regions is drawn connection metal line by dark contact hole.
Further improvement, time implementation step (1), implanted dopant is boron or indium, and dosage is 1e14cm
-2to 1e16cm
-2, energy is less than 15keV.
Further improvement, time implementation step (2), implanted dopant is phosphorus or arsenic, and dosage is 1e12cm
-2to 5e13cm
-2, energy is 100keV to 2000keV.
Further improvement, time implementation step (4), implanted dopant is phosphorus or arsenic, and dosage is 1e14cm
-2to 1e16cm
-2, energy is 2keV to 100keV.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is a kind of schematic diagram of traditional PI N device structure.
Fig. 2 is the schematic diagram of PIN device architecture of the present invention.
Fig. 3 is the flow chart of PIN device architecture manufacture method of the present invention.
Fig. 4 is the schematic diagram one of PIN device architecture manufacture method of the present invention, the device architecture that its step display (1) is formed.
Fig. 5 is the schematic diagram one of PIN device architecture manufacture method of the present invention, the device architecture that its step display (2) is formed.
Fig. 6 is the schematic diagram two of PIN device architecture manufacture method of the present invention, the device architecture that its step display (3) is formed.
Fig. 7 is the schematic diagram three of PIN device architecture manufacture method of the present invention, the device architecture that its step display (4) is formed.
Embodiment
As shown in Figure 2, the parasitic N-I-P type PIN device structure of the present invention, comprising:
Active area is formed above P type substrate, the counterfeit buried regions of P type is formed in active area, be formed above the counterfeit buried regions of P type multiple shallow trench isolation from, shallow trench isolation is formed with polysilicon layer from putting, active region is formed with emitter region, and emitter region and polysilicon layer are alternately arranged, and connection metal line is drawn by contact hole in emitter region, the counterfeit buried regions of P type draws connection metal line by dark contact hole, has titanium or tin and tungsten in dark contact hole.
As shown in Figure 3, the manufacture method of the parasitic N-I-P type PIN device structure of the present invention, comprising:
(1) as shown in Figure 4, P type substrate makes multiple shallow trench isolation from, to inject from bottom at shallow trench isolation and form P type counterfeit buried regions;
(2) as shown in Figure 5, inject and be formed with source region, thermal annealing, make the counterfeit diffusion of buried layer of P type realize overlap each other;
(3) as shown in Figure 6, growing polycrystalline silicon layer;
(4) formation emitter region as shown in Figure 7, is injected;
(5) connection metal line is drawn by contact hole in emitter region, counterfeit for P type buried regions is drawn connection metal line by dark contact hole, forms device as shown in Figure 2.
Below through the specific embodiment and the embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. parasitic N-I-P type PIN device structure in a BiCMOS technique, it is characterized in that, comprise: above P type substrate, be formed with active area, the counterfeit buried regions of P type is formed in active area, be formed above the counterfeit buried regions of P type multiple shallow trench isolation from, shallow trench isolation is formed with polysilicon layer from top, active region is formed with emitter region, emitter region and polysilicon layer are alternately arranged, connection metal line is drawn by contact hole in emitter region, the counterfeit buried regions of P type draws connection metal line by dark contact hole, there is in dark contact hole titanium and tungsten, or tin and tungsten, described active area has phosphorus or arsenic impurities.
2. PIN device architecture as claimed in claim 1, is characterized in that: the counterfeit buried regions of described P type has boron or indium impurity.
3. PIN device architecture as claimed in claim 1, is characterized in that: described emitter region has phosphorus or arsenic impurities.
4. the manufacture method of parasitic N-I-P type PIN device structure in BiCMOS technique, is characterized in that, comprising:
(1) make in P type substrate multiple shallow trench isolation from, to inject from bottom at shallow trench isolation and form P type counterfeit buried regions;
(2) injection is formed with source region, thermal annealing, makes the counterfeit diffusion of buried layer of P type realize overlap each other;
(3) shallow trench isolation from active region growing polycrystalline silicon layer;
(4) polysilicon layer of side injects formation emitter region on the active area;
(5) connection metal line is drawn by contact hole in emitter region, counterfeit for P type buried regions is drawn connection metal line by dark contact hole.
5. the manufacture method of PIN device architecture as claimed in claim 4, it is characterized in that: time implementation step (1), implanted dopant is boron or indium, and dosage is 1e14cm-2 to 1e16cm-2, and energy is less than 15keV.
6. the manufacture method of PIN device architecture as claimed in claim 4, it is characterized in that: time implementation step (2), implanted dopant is phosphorus or arsenic, and dosage is 1e12cm-2 to 5e13cm-2, and energy is 100keV to 2000keV.
7. the manufacture method of PIN device architecture as claimed in claim 4, it is characterized in that: time implementation step (4), implanted dopant is phosphorus or arsenic, and dosage is 1e14cm-2 to 1e16cm-2, and energy is 2keV to 100keV.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110372027.XA CN103123931B (en) | 2011-11-21 | 2011-11-21 | Parasitic N-I-P type PIN device structure and manufacture method thereof in a kind of BiCMOS technique |
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|---|---|---|---|
| CN201110372027.XA CN103123931B (en) | 2011-11-21 | 2011-11-21 | Parasitic N-I-P type PIN device structure and manufacture method thereof in a kind of BiCMOS technique |
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| CN103123931A CN103123931A (en) | 2013-05-29 |
| CN103123931B true CN103123931B (en) | 2016-04-13 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102104062A (en) * | 2009-12-21 | 2011-06-22 | 上海华虹Nec电子有限公司 | Bipolar transistor |
| CN102117748A (en) * | 2009-12-31 | 2011-07-06 | 上海华虹Nec电子有限公司 | Method for manufacturing collector region and collector region buried layer of bipolar transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03145771A (en) * | 1989-10-31 | 1991-06-20 | Hamamatsu Photonics Kk | Semiconductor device |
| DE10252878A1 (en) * | 2002-11-12 | 2004-06-03 | X-Fab Semiconductor Foundries Ag | Monolithically integrated vertical pin photodiode integrated in BiCMOS technology |
| CN103107186B (en) * | 2011-11-11 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | Parasitic N-I-P type PIN device structure and manufacture method thereof in a kind of BiCMOS technique |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102104062A (en) * | 2009-12-21 | 2011-06-22 | 上海华虹Nec电子有限公司 | Bipolar transistor |
| CN102117748A (en) * | 2009-12-31 | 2011-07-06 | 上海华虹Nec电子有限公司 | Method for manufacturing collector region and collector region buried layer of bipolar transistor |
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