CN106057878A - IGBT device and process method - Google Patents
IGBT device and process method Download PDFInfo
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- CN106057878A CN106057878A CN201610620601.1A CN201610620601A CN106057878A CN 106057878 A CN106057878 A CN 106057878A CN 201610620601 A CN201610620601 A CN 201610620601A CN 106057878 A CN106057878 A CN 106057878A
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000008569 process Effects 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000002347 injection Methods 0.000 claims abstract description 5
- 239000007924 injection Substances 0.000 claims abstract description 5
- 238000000407 epitaxy Methods 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000009825 accumulation Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005404 monopole Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Abstract
The invention discloses an IGBT device. A heavily doped P type layer, a P type well, an N type doped layer, an N type epitaxial layer, an N type buffer layer and a substrate are orderly on a P type silicon substrate from top to bottom. The substrate is the collector of the IGBT device. The trench gate of the IGBT device goes through the heavily doped P type layer, the P type well and the N type doped layer, the bottom is in the N type epitaxial layer, and a gate and silicon are separated by the gate oxide layer. In the heavily doped P type layer, the periphery of the trench gate is provided with a heavily doped N type area to form the emitter of an IGBT. Through optimizing a front side MOS structure, the electron injection efficiency of one end near an emitting area is improved, thus the conduction drop is optimized, the turn-off energy loss of each switching cycle can be reduced, a carrier storage layer is arranged, under the premise of high breakdown voltage, the chip area is reduced further. The invention also discloses the process method of the IGBT device.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, particularly relate to a kind of IGBT device, the invention still further relates to described
The process of IGBT device.
Background technology
IGBT (Insulated Gate Bipolar Transistor) insulated gate bipolar transistor, is (double by BJT
Polar form audion) and the compound full-control type voltage driven type power semiconductor that forms of MOS (insulating gate type field effect tube), its
Though switching speed is low compared with power MOS, but far above BJT, again because being voltage control device, control circuit is simple, good stability, holds concurrently
There is advantage of both the high input impedance of MOSFET and the low conduction voltage drop of GTR.There is MOS input, bipolar output function
MOS, the bipolar feature combined, become the main product of new generation of field of power electronics.
IGBT is as a kind of bipolar device, and for comparing MOSFET monopole type device, bipolar device is in robustness side
Face design optimization is the most crucial.It is said that in general, higher IGBT blocking voltage and less size can make Vce (sat) (collect-penetrate
Interpolar electricity) increase.
Summary of the invention
The technical problem to be solved is to provide a kind of IGBT device, has more conducting pressure drop and conduction loss.
Another technical problem to be solved by this invention is to provide the process of described IGBT device.
For solving the problems referred to above, IGBT device of the present invention, P-type silicon substrate is followed successively by heavy doping from top to bottom
P-type layer, p-type trap, n-type doping layer, N-type epitaxy layer, N-type cushion and substrate, substrate is as the colelctor electrode of IGBT device；
The groove type grid of IGBT device runs through heavily doped P-type layer, p-type trap, n-type doping layer, and bottom is positioned at N-type epitaxy layer
In, spacer grid oxide layer between grid and silicon；
In described heavily doped P-type layer, the periphery of groove type grid has heavily doped N-type district and forms the emitter stage of IGBT.
Described p-type trap is as the channel region of IGBT, and N-type epitaxy layer is as the N-type drift region of IGBT.
For solving the problems referred to above, manufacture the process of IGBT device of the present invention, comprise following processing step:
1st step, forms N-type epitaxy layer in P type substrate；
2nd step, in N-type epitaxy layer, etching forms groove；
3rd step, injects in the epitaxial layer and forms n-type doping layer；
4th step, grows gate oxide；
5th step, forms polysilicon gate in groove；
6th step, forms p-type trap；
7th step, forms heavily doped N-type district and heavily doped P-type floor；
8th step, the back side is injected and is formed N-type cushion.
Further, in described 3rd step, the mode using oblique angle to inject injects formation n-type doping layer, note in the epitaxial layer
The concentration entered is 1E15～5E17/CM3。
Further, in described 4th step, gate oxide is generated by thermal oxidation method.
Further, in described 5th step, depositing polysilicon in groove, then perform etching, form groove-shaped polysilicon
Grid.
IGBT device of the present invention, by optimizing front MOS structure, improves the electronics near one end, launch site and injects
Efficiency, thus optimize conduction voltage drop, also can reduce closedown (Turn-off) energy loss in each switching circulation, there is current-carrying
Sub-accumulation layer can reduce chip area on the premise of high-breakdown-voltage further.
Accompanying drawing explanation
Fig. 1～8 is present invention process method each step schematic diagram.
Fig. 9 is the Vce curve synoptic diagram of the present invention and existing structure.
Figure 10 is the forward voltage drop simulation curve figure of the present invention and existing structure.
Figure 11 is present invention process flow chart of steps.
Description of reference numerals
101 is P type substrate, and 102 is N-type epitaxy layer, and 103 is groove, and 104 is n-type doping layer, and 105 is gate oxide,
106 is polysilicon gate, and 107 is p-type trap, and 108 is heavily doped N-type district, and 109 is heavily doped P-type district, and 110 is N-type cushion.
Detailed description of the invention
IGBT device of the present invention as shown in Figure 8, is followed successively by heavily doped P-type layer in P-type silicon substrate from top to bottom
109, p-type trap 107, n-type doping layer 104, N-type epitaxy layer 102, N-type cushion 110 and substrate 101, substrate 101 is as IGBT
The colelctor electrode of device.
The groove type grid of IGBT device runs through heavily doped P-type layer 109, p-type trap 107, n-type doping layer 104, and bottom is positioned at
In N-type epitaxy layer 102, spacer grid oxide layer 105 between grid 106 and silicon.
In described heavily doped P-type layer 109, the periphery of groove type grid has heavily doped N-type district 108 and forms the transmitting of IGBT
Pole.
Described p-type trap 107 is as the channel region of IGBT, and N-type epitaxy layer 102 is as the N-type drift region of IGBT.
The present invention, by optimizing front MOS structure, increases the n-type doping layer 104 as carrier accumulation layer, this doped layer
Shorten channel length, and add holoe carrier and flow to the potential barrier of IGBT emitter stage, limit the hole fortune to p-well direction
Dynamic, hole is stored in n-type doping district near N-type epitaxy layer side, improves the electron injection efficiency near one end, launch site, from
And optimize conduction voltage drop.Therefore, relatively low Vce (sat) is the major advantage that the present invention has carrier accumulation layer IGBT, simultaneously
Also can reduce closedown (Turn-off) energy loss in each switching circulation.Having carrier accumulation layer can be at high-breakdown-voltage
On the premise of, reduce chip area further.
As it is shown in figure 9, show the Potential Distributing of near surface in the case of Vce=0V in figure, existing structure is in p-type trap
Electromotive force is to the monolateral decline in emitter stage side, and due to the fact that the existence in n-type doping district 104, declines after the lifting of electromotive force elder generation, increases
Barrier height.
Shown in Figure 10 is the forward voltage drop simulation curve figure of the present invention and existing structure, and n-type doping district is below p-type trap
Define the accumulation layer in a hole, and add electronics in the on-state and, from the injection efficiency of MOS raceway groove, thus enhance
Conductivity modulation effect at this, can be greatly reduced the conduction loss of device.
The process of IGBT device of the present invention, comprises following processing step:
1st step, forms N-type epitaxy layer 102, as shown in Figure 1 in P type substrate 101.Described substrate 101 serves as a contrast for low-resistance
The end.
2nd step, as in figure 2 it is shown, etching forms groove 103 in N-type epitaxy layer 102, this groove is used for forming grid.
3rd step, injects in epitaxial layer 102 and forms n-type doping layer 104；Use the mode that oblique angle injects in the epitaxial layer
Injecting and form n-type doping layer, the concentration of injection is 1E15～5E17/CM3.As shown in Figure 3.
4th step, grows gate oxide 105 by thermal oxidation method.As shown in Figure 4.
5th step, as it is shown in figure 5, depositing polysilicon in groove, then performs etching, and forms groove-shaped polysilicon gate
106。
6th step, ion implanting forms p-type trap 107, as shown in Figure 6.
7th step, as it is shown in fig. 7, form heavily doped N-type district 108 and heavily doped P-type floor 109.
8th step, the back side is injected and is formed N-type cushion 110.Element manufacturing completes.As shown in Figure 8.
Technique realize on, owing to n-type doping district is positioned at bottom p-type trap, conventional flowsheet need high-energy inject and
Long Time Thermal advances, and the mode that the present invention uses oblique angle to inject after etching groove completes forms n-type doping district, saves technique
Cost, the mode that oblique angle injects simultaneously, due to the existence of groove high-aspect-ratio, does not interferes with the doping content of channel bottom, from
And ensure that the pressure of device.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.Those skilled in the art is come
Saying, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of being made, equivalent
Replacement, improvement etc., should be included within the scope of the present invention.
Claims (6)
1. an IGBT device, it is characterised in that: in P-type silicon substrate, it is followed successively by heavily doped P-type layer, p-type trap, N from top to bottom
Type doped layer, N-type epitaxy layer, N-type cushion and substrate, substrate is as the colelctor electrode of IGBT device；
The groove type grid of IGBT device runs through heavily doped P-type layer, p-type trap, n-type doping layer, and bottom is positioned in N-type epitaxy layer,
Spacer grid oxide layer between grid and silicon；
In described heavily doped P-type layer, the periphery of groove type grid has heavily doped N-type district and forms the emitter stage of IGBT.
2. IGBT device as claimed in claim 1, it is characterised in that: p-type trap is made as the channel region of IGBT, N-type epitaxy layer
N-type drift region for IGBT.
3. manufacture the process of IGBT device as claimed in claim 1, it is characterised in that: comprise following processing step:
1st step, forms N-type epitaxy layer in P type substrate；
2nd step, in N-type epitaxy layer, etching forms groove；
3rd step, injects in the epitaxial layer and forms n-type doping layer；
4th step, grows gate oxide；
5th step, forms polysilicon gate in groove；
6th step, forms p-type trap；
7th step, forms heavily doped N-type district and heavily doped P-type floor；
8th step, the back side is injected and is formed N-type cushion.
4. the process of IGBT device as claimed in claim 3, it is characterised in that: in described 3rd step, use oblique angle to inject
Mode in the epitaxial layer inject formation n-type doping layer, the concentration of injection is 1E15～5E17/CM3。
5. the process of IGBT device as claimed in claim 3, it is characterised in that: in described 4th step, pass through thermal oxidation method
Generate gate oxide.
6. the process of IGBT device as claimed in claim 3, it is characterised in that: in described 5th step, in groove, deposit is many
Crystal silicon, then performs etching, and forms groove-shaped polysilicon gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610620601.1A CN106057878A (en) | 2016-08-01 | 2016-08-01 | IGBT device and process method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610620601.1A CN106057878A (en) | 2016-08-01 | 2016-08-01 | IGBT device and process method |
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| Publication Number | Publication Date |
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| CN106057878A true CN106057878A (en) | 2016-10-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610620601.1A Pending CN106057878A (en) | 2016-08-01 | 2016-08-01 | IGBT device and process method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504313A (en) * | 2019-08-29 | 2019-11-26 | 电子科技大学 | A kind of lateral trench type insulated gate bipolar transistor and preparation method thereof |
| CN111785628A (en) * | 2020-06-28 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of IGBT device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6001678A (en) * | 1995-03-14 | 1999-12-14 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| US6570185B1 (en) * | 1997-02-07 | 2003-05-27 | Purdue Research Foundation | Structure to reduce the on-resistance of power transistors |
| JP2010232627A (en) * | 2009-03-04 | 2010-10-14 | Fuji Electric Systems Co Ltd | Semiconductor device and method of manufacturing the same |
| CN105789291A (en) * | 2016-04-26 | 2016-07-20 | 电子科技大学 | Double split trench gate charge storage type insulated gate bipolar transistor (IGBT) and manufacturing method thereof |
-
2016
- 2016-08-01 CN CN201610620601.1A patent/CN106057878A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6001678A (en) * | 1995-03-14 | 1999-12-14 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| US6570185B1 (en) * | 1997-02-07 | 2003-05-27 | Purdue Research Foundation | Structure to reduce the on-resistance of power transistors |
| JP2010232627A (en) * | 2009-03-04 | 2010-10-14 | Fuji Electric Systems Co Ltd | Semiconductor device and method of manufacturing the same |
| CN105789291A (en) * | 2016-04-26 | 2016-07-20 | 电子科技大学 | Double split trench gate charge storage type insulated gate bipolar transistor (IGBT) and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504313A (en) * | 2019-08-29 | 2019-11-26 | 电子科技大学 | A kind of lateral trench type insulated gate bipolar transistor and preparation method thereof |
| CN110504313B (en) * | 2019-08-29 | 2023-02-03 | 电子科技大学 | Transverse groove type insulated gate bipolar transistor and preparation method thereof |
| CN111785628A (en) * | 2020-06-28 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of IGBT device |
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Application publication date: 20161026 |