CN102956480A - Manufacturing method and device for reducing collector resistance through germanium-silicon HBT (Heterojunction Bipolar Transistor) with spuriously buried layer - Google Patents
Manufacturing method and device for reducing collector resistance through germanium-silicon HBT (Heterojunction Bipolar Transistor) with spuriously buried layer Download PDFInfo
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Abstract
The invention discloses a germanium-silicon HBT (Heterojunction Bipolar Transistor) device with a spuriously buried layer. The device comprises a collector region, an N-type spuriously buried layer, an intrinsic base region, an outer base region and an emitting region, wherein the collector region comprises a first N-type ion injection region formed between shallow slots, and a second N-type ion injection region formed in the first N-type ion injection region; the N-type spuriously buried layer is formed at the bottoms of the shallow slots positioned on the both sides of an active region, and metal silicide is formed on the contact parts of the N-type spuriously buried layer and the shallow slots; the intrinsic base region comprises a germanium-silicon epitaxial layer; the outer base region comprises polysilicon of the outer base region and metal silicide, the polysilicon of the outer base region is formed on the upper parts of the shallow slots and contacts the intrinsic base region, and the metal silicide is positioned on the upper part of the polysilicon of the outer base region and contacts the polysilicon of the outer base region; and the emitting region comprises N-type emitting electrode polysilicon which is formed on the upper part of the intrinsic base region and contacts the intrinsic base region. The invention also discloses a manufacturing method of the device. The germanium-silicon HBT device disclosed by the invention shortens transition time of a base region and an exhaust region formed by a junction of the base region and the collector region so as to improve the working cut-off frequency of the device, prevents generation of silicon oxides through the metal silicide with deep contact holes, and reduces the open-circuit risk of a circuit so as to improve the reliability of the device.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly a kind of manufacture method that the germanium silicium HBT reduction collector resistance of counterfeit buried regions is arranged.The invention still further relates to the device of being made by described method.
Background technology
Conventional Ge-Si heterojunction bipolar type triode requires to have high as far as possible cut-off frequency under certain puncture voltage.The major effect cut-off frequency be the transit time of base and base-depletion region that collector region knot forms.Cut-off frequency and transit time are inversely proportional to, and the transit time is proportional to width and base and the collector region resistance (being that collector base junction RC postpones) of base and collector base junction depletion region.The knot width of depletion region is directly proportional with the puncture voltage of emitter to collector electrode again.So, under identical puncture voltage, obtaining higher cut-off frequency, need base width narrower.Simultaneously, the resistance of base is less, to meet the high frequency requirement.
Under current technique, the width of base and the width of collector junction have not had too many space of improving.The resistance of base stage, emitter and collector is mainly determined by the contact resistance of contact hole (dark contact hole) and polysilicon (monocrystalline silicon).Between contact hole and polysilicon, be mingled with conventional metal silicide and can reduce greatly contact resistance (＜20 ohm/contact hole), but dark contact hole directly and shallow trench isolation under monocrystalline silicon contact so that contact resistance large (＞150 ohm/whenever deeply contact hole), affected the performance of one of radio circuit important performance indexes cut-off frequency.Simultaneously, owing to the place of opening at dark contact hole can form one deck natural oxide film, when making tack coat Ti/TiN, additionally need the wet etching machine bench of a metal silicide processing procedure to carry out the monocrystalline silicon surface cleaning, otherwise the phenomenon that very easily opens circuit.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of manufacture method that the germanium silicium HBT reduction collector resistance of counterfeit buried regions is arranged, can be used for producing the power amplifying device in high speed, the high-output power gain circuitry, can reduce collector base junction RC postpones, improve device work cut-off frequency, and the risk of reduction circuit breaker, improve device reliability; For this reason, the present invention also provides a kind of device of being made by the method.
For solving the problems of the technologies described above, the manufacture method that the germanium silicium HBT reduction collector resistance of counterfeit buried regions is arranged of the present invention comprises the steps:
In the 1st step, form shallow slot at P type silicon substrate;
In the 2nd step, inject the N-type ion in the shallow slot bottom and form the counterfeit buried regions of N-type;
In the 3rd step, carry out the N-type Implantation at active area and form collector region;
The 4th step, the epitaxial growth Ge silicon epitaxy layer;
The 5th step, the deposition dielectric film layer, etching forms emitter window, deposit emitter-polysilicon on it;
The 6th step, emitter-polysilicon is carried out the N-type Implantation, etching forms emitter, and germanium silicon outer base area polysilicon is carried out P type Implantation;
The 7th step is to the implanted dopant activation of annealing;
In the 8th step, deposition oxidation film carries out reverse etching, generates emitter-polysilicon side wall and base polysilicon side wall;
The 9th step, carry out dark contact hole photoetching, dry etching and wet etching, open the zone that needs the growing metal silicide;
In the 10th step, zone and the germanium silicon outer base area polysilicon opened at the dark contact hole in shallow slot bottom generate metal silicide, and the silicon oxide deposition medium forms contact hole, dark contact hole and metal connecting line successively.
Wherein, the formation of collector region described in the 3rd step comprises that the collector region of high speed device forms and the collector region of high tension apparatus forms, finished by twice Implantation, for the first time Implantation and the second time ion implantation technology jointly form together the collector region of high speed device; Implantation forms the collector region of high tension apparatus for the second time.Wherein the first ion implanted region in the active area adds that the second ion implanted region that is formed at active area and shallow slot edge forms to the collector region of high speed device between the shallow slot by being formed at, the collector region of high tension apparatus is comprised of the second ion implanted region that is formed at active area and shallow slot edge, and described the first ion implanted region and the second ion implanted region are N-type.
Further, media coating is silica or silicon oxynitride or silica adds silicon nitride or silicon oxynitride adds silicon nitride described in the 5th step.
Preferably, carry out high annealing between described the 2nd step and the 3rd step, temperature is at 900～1100 ℃, and annealing time is in 10～60 seconds.
Wherein, annealing temperature is at 900～1100 ℃ in the 7th step, and annealing time was at 5～100 seconds.
The device that the method that the present invention also provides the described germanium silicium HBT that counterfeit buried regions arranged to reduce collector resistance is made, active area is comprised by the isolation of shallow slot field oxygen:
One collector region is comprised of with the second ion implanted region that is formed at active area and shallow slot edge the first ion implanted region that is formed between the shallow slot, and described the first ion implanted region and the second ion implanted region are N-type;
One counterfeit buried regions, the 3rd ion implanted region bottom the shallow slot that is formed at the active area both sides forms, and described counterfeit buried regions is N-type, and counterfeit buried regions forms with collector region and is connected; Described counterfeit buried regions and shallow slot contact position are formed with metal silicide, draw the collector region electrode by the dark contact hole that the shallow slot at described metal silicide top forms;
One base, comprise an intrinsic base region and an outer base area, described intrinsic base region is comprised of the P type germanium and silicon epitaxial layer that is formed at collector region top and contacts with collector region, described outer base area comprises the outer base area polysilicon that is formed at shallow slot top and contacts with intrinsic base region, the metal silicide that is positioned at outer base area polysilicon top and is in contact with it, and draws base electrode by the contact hole that the metal silicide top forms;
One emitter region is comprised of the N-type emitter-polysilicon that is formed at intrinsic base region top, and contacts with intrinsic base region formation.
Further, the outside of described outer base area polysilicon and emitter-polysilicon is formed with side wall.
Preferably, the ion implantation dosage of the counterfeit buried regions of described N-type is 10
15～10
16Cm
-2, Implantation Energy is 50～100keV, ion is phosphorus and/or arsenic.
Preferably, described germanium and silicon epitaxial layer is divided into silicon buffer layer, germanium silicon layer and silicon cap layer, and wherein the germanium silicon layer has highly doped boron, and silicon cap layer has low-doped boron; Described silicon buffer layer is 50～300 dusts, and the germanium silicon layer is 400～800 dusts, wherein 20～200 dust boron-dopings, and doping content is 2 * 10
19～6 * 10
19Cm
-3, silicon cap layer is 100～500 dusts, doping content is 10
15～10
17Cm
-3
Preferably, the ion that injects in the described emitter-polysilicon is arsenic and/or phosphorus.
Beneficial effect of the present invention is:
1, the present invention has comprehensively adopted low-resistance counterfeit buried regions passage, the Metal-silicides Contact of contact hole and dark contact hole, and the SiGe base of highly doped boron, postpone greatly to reduce the transit time of base and base-depletion region that the collector region knot forms thereby reduced collector-base junction RC, and then improved device work cut-off frequency; Dark contact metal silicide has been avoided the generation of Si oxide, has reduced the risk of circuit breaker, improves device reliability;
2, the relative silicon cap layer location-appropriate of the highly doped germanium silicon layer of boron of the present invention, and the ion implantation dosage of emitter region polysilicon and energy-optimised and/or in conjunction with polysilicon doping in place, resulting devices is through thermal annealing diffusion and activation, can form the EB junction than low ion concns, improve the puncture voltage of finishing;
3, EB junction of the present invention has promoted the linearity of device away from emitter-window and be formed in the germanic zone; In addition, base-collector junction is formed in the germanic zone equally, has further improved the power output gain of device.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the structural representation of the germanium silicium HBT device that counterfeit buried regions is arranged of the embodiment of the invention;
Fig. 2-Fig. 4 is the device schematic cross-section in the germanium silicium HBT manufacture process that counterfeit buried regions is arranged of the embodiment of the invention.
Embodiment
As shown in Figure 1, the germanium silicium HBT that counterfeit buried regions is arranged of the embodiment of the invention reduces the device of collector resistance, and active area is shallow groove isolation layer 105 isolation among Fig. 1 by shallow slot field oxygen, comprises collector region, counterfeit buried regions, base and emitter region.
One collector region, be comprised of with the second ion implanted region 103 that is formed at active area and shallow groove isolation layer 105 edges the first ion implanted region 102 that is formed between the shallow groove isolation layer 105, described the first ion implanted region 102 and the second ion implanted region 103 are N-type.For the first time Implantation and for the second time ion implantation technology jointly form together high speed device, the implantation dosage of the first ion implanted region 102 is higher, energy is lower; Implantation forms high tension apparatus for the second time, and the implantation dosage of the second ion implanted region 103 is lower, energy is higher.
One counterfeit buried regions 104 is comprised of the 3rd ion implanted region of shallow groove isolation layer 105 bottoms that are formed at the active area both sides, and described counterfeit buried regions 104 is N-type, and counterfeit buried regions forms with collector region and is connected; Described counterfeit buried regions 104 is formed with metal silicide 107 with shallow groove isolation layer 105 contact positions, draws the collector region electrode by the profound contact hole 110 of current collection that the shallow groove isolation layer 105 at described metal silicide 107 tops forms.The doping content of described counterfeit buried regions 104 is greater than the doping content of collector region, and its ion implantation dosage is 10
15～10
16Cm
-2, Implantation Energy is 50～100keV, ion is phosphorus and/or arsenic.
One base, comprise an intrinsic base region and an outer base area, described intrinsic base region is comprised of the P type germanium and silicon epitaxial layer 113 that is formed at collector region top and contacts with collector region, described outer base area comprises the metal silicide 107 that is formed at shallow groove isolation layer 105 tops and the outer base area polysilicon 106 that contacts with intrinsic base region, is positioned at outer base area polysilicon 106 tops and is in contact with it, and draws base electrode by the base stage contact hole 111 that metal silicide 107 tops form.
Wherein, described germanium and silicon epitaxial layer is divided into silicon buffer layer, germanium silicon layer and silicon cap layer, and wherein the germanium silicon layer has highly doped boron, and silicon cap layer has low-doped boron; Described silicon buffer layer is 50～300 dusts, and the germanium silicon layer is 400～800 dusts, wherein 20～200 dust boron-dopings, and doping content is 2 * 10
19～6 * 10
19Cm
-3, silicon cap layer is 100～500 dusts, doping content is 10
15～10
17Cm
-3
One emitter region is comprised of the N-type emitter-polysilicon 114 that is formed at intrinsic base region top, and contacts with intrinsic base region formation.Position, described emitter region and size are defined by an emitter window, and the position of described emitter window and size are defined by emitter region interior media 115.The N-type ion that injects in the described emitter-polysilicon 114 is arsenic and/or phosphorus.The emitter region electrode is drawn by the emitter contact hole 112 on the emitter-polysilicon 114.
In the said structure, be formed with side wall 108 in the side of described outer base area polysilicon 106 and emitter-polysilicon 114.
Extremely shown in Figure 4 such as Fig. 2, be the device architecture schematic diagram in the embodiment of the invention manufacture process.The manufacture method of the embodiment of the invention may further comprise the steps:
In the 1st step, form shallow groove isolation layer 105 at P type silicon substrate 101;
The 2nd step was 10 at shallow groove isolation layer 105 bottom implantation dosages
15～10
16Cm
-2, energy is that the N-type ion of 50～100keV forms the counterfeit buried regions 104 of N-type, ion is phosphorus and/or arsenic;
In the 3rd step, carry out the N-type Implantation at active area and form collector region; The formation of described collector region comprises Implantation twice, and ion implantation technology is identical with the N-type collector electrode ion implantation technology of high speed device for the first time, and implantation dosage is higher, energy is lower; Ion implantation technology is identical with the N-type collector electrode ion implantation technology of high tension apparatus for the second time, and implantation dosage is lower, energy is higher;
The 4th step, at collector region top silicon oxide deposition and polysilicon layer, by doing the zone that quarter and wet etching are opened needs long monocrystalline, then the epitaxial growth Ge silicon epitaxy layer 113, described germanium and silicon epitaxial layer 113 is divided into silicon buffer layer, germanium silicon layer and silicon cap layer, wherein the germanium silicon layer has highly doped boron, and silicon cap layer has low-doped boron; Described silicon buffer layer is 50～300 dusts, and the germanium silicon layer is 400～800 dusts, wherein 20～200 dust boron-dopings, and doping content is 2 * 10
19～6 * 10
19Cm
-3, silicon cap layer is 100～500 dusts, doping content is 10
15～10
17Cm
-3
In the 5th step, deposit one media coating, described media coating are silica or silicon oxynitride or silica adds silicon nitride or silicon oxynitride adds silicon nitride, and the etching media coating forms emitter window, deposit emitter-polysilicon 114 on it; Also can be under the environment of aerobic form the oxide layer of 5～10 dusts by short annealing, depositing polysilicon again, chemical wet etching forms polycrystal emitter; Polysilicon can be non-doping, also can be that N-type in place is mixed;
The 6th step, emitter-polysilicon 114 is carried out the N-type Implantation, ion is arsenic and/or phosphorus, etching forms emitter, and germanium silicon outer base area polysilicon is carried out P type Implantation;
The 7th step, to the implanted dopant activation of annealing, annealing temperature is at 900～1100 ℃, annealing time was at 5～100 seconds, heavily doped N-type emitter-polysilicon is advanced to the shallow junction that the base forms 100～500 dusts as diffuse source, be EB junction, base and collector region activate and diffusion by thermal annealing simultaneously, form base-collector junction;
In the 8th step, deposition oxidation film carries out reverse etching, generates emitter-polysilicon side wall 108 and base polysilicon side wall 108;
The 9th step, carry out dark contact hole photoetching, dry etching and wet etching, open the zone that needs the growing metal silicide;
The 10th step generated metal silicide 107 at zone and the germanium silicon outer base area polysilicon 106 that the dark contact hole 110 in shallow groove isolation layer 105 bottoms is opened, and the silicon oxide deposition medium 109 successively, form contact hole, dark contact hole and metal connecting line.
In above-mentioned steps, carry out high annealing between described the 2nd step and the 3rd step, temperature is at 900～1100 ℃, and annealing time is in 10～60 seconds.
The present invention has comprehensively adopted low-resistance counterfeit buried regions passage, the Metal-silicides Contact of contact hole and dark contact hole, and the SiGe base of highly doped boron, postpone greatly to reduce the transit time of base and base-depletion region that the collector region knot forms thereby reduced collector-base junction RC, and then improved device work cut-off frequency; Dark contact metal silicide has been avoided the generation of Si oxide, has reduced the risk of circuit breaker, improves device reliability.
Secondly, the relative silicon cap layer location-appropriate of the highly doped germanium silicon layer of boron of the present invention, and the implantation dosage of emitter region doped polycrystalline silicon ion in place and energy-optimised, resulting devices is through thermal annealing diffusion and activation, can form the EB junction than low ion concns, improve the puncture voltage of finishing.
At last, EB junction of the present invention is away from emitter-window and be formed in the germanic zone, has promoted the linearity of device; In addition, base-collector junction is formed in the germanic zone equally, has further improved the power output gain of device.Minimum parasitic resistance of the present invention and electric capacity, direct current and the radio-frequency performance of device obtain optimization.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. the manufacture method that the germanium silicium HBT reduction collector resistance of counterfeit buried regions is arranged is characterized in that, comprises the steps:
In the 1st step, form shallow slot at P type silicon substrate;
In the 2nd step, inject the N-type ion in the shallow slot bottom and form the counterfeit buried regions of N-type;
In the 3rd step, carry out the N-type Implantation at active area and form collector region;
The 4th step, the epitaxial growth Ge silicon epitaxy layer;
The 5th step, the deposition dielectric film layer, etching forms emitter window, deposit emitter-polysilicon on it;
The 6th step, emitter-polysilicon is carried out the N-type Implantation, etching forms emitter, and germanium silicon outer base area polysilicon is carried out P type Implantation;
The 7th step is to the implanted dopant activation of annealing;
In the 8th step, deposition oxidation film carries out reverse etching, generates emitter-polysilicon side wall and base polysilicon side wall;
The 9th step, carry out dark contact hole photoetching, dry etching and wet etching, open the zone that needs the growing metal silicide;
In the 10th step, zone and the germanium silicon outer base area polysilicon opened at the dark contact hole in shallow slot bottom generate metal silicide, and the silicon oxide deposition medium forms contact hole, dark contact hole and metal connecting line successively.
2. the germanium silicium HBT that counterfeit buried regions arranged according to claim 1 reduces the manufacture method of collector resistance, it is characterized in that, the formation of collector region comprises Implantation twice described in the 3rd step, for the first time Implantation and for the second time ion implantation technology jointly form together the collector region of high speed device; Implantation forms the collector region of high tension apparatus for the second time.
3. the germanium silicium HBT that counterfeit buried regions arranged according to claim 1 reduces the manufacture method of collector resistance, it is characterized in that, media coating described in the 5th step is silica or silicon oxynitride or silica adds silicon nitride or silicon oxynitride adds silicon nitride.
4. the manufacture method that the germanium silicium HBT reduction collector resistance of counterfeit buried regions is arranged according to claim 1 is characterized in that, carry out high annealing between described the 2nd step and the 3rd step, temperature is at 900～1100 ℃, and annealing time is in 10～60 seconds.
5. the manufacture method that the germanium silicium HBT reduction collector resistance of counterfeit buried regions is arranged according to claim 1 is characterized in that annealing temperature is at 900～1100 ℃ in the 7th step, and annealing time was at 5～100 seconds.
6. the germanium silicium HBT that counterfeit buried regions arranged according to claim 1 reduces the device of the method manufacturing of collector resistance, it is characterized in that, active area is comprised by the isolation of shallow slot field oxygen:
One collector region, comprise the collector region of high speed device and the collector region of high tension apparatus, the first ion implanted region in the active area adds that the second ion implanted region that is formed at active area and shallow slot edge forms to the collector region of described high speed device between the shallow slot by being formed at, the collector region of high tension apparatus is comprised of the second ion implanted region that is formed at active area and shallow slot edge, and described the first ion implanted region and the second ion implanted region are N-type;
One counterfeit buried regions, the 3rd ion implanted region bottom the shallow slot that is formed at the active area both sides forms, and described counterfeit buried regions is N-type, and counterfeit buried regions forms with collector region and is connected; Described counterfeit buried regions and shallow slot contact position are formed with metal silicide, draw the collector region electrode by the dark contact hole that the shallow slot at described metal silicide top forms;
One base, comprise an intrinsic base region and an outer base area, described intrinsic base region is comprised of the P type germanium and silicon epitaxial layer that is formed at collector region top and contacts with collector region, described outer base area comprises the outer base area polysilicon that is formed at shallow slot top and contacts with intrinsic base region, the metal silicide that is positioned at outer base area polysilicon top and is in contact with it, and draws base electrode by the contact hole that the metal silicide top forms;
One emitter region is comprised of the N-type emitter-polysilicon that is formed at intrinsic base region top, and contacts with intrinsic base region formation.
7. the germanium silicium HBT that counterfeit buried regions arranged according to claim 6 reduces the device of the method manufacturing of collector resistance, it is characterized in that the outside of described outer base area polysilicon and emitter-polysilicon is formed with side wall.
8. the germanium silicium HBT that counterfeit buried regions arranged according to claim 6 reduces the device of the method manufacturing of collector resistance, it is characterized in that the ion implantation dosage of the counterfeit buried regions of described N-type is 10
15～10
16m
-2, Implantation Energy is 50～100keV, ion is phosphorus and/or arsenic.
9. the germanium silicium HBT that counterfeit buried regions arranged according to claim 6 reduces the device of the method manufacturing of collector resistance, it is characterized in that, described germanium and silicon epitaxial layer is divided into silicon buffer layer, germanium silicon layer and silicon cap layer, and wherein the germanium silicon layer has highly doped boron, and silicon cap layer has low-doped boron; Described silicon buffer layer is 50～300 dusts, and the germanium silicon layer is 400～800 dusts, wherein 20～200 dust boron-dopings, and doping content is 2 * 10
19～6 * 10
19Cm
-3, silicon cap layer is 100～500 dusts, doping content is 10
15～10
17Cm
-3
10. the germanium silicium HBT that counterfeit buried regions arranged according to claim 6 reduces the device of the method manufacturing of collector resistance, it is characterized in that the ion that injects in the described emitter-polysilicon is arsenic and/or phosphorus.
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