CN102403343B - Vertical parasitic PNP device in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method - Google Patents

Vertical parasitic PNP device in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method Download PDF

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CN102403343B
CN102403343B CN 201010275455 CN201010275455A CN102403343B CN 102403343 B CN102403343 B CN 102403343B CN 201010275455 CN201010275455 CN 201010275455 CN 201010275455 A CN201010275455 A CN 201010275455A CN 102403343 B CN102403343 B CN 102403343B
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dielectric layer
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CN102403343A (en
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刘冬华
钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a vertical parasitic PNP device in the BiCMOS (bipolar complementary metal oxide semiconductor) process, which comprises a collector region, a base region, an emitter region, a buried layer and N-shaped polycrystalline silicon. The collector region is formed in a first active region, the buried layer is formed at the bottom of shallow trench field oxides on two sides of the collector region and transversely extends to enter the first active region and contact with the collector region, the collector region is connected with an adjacent second active region and an adjacent third active region through the buried layer, and collectors are led out by metallic contacts formed at the tops of the second active region and the third active region. The N-shaped polycrystalline silicon is formed on the upper portion of the base region and contacts with the base region, and bases are led out by metallic contacts formed on the N-shaped polycrystalline silicon. The invention further discloses a manufacturing method for the vertical parasitic PNP device in the BiCMOS process. The vertical parasitic PNP device can be used as an output device in a high-speed and high-gain BiCMOS circuit so as to provide one more choice for the circuit, and the resistance of the collectors can be decreased and the performance of the devices is improved without increasing the area of the device.

Description

Vertical parastic PNP device and manufacture method in the BiCMOS technology
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to the vertical parastic PNP device in a kind of BiCMOS technology, the invention still further relates to the manufacture method of the vertical parastic PNP device in this BiCMOS technology.
Background technology
In radio frequency applications, need more and more higher device feature frequency.In the BiCMOS technology, NPN triode, particularly Ge-Si heterojunction triode (SiGe) or germanium silicon-carbon heterojunction triode (SiGeC HBT) then are the fine selections of hyperfrequency device.And SiGe technology is compatible mutually with silicon technology substantially, so SiGe HBT has become one of main flow of hyperfrequency device.Under this background, its requirement to output device also correspondingly improves, such as having certain current gain coefficient and cut-off frequency.
Output device can adopt the parasitic PNP triode of vertical-type in the prior art, and the common elder generation of drawing of the collector electrode of the vertical parastic PNP device in the existing BiCMOS technology is contacted by a collector region that is formed at buried regions that shallow-trench isolation (STI) is oxygen bottom, shallow slot field or trap and device and collector region is drawn out in another active area adjacent with collector region, draws collector electrode by form Metal Contact in this another active area.Such way is that the vertical stratification characteristics by its device are determined.Its shortcoming is that device area is big, and the connection resistance of collector electrode is big.Since collector electrode of the prior art draw will by another active area adjacent with collector region realize and this another active area and collector region between need to isolate with STI or other oxygen, so limited further dwindling of device size greatly.
Summary of the invention
Technical problem to be solved by this invention provides the vertical parastic PNP device in a kind of BiCMOS technology, can be as the output device in high speed, the high-gain BiCMOS circuit, select for circuit provides many a kind of devices, can be under the situation that does not increase device area, reduce the PNP pipe collector resistance, improve the performance of device; The present invention also provides the manufacture method of the vertical parastic PNP device in this BiCMOS technology, and process conditions that need not be extra can reduce production costs.
For solving the problems of the technologies described above, the vertical parastic PNP device in the BiCMOS technology provided by the invention is formed on the silicon substrate, and active area is isolated by shallow slot field oxygen, and wherein said active area comprises a plurality of, and described vertical parastic PNP device comprises:
One collector region, in each described active area, be formed with P type ion implanted region, the P type ion implanted region degree of depth of each described active area is more than or equal to the bottom degree of depth of described shallow slot field oxygen and interconnect, and described collector region is made up of a P type ion implanted region that is formed in first active area.The implanted dopant of the P type ion implanted region of each described active area is a boron, and inject in two steps and realize: first step implantation dosage is 1e11cm -2～5e13cm -2, the injection energy is 100keV～300keV; The second step implantation dosage is 5e11cm -2～1e13cm -2, the injection energy is 30keV～100keV.
One counterfeit buried regions is made up of the P type ion implanted region of the oxygen bottom, described shallow slot field that is formed at described collector region both sides, and described counterfeit buried regions horizontal expansion enters described first active area and contacts with described collector region formation.Described counterfeit buried regions also horizontal expansion enter in second active area and the 3rd active area and and described second active area contact with P type ion implanted region formation in the 3rd active area.Described second active area and the 3rd active area are to be positioned at also there is described shallow slot field oxygen the described first active area both sides with described first active area isolation described active area.By drawing collector electrode at described second active area and the 3rd active area top formation Metal Contact.The process conditions that the P type ion of described counterfeit buried regions injects are: implantation dosage is 1e14cm -2～1e16cm -2, energy is for being boron or boron difluoride less than 15keV, implanted dopant.Also be formed with P type heavily doped region in described second active area and the 3rd active area, the Metal Contact of described P type heavily doped region and described collector electrode forms ohmic contact.
One base is by being formed at described collector region top and forming with the contacted N type ion implanted region of described collector region.The process conditions that the N type ion of described base injects are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e12cm -2～1e14cm -2
Emitter by being formed at top, described base and forming with the contacted P type germanium and silicon epitaxial layer in described base, is directly drawn by a Metal Contact in one emitter region.The size of described emitter region is less than the size of described active area, the size of described emitter region is defined by the base window that forms on first dielectric layer, described first dielectric layer is formed on the described silicon substrate, described first dielectric layer of part that is positioned at described first active area top of described silicon substrate by etched portions forms described base window, and described base window is positioned on described first active area and less than described first active area.The P type germanium and silicon epitaxial layer of described emitter region adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 5e14cm -2～5e15cm -2, energy is for being boron or boron difluoride less than 10keV, implanted dopant.
One N type polysilicon, described N type polysilicon are formed at top, described base and contact with described base, draw base stage by do Metal Contact on described N type polysilicon.Described N type polysilicon is isolated by second dielectric layer and described emitter region.Described N type polysilicon adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 1e14cm -2～1e16cm -2, energy is that 150keV～200keV, implanted dopant are arsenic or phosphorus.
For solving the problems of the technologies described above, the manufacture method of the vertical parastic PNP device in the BiCMOS technology provided by the invention comprises the steps:
Step 1, employing etching technics are formed with source region and shallow trench on silicon substrate.Etching technics adopts the silicon nitride hardmask, and the formation method of described silicon nitride hardmask is removed, described silicon nitride hardmask only is covered on each described surfaces of active regions of described silicon substrate for the described silicon nitride that at first will form the zone of described shallow trench by chemical wet etching technology at growth one silicon nitride layer on the described silicon substrate, again.
Step 2, carry out N type ion at first active area and inject to form the base.The degree of depth of described base is less than the bottom degree of depth of described shallow trench.It is to pass described silicon nitride hardmask to be injected into described first active area that the N type ion of described base injects, and the process conditions that the N type ion of described base injects are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e12cm -2～1e14cm -2
Step 3, carry out P type ion in described shallow trench bottom and inject and form counterfeit buried regions.The process conditions that the P type ion of described counterfeit buried regions injects are: implantation dosage is 1e14cm -2～1e16cm -2, energy is for being boron or boron difluoride less than 15keV, implanted dopant.
Step 4, carry out annealing process, described counterfeit buried regions is horizontal and vertical to be diffused in described first active area, second active area and the 3rd active area, and described second active area and the 3rd active area are to be positioned at also there is described shallow trench the described first active area both sides with described first active area isolation described active area.The process conditions of described annealing are: temperature is 900 ℃～1100 ℃, and the time is 10 minutes～100 minutes.
Step 5, in described shallow trench, insert silica and form shallow slot field oxygen;
Step 6, in each described active area, carry out the P type ion implanted region that P type ion inject to form each described active area, the degree of depth of the P type ion implanted region of each described active area forms more than or equal to the bottom degree of depth of described shallow slot field oxygen and with described counterfeit buried regions and contacts, and the P type ion implanted region of described first active area is formed collector region.The P type ion of each described active area injects and adopts existing C MOSP trap injection technology, and implanted dopant is a boron, and inject in two steps and realize: first step implantation dosage is 1e11cm -2～5e13cm -2, the injection energy is 100keV～300keV; The second step implantation dosage is 5e11cm -2～1e13cm -2, the injection energy is 30keV～100keV.
Step 7, formation emitter region form by growth one P type germanium and silicon epitaxial layer and etching above described first active area, and the size of described emitter region contacts less than described first active area and with described base.Described P type germanium and silicon epitaxial layer adopts the germanium and silicon epitaxial layer process of SiGe HBT to form and injects with the heavy doping P type of the extrinsic base region of SiGeHBT and mixes, and the ion implantation technology of described P type germanium and silicon epitaxial layer is that the process conditions of heavy doping P type injection of the extrinsic base region of SiGe HBT are: implantation dosage is 5e14cm -2～5e15cm -2, energy is for being boron or boron difluoride less than 10keV, implanted dopant.The position of described emitter region and size define by the base window that one first dielectric layer forms, and comprise step: form described first dielectric layer on described silicon substrate; Described first dielectric layer of part that etching is positioned at described first active area top forms described base window, and described base window is positioned on described first active area and less than described first active area; Growth one P type germanium and silicon epitaxial layer and etching form described emitter region on the described base window of described silicon substrate and described first dielectric layer, be formed at the interior described P type germanium and silicon epitaxial layer of described base window and contact with the formation of described base, the size that is formed at the outer described P type germanium and silicon epitaxial layer of described base window is passed through described first dielectric layer isolation less than described first active area and with described base.
Step 8, form N type polysilicon on top, described base, described N type polysilicon and described base contact.Comprise the steps: on described silicon substrate, to form second dielectric layer when forming described N type polysilicon; Described second dielectric layer of etching makes described second dielectric layer wrap described emitter region and the regional size that is less than described first active area of parcel, and extra-regional described second dielectric layer of described parcel is all removed; The described N type of deposit polysilicon contacts described N type polysilicon and described base and isolated by described second dielectric layer and described emitter region.Described N type polysilicon adopts the emitter-polysilicon technology of SiGeHBT to form, and adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 1e14cm -2～1e16cm -2, energy is that 150keV～200keV, implanted dopant are arsenic or phosphorus.
Step 9, form Metal Contact at described second active area and the 3rd active area top and draw collector electrode; The Metal Contact that forms the base is drawn base stage; The Metal Contact that forms the emitter region is drawn emitter.Wherein, also be included in the step that forms P type heavily doped region in described second active area and the 3rd active area before the Metal Contact that forms described collector electrode, described P type heavily doped region doping content satisfies the requirement that forms ohmic contact with the Metal Contact of described collector electrode.
Vertical parastic PNP device in the BiCMOS technology of the present invention has bigger current amplification factor and frequency characteristic preferably, can as at a high speed, output device in the high-gain BiCMOS circuit, select for circuit provides many a kind of devices; Device of the present invention is drawn collector electrode by adopting the advanced counterfeit buried regions of heavy doping P type, can effectively reduce the resistance of the collector electrode of device, the frequency characteristic that can improve device and keep the input characteristics of device and current gain unaffected simultaneously under the situation of the area that does not increase device.Manufacture method of the present invention adopts existing BiCMOS process conditions, can reduce production costs.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of the vertical parastic PNP device in the embodiment of the invention BiCMOS technology;
Fig. 2 A-Fig. 2 G is the structural representation of vertical parastic PNP device in manufacture process in the BiCMOS technology of the embodiment of the invention;
Fig. 3 A is the input characteristic curve of the vertical parastic PNP device in the BiCMOS technology of the embodiment of the invention of TCAD simulation;
Fig. 3 B is the gain curve of the vertical parastic PNP device in the BiCMOS technology of the embodiment of the invention of TCAD simulation.
Embodiment
As shown in Figure 1, it is the structural representation of the vertical parastic PNP device in the embodiment of the invention BiCMOS technology, vertical parastic PNP device in the embodiment of the invention BiCMOS technology, be formed on the silicon substrate 1, active area is isolated by shallow slot field oxygen 3, wherein said active area comprises a plurality of, and described vertical parastic PNP device comprises:
One collector region, in each described active area, be formed with P type ion implanted region 7, P type ion implanted region 7 degree of depth of each described active area are more than or equal to the bottom degree of depth of described shallow slot field oxygen 3 and interconnect, and described collector region is made up of a P type ion implanted region 7 that is formed in first active area.The implanted dopant of the P type ion implanted region 7 of each described active area is a boron, and inject in two steps and realize: first step implantation dosage is 1e11cm -2～5e13cm -2, the injection energy is 100keV～300keV; The second step implantation dosage is 5e11cm -2～1e13cm -2, the injection energy is 30keV～100keV.
One counterfeit buried regions 6 is made up of the P type ion implanted region of oxygen 3 bottoms, described shallow slot field that are formed at described collector region both sides, and described counterfeit buried regions 6 horizontal expansions enter described first active area and contact with described collector region formation.Described counterfeit buried regions 6 also horizontal expansion enter in second active area and the 3rd active area and and described second active area contact with P type ion implanted region 7 formation in the 3rd active area.Described second active area and the 3rd active area are to be positioned at also there is described shallow slot field oxygen 3 the described first active area both sides with described first active area isolation described active area.By drawing collector electrode at described second active area and the 3rd active area top formation Metal Contact 13.The process conditions that the P type ion of described counterfeit buried regions 6 injects are: implantation dosage is 1e14cm -2～1e16cm -2, energy is for being boron or boron difluoride less than 15keV, implanted dopant.Also be formed with P type heavily doped region 12 in described second active area and the 3rd active area, the Metal Contact 13 of described P type heavily doped region 12 and described collector electrode forms ohmic contact.
One base 5 is by being formed at described collector region top and forming with the contacted N type ion implanted region of described collector region.The process conditions that the N type ion of described base 5 injects are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e12cm -2～1e14cm -2
Emitter by being formed at 5 tops, described base and forming with described base 5 contacted P type germanium and silicon epitaxial layers, is directly drawn by a Metal Contact 13 in one emitter region 9.The size of described emitter region 9 is less than the size of described active area, the size of described emitter region is defined by the base window that forms on first dielectric layer 8, described first dielectric layer 8 is formed on the described silicon substrate 1, described first dielectric layer 8 of part that is positioned at described first active area top of described silicon substrate 1 by etched portions forms described base window, and described base window is positioned on described first active area and less than described first active area.The P type germanium and silicon epitaxial layer of described emitter region 9 adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 5e14cm -2～5e15cm -2, energy is for being boron or boron difluoride less than 10keV, implanted dopant.
One N type polysilicon 11, described N type polysilicon 11 are formed at 5 tops, described base and contact with described base 5, draw base stage by do Metal Contact 13 on described N type polysilicon 11.Described N type polysilicon 11 is isolated by second dielectric layer 10 and described emitter region 9.Described N type polysilicon 11 adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 1e14cm -2～1e16cm -2, energy is that 150keV～200keV, implanted dopant are arsenic or phosphorus.
Shown in Fig. 2 A-Fig. 2 G, be the structural representation of vertical parastic PNP device in manufacture process in the BiCMOS technology of the embodiment of the invention, the manufacture method of the vertical parastic PNP device in the BiCMOS technology of the embodiment of the invention comprises following processing step:
Step 1, shown in Fig. 2 A, adopt etching technics on silicon substrate 1, to be formed with source region and shallow trench 3a.Etching technics adopts silicon nitride hardmask 4, and the formation method of described silicon nitride hardmask 4 is removed, 4 of described silicon nitride hardmasks are covered on each described surfaces of active regions of described silicon substrate 1 for the described silicon nitride layer that at first will form the zone of described shallow trench 3a by chemical wet etching technology at growth one silicon nitride layer on the described silicon substrate 1, again.The thickness of wherein said silicon nitride hardmask 4 is 300 dusts～800 dusts.
Step 2, shown in Fig. 2 B, carry out N type ion at first active area and inject to form base 5.The degree of depth of described base 5 is less than the bottom degree of depth of described shallow trench 3a.It is to pass described silicon nitride hardmask 4 to be injected into described first active area that the N type ion of described base 5 injects, and the process conditions that the N type ion of described base 5 injects are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e12cm -2～1e14cm -2
Step 3, shown in Fig. 2 C, carry out P type ion in described shallow trench 3a bottom and inject and form counterfeit buried regions 6.The process conditions that the P type ion of described counterfeit buried regions 6 injects are: implantation dosage is 1e14cm -2～1e16cm -2, energy is for being boron or boron difluoride less than 15keV, implanted dopant.
Step 4, shown in Fig. 2 D, carry out annealing process, described counterfeit buried regions 6 horizontal and vertical diffusing in described first active area, second active area and the 3rd active area, described second active area and the 3rd active area are to be positioned at also there is described shallow trench 3a the described first active area both sides with described first active area isolation described active area.The process conditions of described annealing are: temperature is 900 ℃～1100 ℃, and the time is 10 minutes～100 minutes.
Step 5, shown in Fig. 2 E, remove described silicon nitride hardmask 4 and in described shallow trench 3a, insert silica and form shallow slot field oxygen 3.
Step 6, shown in Fig. 2 E, in each described active area, carry out P type ion and inject the P type ion implanted region 7 that forms each described active area, the degree of depth of the P type ion implanted region 7 of each described active area forms more than or equal to the bottom degree of depth of described shallow slot field oxygen 3 and with described counterfeit buried regions 6 and contacts, and the P type ion implanted region 7 of described first active area is formed collector region.The P type ion of each described active area injects and adopts existing C MOSP trap injection technology, and implanted dopant is a boron, and inject in two steps and realize: first step implantation dosage is 1e11cm -2～5e13cm -2, the injection energy is 100keV～300keV; The second step implantation dosage is 5e11cm -2～1e13cm -2, the injection energy is 30keV～100keV.
Step 7, shown in Fig. 2 F, form emitter region 9, form by growth one P type germanium and silicon epitaxial layer and etching above described first active area, the size of described emitter region 9 less than described first active area and and described base 5 contact.Described P type germanium and silicon epitaxial layer adopts the germanium and silicon epitaxial layer process of SiGe HBT to form and adopts the heavy doping P type injection of the extrinsic base region of SiGe HBT to mix, and the ion implantation technology of described P type germanium and silicon epitaxial layer is that the process conditions that the heavy doping P type of the extrinsic base region of SiGe HBT injects are: implantation dosage is 5e14cm -2～5e15cm -2, energy is for being boron or boron difluoride less than 10keV, implanted dopant.The position of described emitter region 9 and size define by the base window that one first dielectric layer 8 forms, and comprise step: form described first dielectric layer 8 on described silicon substrate 1; Described first dielectric layer 8 of part that etching is positioned at described first active area top forms described base window, and described base window is positioned on described first active area and less than described first active area; Growth one P type germanium and silicon epitaxial layer and etching form described emitter region 9 on the described base window of described silicon substrate 1 and described first dielectric layer 8, be formed at the interior described P type germanium and silicon epitaxial layer of described base window and contact with the formation of described base, the size that is formed at the outer described P type germanium and silicon epitaxial layer of described base window is passed through described first dielectric layer isolation less than described first active area and with described base.
Step 8, shown in Fig. 2 F, Fig. 2 G, form N type polysilicon 11 on 5 tops, described base, described N type polysilicon 11 and described base 5 contact.Comprise the steps: when forming described N type polysilicon 11 to form second dielectric layer 10 on described silicon substrate 1, described second dielectric layer 10 can add silicon nitride for silica, silicon nitride or silica; Described second dielectric layer 10 of etching makes described second dielectric layer 10 wrap described emitter region 9 and the regional size that is less than described first active area of parcel, and extra-regional described second dielectric layer 10 of described parcel is all removed; Described second dielectric layer 10 and the described N type polysilicon 11 at the described N type of deposit polysilicon 11 and 9 tops, the described emitter region of etching make described N type polysilicon 11 and described base 5 contacts and isolated by described second dielectric layer 10 and described emitter region 9.Described N type polysilicon 11 adopts the emitter-polysilicon technology of SiGe HBT to form, and adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 1e14cm -2～1e16cm -2, energy is that 150keV～200keV, implanted dopant are arsenic or phosphorus.
Step 9, as shown in Figure 1 forms Metal Contact 13 at described second active area and the 3rd active area top and draws collector electrode; The Metal Contact 13 that forms base 5 is drawn base stage; The Metal Contact 13 that forms emitter region 9 is drawn emitter.Wherein, also be included in the step that forms P type heavily doped region 12 in described second active area and the 3rd active area before the Metal Contact that forms described collector electrode, described P type heavily doped region 12 doping contents satisfy the requirement that forms ohmic contact with the Metal Contact of described collector electrode.
Shown in Fig. 3 A and 3B, be respectively the input characteristic curve and the gain curve of the vertical parastic PNP device in the BiCMOS technology of the embodiment of the invention of TCAD simulation.Therefrom as can be seen,, can under the situation of the area that does not increase device, reduce the resistance of collector electrode effectively, thereby help and the frequency characteristic that improves device owing to adopted the advanced counterfeit buried regions of heavy doping P type to draw collector electrode.And other characteristics, such as input characteristics and current gain, but can be not influenced, current gain can remain on more than 20.
Shown in Fig. 3 A and 3B, be respectively the input characteristic curve and the gain curve of the vertical parastic PNP device in the BiCMOS technology of the embodiment of the invention of TCAD simulation.Therefrom as can be seen, owing to adopted advanced deep hole contact process directly to contact with the counterfeit buried regions of P type, draw the collector electrode of this device, the area of device has compared with prior art effectively reduced.And because extraction location adds the highly doped counterfeit buried regions of P type to the distance shortening of collector region, the resistance of collector electrode also reduces thereupon effectively, thereby helps and the frequency characteristic that improves device.And other characteristics, such as input characteristics and current gain, but can be not influenced, current gain can remain on more than 20.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (16)

1. the vertical parastic PNP device in the BiCMOS technology is formed on the silicon substrate, and active area is isolated by shallow slot field oxygen, it is characterized in that described vertical parastic PNP device comprises:
One collector region, in each described active area, be formed with P type ion implanted region, the P type ion implanted region degree of depth of each described active area is more than or equal to the bottom degree of depth of described shallow slot field oxygen and interconnect, and described collector region is made up of a P type ion implanted region that is formed in first active area;
One counterfeit buried regions is made up of the P type ion implanted region of the oxygen bottom, described shallow slot field that is formed at described collector region both sides, and described counterfeit buried regions horizontal expansion enters described first active area and contacts with described collector region formation; Described counterfeit buried regions also horizontal expansion enter in second active area and the 3rd active area and and described second active area form with P type ion implanted region in the 3rd active area and contact, described second active area and the 3rd active area are to be positioned at also there is described shallow slot field oxygen the described first active area both sides with described first active area isolation described active area; By drawing collector electrode at described second active area and the 3rd active area top formation Metal Contact;
One base is by being formed at described collector region top and forming with the contacted N type ion implanted region of described collector region;
Emitter by being formed at top, described base and forming with the contacted P type germanium and silicon epitaxial layer in described base, is directly drawn by a Metal Contact in one emitter region;
One N type polysilicon, described N type polysilicon are formed at top, described base and contact with described base, draw base stage by do Metal Contact on described N type polysilicon;
The size of described emitter region is less than the size of described active area, the size of described emitter region is defined by the base window that forms on first dielectric layer, described first dielectric layer is formed on the described silicon substrate, described first dielectric layer of part that is positioned at described first active area top of described silicon substrate by etched portions forms described base window, and described base window is positioned on described first active area and less than described first active area;
Described N type polysilicon is isolated by second dielectric layer and described emitter region.
2. the vertical parastic PNP device in the BiCMOS technology as claimed in claim 1 is characterized in that: the implanted dopant of the P type ion implanted region of each described active area is a boron, and inject in two steps and realize: first step implantation dosage is 1e11cm -2～5e13cm -2, the injection energy is 100keV～300keV; The second step implantation dosage is 5e11cm -2～1e13cm -2, the injection energy is 30keV～100keV.
3. the vertical parastic PNP device in the BiCMOS technology as claimed in claim 1 is characterized in that: the process conditions that the P type ion of described counterfeit buried regions injects are: implantation dosage is 1e14cm -2～1e16cm -2, energy is for being boron or boron difluoride less than 15keV, implanted dopant.
4. the vertical parastic PNP device in the BiCMOS technology as claimed in claim 1 is characterized in that: the process conditions that the N type ion of described base injects are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e12cm -2～1e14cm -2
5. the vertical parastic PNP device in the BiCMOS technology as claimed in claim 1 is characterized in that: the P type germanium and silicon epitaxial layer of described emitter region adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 5e14cm -2～5e15cm -2, energy is for being boron or boron difluoride less than 10keV, implanted dopant.
6. the vertical parastic PNP device in the BiCMOS technology as claimed in claim 1 is characterized in that: described N type polysilicon adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 1e14cm -2～1e16cm -2, energy is that 150keV～200keV, implanted dopant are arsenic or phosphorus.
7. the vertical parastic PNP device in the BiCMOS technology as claimed in claim 1, it is characterized in that: also be formed with P type heavily doped region in described second active area and the 3rd active area, the Metal Contact of described P type heavily doped region and described collector electrode forms ohmic contact.
8. the manufacture method of the vertical parastic PNP device in the BiCMOS technology is characterized in that, comprises the steps:
Step 1, employing etching technics are formed with source region and shallow trench on silicon substrate;
Step 2, carry out N type ion at first active area and inject to form the base; The degree of depth of described base is less than the bottom degree of depth of described shallow trench;
Step 3, carry out P type ion in described shallow trench bottom and inject and form counterfeit buried regions;
Step 4, carry out annealing process, described counterfeit buried regions is horizontal and vertical to be diffused in described first active area, second active area and the 3rd active area, and described second active area and the 3rd active area are to be positioned at also there is described shallow trench the described first active area both sides with described first active area isolation described active area;
Step 5, in described shallow trench, insert silica and form shallow slot field oxygen;
Step 6, in each described active area, carry out the P type ion implanted region that P type ion inject to form each described active area, the degree of depth of the P type ion implanted region of each described active area forms more than or equal to the bottom degree of depth of described shallow slot field oxygen and with described counterfeit buried regions and contacts, and the P type ion implanted region of described first active area is formed collector region;
Step 7, formation emitter region form by growth one P type germanium and silicon epitaxial layer and etching above described first active area, and the size of described emitter region contacts less than described first active area and with described base;
Step 8, form N type polysilicon on top, described base, described N type polysilicon and described base contact;
Step 9, form Metal Contact at described second active area and the 3rd active area top and draw collector electrode; The Metal Contact that forms the base is drawn base stage; The Metal Contact that forms the emitter region is drawn emitter.
9. method as claimed in claim 8, it is characterized in that: the etching technics in the step 1 adopts the silicon nitride hardmask, described silicon nitride hardmask is formed on each described surfaces of active regions of described silicon substrate, it is to pass described silicon nitride hardmask to be injected into described first active area that the N type ion of the described base in the step 2 injects, and the process conditions that the N type ion of described base injects are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e12cm -2～1e14cm -2
10. method as claimed in claim 8 is characterized in that: the process conditions that the P type ion of counterfeit buried regions described in the step 3 injects are: implantation dosage is 1e14cm -2～1e16cm -2, energy is for being boron or boron difluoride less than 15keV, implanted dopant.
11. method as claimed in claim 8 is characterized in that: the process conditions of the annealing in the step 4 are: temperature is 900 ℃～1100 ℃, and the time is 10 minutes～100 minutes.
12. method as claimed in claim 8 is characterized in that: the implanted dopant that the P type ion of each described active area injects in the step 6 is a boron, and inject in two steps and realize: first step implantation dosage is 1e11cm -2～5e13cm -2, the injection energy is 100keV～300keV; The second step implantation dosage is 5e11cm -2～1e13cm -2, the injection energy is 30keV～100keV.
13. method as claimed in claim 8 is characterized in that: the position of the described emitter region in the step 7 and size define by the base window that one first dielectric layer forms, and comprise step: form described first dielectric layer on described silicon substrate; Described first dielectric layer of part that etching is positioned at described first active area top forms described base window, and described base window is positioned on described first active area and less than described first active area; Growth one P type germanium and silicon epitaxial layer and etching form described emitter region on the described base window of described silicon substrate and described first dielectric layer, be formed at the interior described P type germanium and silicon epitaxial layer of described base window and contact with the formation of described base, the size that is formed at the outer described P type germanium and silicon epitaxial layer of described base window is passed through described first dielectric layer isolation less than described first active area and with described base; The P type germanium and silicon epitaxial layer of described emitter region adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 5e14cm -2～5e15cm -2, energy is for being boron or boron difluoride less than 10keV, implanted dopant.
14. method as claimed in claim 8 is characterized in that: comprise the steps: on described silicon substrate, to form second dielectric layer when forming described N type polysilicon in the step 8; Described second dielectric layer of etching makes described second dielectric layer wrap described emitter region and the regional size that is less than described first active area of parcel, and extra-regional described second dielectric layer of described parcel is all removed; The described N type of deposit polysilicon contacts described N type polysilicon and described base and isolated by described second dielectric layer and described emitter region.
15. as claim 8 or 14 described methods, it is characterized in that: described N type polysilicon adopts ion implantation technology to mix, and the doping process condition is: implantation dosage is 1e14cm -2～1e16cm -2, energy is that 150keV～200keV, implanted dopant are arsenic or phosphorus.
16. method as claimed in claim 8, it is characterized in that: also be included in the step that forms P type heavily doped region in described second active area and the 3rd active area in the step 9, described P type heavily doped region doping content satisfies the requirement that forms ohmic contact with the Metal Contact of described collector electrode.
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