JPH10223785A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance high frequency characteristics of a bipolar transistor by making a trench in a buried insulator and an N<-> type silicon substrate and filling the trench with an isolation insulator thereby suppressing generation of latch-up and decreasing the isolation area. SOLUTION: An NPN bipolar transistor 51, a PNP bipolar transistor, an N-channel MOS transistor 53 and a P-channel MOS transistor 54 are formed on semiconductor substrate 1 isolated by a buried insulating film 31 and an element isolation isolating film 33. This structure blocks formation of parasitic NPN and PNP bipolar transistors and suppresses generation of latch-up. Furthermore, isolation area can be decrease by making a trench 32 in an N<-> type silicon substrate 32 and filling the trench with the isolation isolating film 33. Junction capacity being formed parasitically at the collector part can also be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having both a bipolar transistor and a transistor of a complementary field effect (CMOS) structure and a method of manufacturing the same, and more particularly, to a semiconductor device formed on an insulating film and It relates to the manufacturing method.

[0002]

2. Description of the Related Art FIG. 7 is a cross-sectional view showing a cross-sectional structure of a semiconductor device (hereinafter, referred to as BiCMOS) including a bipolar transistor and a complementary field effect transistor according to the prior art. The structure of a conventional BiCMOS semiconductor device and its manufacturing method will be described below with reference to FIG.

As shown in FIG. 7, a P ⁺ type buried diffusion layer 3 and a P ⁻ type diffusion layer 5 are composed of an NPN bipolar transistor 51, a PNP bipolar transistor 52, an N channel MOS transistor 53 and a P channel MOS transistor.
It is a diffusion layer for separating the transistor 54 from the transistor.

The N ⁺ type buried diffusion layer 2 is a diffusion layer for reducing the collector resistance of the NPN bipolar transistor and suppressing the current amplification factor of the PNP bipolar transistor. The N ⁺ type diffusion layers 10 and 11 and the N ⁺⁺ type diffusion layers 15 and 16 are N-channel MOS type transistors 5.
3 is a diffusion layer serving as a source and a drain.

Further, the P ⁺ type diffusion layers 12 and 13 and P
^{The ++-} type diffusion layers 17 and 18 are diffusion layers serving as a source and a drain of the P-channel MOS transistor 54.

Next, a manufacturing method for forming a BiCMOS type integrated circuit according to the prior art will be described with reference to the sectional view of FIG. A P ⁺ type buried diffusion layer 3 is formed by ion implantation and thermal diffusion in a region where a junction isolation layer with the N-channel MOS transistor 53 of the P-type semiconductor substrate 1 is to be formed.

Further, an NPN bipolar transistor 5
An N ⁺ -type buried diffusion layer 2 is formed by ion implantation and thermal diffusion in a region where a PNP bipolar transistor 1, a PNP bipolar transistor 52 and a P-channel MOS transistor 54 are to be formed.

Next, epitaxial growth is performed at a temperature of 1200 ° C. using silicon tetrachloride (SiCl ₄ ) and phosphine (PH ₃ ) as source gases to form an N ⁻ -type epitaxial layer 4.

Next, in the region where the N-channel MOS transistor 53 and the junction isolation layer are formed, the P ⁻ type diffusion layer 5 is formed.
Is formed by an ion implantation method and a thermal diffusion method.

Next, a P ⁺ diffusion layer 6 for preventing inversion of the field portion is formed on the surface of the P ^- type diffusion layer 5.

Next, in order to insulate and separate the P ⁻ type diffusion layer 5 and the N ⁻ type epitaxial layer 4, an oxidation resistant film is used as an antioxidant film, and an oxide film is formed in a region where the oxidation resistant film is not formed. The silicon oxide film 9 is formed by a so-called selective oxidation (LOCOS) method.

Thereafter, a P ⁺ type diffusion layer 7 serving as a base of the NPN bipolar transistor and a collector and an emitter of the PNP bipolar transistor is formed by an ion implantation method and a thermal diffusion method.

Further, a gate oxidation process, formation of polysilicon, and patterning of the polysilicon are performed to form gate electrodes 8 and 27.

After that, an N ⁺ type diffusion layer 10 is
Then, P ⁺ -type diffusion layers 12 and 13 are formed on the source and drain of the P-channel transistor 54 by ion implantation and thermal diffusion. As a result, a low impurity concentration region and a high impurity concentration region were formed in the drain region.
A so-called lightly doped drain (hereinafter referred to as LDD) layer.

Thereafter, a PSG film made of a silicon oxide film containing phosphorus is formed, and an etch-back process is performed to form a sidewall 14 while leaving the PSG film only on the gate side wall.

After that, the emitter and collector of the NPN bipolar transistor 51 and the source and drain of the N-channel MOS transistor 53 are connected to the N ⁺⁺ type diffusion layer 1.
5, 16, 20 and 21 are formed, and P ⁺⁺ type diffusion layers 17 and 18 are formed at the source and drain of the P-channel MOS transistor 54 by ion implantation and thermal diffusion.

Thereafter, an intermediate insulating film 19 is formed on the entire surface,
Thereafter, the intermediate insulating film 19 is opened, and a wiring material is further formed, so that the source electrodes 23, 24, the drain electrodes 25, 2
6, an emitter electrode 28, a base electrode 29, and a collector electrode 30 are formed.

[0018]

In the prior art BiCMOS type integrated circuit described with reference to FIG.
A parasitic NPN bipolar transistor formed of the N ⁺⁺ -type diffusion layer 16, the P ⁻ -type diffusion layer 5, and the N ⁻ -type epitaxial layer 4, the P ⁺⁺ -type diffusion layer 18, the N ⁻ -type epitaxial layer 4, and P ⁻ Thus, a parasitic PNP bipolar transistor formed with the mold diffusion layer 5 is formed. The parasitic NPN bipolar transistor and the parasitic PNP bipolar transistor have a disadvantage that they have a so-called thyristor structure and cause latch-up.

Furthermore, the N ⁺⁺ type diffusion layer 15 and the P ⁺ -type diffusion layer 7 N ^- and NPN bipolar transistor formed by the type epitaxial layer 4, the P ⁺ -type diffusion layer 7 and the N ^- epitaxial layer 4 Parasitic P formed with P ⁻ type diffusion layer 5
There is a disadvantage that the NP bipolar transistor has a thyristor structure and causes latch-up.

Furthermore, in the conventional BiCMOS type integrated circuit, the NPN bipolar transistor 51 and the P
NP bipolar transistor 52 and N-channel MO
In order to separate the S-type transistor 53 from the P-channel MOS type transistor 54, an isolation region is formed by the P ⁺ -type buried diffusion layer 3 and the P ^-- type diffusion layer 5. Since this isolation region is formed by lateral diffusion of impurities, there is a disadvantage that the isolation area increases.

The N ⁺ type buried diffusion layer 2 and the N ⁻ type epitaxial layer 4 form the collector of an NPN type bipolar transistor. The junction capacitance formed by the semiconductor substrate 1, the P ⁺ type buried diffusion layer 3 and the P ⁻ type diffusion layer 5 is connected to this collector. For this reason, there is a disadvantage that the gain bandwidth product f _T of the NPN bipolar transistor is not improved.

An object of the present invention is to eliminate the above-mentioned drawbacks, thereby suppressing the occurrence of latch-up, reducing the separation area, and improving the high-frequency characteristics of a bipolar transistor and its semiconductor device. It is to provide a manufacturing method.

[0023]

To achieve the above object, a semiconductor device and a method of manufacturing the same according to the present invention employ the following means.

The semiconductor device according to the present invention comprises an NPN bipolar transistor, a PNP bipolar transistor and an NPN bipolar transistor.
Channel MOS type transistor and P channel MOS
NPN bipolar transistor and PNP bipolar transistor are separated by a buried insulating film and an isolation insulating film on a semiconductor substrate, and have an N ⁺⁺ type diffusion layer at an interface with the buried insulating film. An N-channel MOS transistor is provided on an N ^- type silicon substrate, is separated by a buried insulating film on a semiconductor substrate and an insulating film for element isolation, and has an N ⁺⁺ type diffusion layer at an interface with the buried insulating film. ^- P on type silicon substrate ^- provided -type diffusion layer, P-channel MOS transistor are isolated by the buried insulating film and the isolation insulating film on the semiconductor substrate, N ⁺⁺ type in the interface between the buried insulating film The N-channel MOS transistor is provided on an N ^- type diffusion layer on an N ^- type substrate having a diffusion layer, and the N-channel MOS transistor has N
Having a ⁺ type diffusion layer, an N ⁺⁺ type diffusion layer and a sidewall,
The P-channel MOS transistor has a P ⁺ -type diffusion layer serving as a source and a drain, a P ⁺⁺ -type diffusion layer, and a sidewall, and has an NPN bipolar transistor, a PNP bipolar transistor, an N-channel MOS transistor, and a P-channel MOS. The type transistor is characterized in that it is separated by a buried insulating film and an insulating film for element isolation.

A semiconductor device according to the present invention comprises an NPN bipolar transistor, a PNP bipolar transistor and an NPN bipolar transistor.
Channel MOS type transistor and P channel MOS
NPN bipolar transistor and PNP bipolar transistor are separated by a buried insulating film and an isolation insulating film on a semiconductor substrate, and have an N ⁺⁺ type diffusion layer at an interface with the buried insulating film. An N-channel MOS transistor is provided on an N ^- type silicon substrate, is separated by a buried insulating film on a semiconductor substrate and an insulating film for element isolation, and has an N ⁺⁺ type diffusion layer at an interface with the buried insulating film. ^- P on type silicon substrate ^- provided -type diffusion layer, P-channel MOS transistor are isolated by the buried insulating film and the isolation insulating film on the semiconductor substrate, N ⁺⁺ type in the interface between the buried insulating film An NPN bipolar transistor and a PN are provided on an N ⁻ type diffusion layer on a N ⁻ type silicon substrate on a semiconductor substrate having a diffusion layer.
P bipolar transistor, N channel MOS transistor and P channel MOS transistor
It is characterized by being separated by a buried insulating film and an insulating film for element isolation.

According to a method of manufacturing a semiconductor device of the present invention, an NPN bipolar transistor on a semiconductor substrate separated by a buried insulating film on a semiconductor substrate and having an N ⁺⁺ type diffusion layer at an interface with the buried insulating film is provided. PNP bipolar transistor and N
Channel MOS type transistor and P channel MOS
Forming a trench in a region separating the transistor and embedding an insulating film for element isolation, and forming a P ⁻ -type diffusion layer and an N ⁻ -type diffusion layer in the semiconductor substrate having the N ⁺⁺ type diffusion layer. , NPN bipolar transistor base and PN
Forming a P ⁺ -type diffusion layer serving as an emitter and a collector of the P-type bipolar transistor; forming a gate oxide film and a gate electrode; and forming an N ⁺ -type diffusion layer and a P ⁺ -type diffusion layer in a region where the gate electrode matches. Forming a sidewall on the side wall of the gate electrode, and diffusing N ⁺⁺ diffusion into a region where the gate electrode of the N-channel MOS transistor is aligned with the sidewall and a region serving as an emitter of the NPN bipolar transistor. Forming a P ⁺⁺ diffusion layer in a region where the gate electrode of the P-channel MOS transistor is aligned with the sidewall;
Forming an intermediate insulating film, opening the intermediate insulating film, and forming an emitter electrode, a base electrode, a collector electrode, a source electrode, and a drain electrode.

According to a method of manufacturing a semiconductor device of the present invention, an NPN bipolar transistor on a semiconductor substrate separated by a buried insulating film on a semiconductor substrate and having an N ⁺⁺ type diffusion layer at an interface with the buried insulating film is provided. PNP bipolar transistor and N
Channel MOS type transistor and P channel MOS
Forming a trench in a region separating the transistor and embedding an insulating film for element isolation, and forming a P ⁻ -type diffusion layer and an N ⁻ -type diffusion layer in the semiconductor substrate having the N ⁺⁺ type diffusion layer. Forming an N ⁺⁺ type diffusion layer in a region to be an emitter of an NPN bipolar transistor, and forming a P ⁺⁺ region in a region matching a gate electrode of a P-channel MOS transistor.
Forming a ⁺⁺ type diffusion layer, and forming an intermediate insulating film, opening the intermediate insulating film, and forming an emitter electrode, a base electrode, a collector electrode, a source electrode, and a drain electrode. Features.

[Operation] In the present invention, an NPN bipolar transistor, a PNP bipolar transistor, an N-channel MOS transistor, and a P-channel MOS transistor are formed on a semiconductor substrate separated by a buried insulating film and an element separating insulating film. Form.

By employing such a structure of the present invention and a method of manufacturing the same, an N ⁺⁺ type diffusion layer forming the source / drain of an N channel MOS type transistor, a P ⁻ type diffusion layer serving as a P well, and N ⁻ type diffusion layer. P -type epitaxial layer and the P-well ^{- -} parasitic NPN bipolar transistor formed by the type epitaxial layer, P ⁺⁺ type diffusion layer and the N to form a source drain of the P-channel MOS transistor and diffusion layers Will not form a thyristor structure. As a result, in the semiconductor device including the BiCMOS of the present invention, latch-up can be suppressed.

Further, in the conventional device isolation using the P ⁻ type diffusion layer and the P ⁺ type buried diffusion layer, there is a lateral diffusion of about 0.8 times the diffusion depth, and the element isolation width becomes wide. was there. However, when the semiconductor structure of the present invention is employed to perform element isolation by the element isolation insulating film, the element isolation width can be reduced to about one fifth of the conventional technique. Therefore, in the semiconductor device of the present invention, the element isolation area can be reduced.

The high-frequency characteristics of the bipolar transistor are represented by a gain bandwidth product f _T , which is the carrier depletion layer charging time of the carrier, the base transit time, the collector depletion layer transit time, and the collector charging time. Is known to be inversely proportional to the sum of

The collector charging time is the product of the sum of the series resistance of the collector, the junction capacitance between the base and the collector, and the junction capacitance parasitically formed in the collector due to element isolation. In the device structure and the method of manufacturing the same according to the present invention, the parasitic capacitance formed in the collector can be reduced. Thus, the gain bandwidth product f _T can be improved.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below with reference to FIGS. FIG. 5 is a sectional view showing the structure of the semiconductor device according to the embodiment of the present invention.

[Structure of Semiconductor Device: FIG. 5] As shown in FIG. 5, an NPN bipolar transistor 51 is composed of an N ⁻ type silicon substrate separated by a semiconductor substrate 1 and a buried insulating film 31 on the semiconductor substrate 1. comprising a base consisting of P ⁺ -type diffusion layer 7 provided on 32, the emitter consisting of N ⁺⁺ type diffusion layer 20, and a collector consisting of N ⁺⁺ type diffusion layer 21.

The PNP bipolar transistor 52 has a collector and an emitter composed of a semiconductor substrate 1 and a P ⁺ -type diffusion layer 7 provided on an N ⁻ -type silicon substrate 32 separated by a buried insulating film 31 on the semiconductor substrate 1. And a base made of the N ⁺⁺ type diffusion layer 22.

Further, the N-channel MOS transistor 53 is formed on an N ⁻ type silicon substrate 32 having a semiconductor substrate 1 and an N ⁺ type buried diffusion layer 2 separated by a buried insulating film 31 on the semiconductor substrate 1. P ^- type diffusion layer 5 to be provided
, A gate electrode 8 made of polysilicon provided on an N ⁻ type silicon substrate 32 and a gate oxide film, and an N ⁺ type diffusion layer 10.
A source consisting of N ⁺⁺ type diffusion layer 16 and, N ⁺ -type diffusion layer 1
1 and an N ⁺⁺ type diffusion layer 15.

Further, the P-channel MOS transistor 54 has a gate and an N ⁻ type silicon substrate 32 having a semiconductor substrate 1 and an N ⁺ type buried diffusion layer 2 separated by a buried insulating film 31 on the semiconductor substrate 1. Gate electrode 27 made of polysilicon provided on oxide film and P ⁺ type diffusion layer 13
Provided with a source comprising a P ⁺⁺ type diffusion layer 18., and a drain consisting of P ⁺ -type diffusion layer 12 and P ⁺⁺ type diffusion layer 17.

As shown in FIG. 5, the element isolation means which is a feature of the present invention is to provide a buried insulating film 31 and a groove in an N ^- type silicon substrate 32, and to form an element isolating insulating film 33 in the groove. Embedding.

The buried insulating film 31 and the isolation insulating film 33 shown in FIG. 5 have a structure for suppressing latch-up due to the parasitic NPN bipolar transistor and the parasitic PNP bipolar transistor.

Further, the structure in which a groove is dug in the N ⁻ type silicon substrate 32 and the element isolation insulating film 33 is buried is used in order to reduce the element isolation width to about one-fifth of the element isolation method using a conventional PN junction. The structure is as follows.

Further, the buried insulating film 31 and the element isolating insulating film 33 are used to reduce the junction capacitance parasitically formed in the collector portion and to improve the gain bandwidth product f _T of the NPN bipolar transistor. The structure is as follows.

[Method of Manufacturing Semiconductor Device: FIGS. 1 to 5] Next, a method of manufacturing the above-described structure will be described. First, as shown in FIG. 1, a silicon oxide film having a thickness of 0.5 μm is formed on a semiconductor substrate 1 by steam oxidation to form a buried insulating film 31. Then, N with N ⁺ -type buried diffusion layer ^- polishing the surface of -type silicon substrate 32, N ^{- -} by bonding type silicon substrate 32, N was performed 5 hours heat treatment at a temperature 1200 ° C. -type silicon substrate 3μ thickness
A bonded wafer having a value of m is prepared.

A photosensitive resin having a thickness of 0.93 μm is formed on an N ⁻ type silicon substrate 32 having a silicon active layer having a thickness of 3 μm by a spin coating method. Thereafter, an exposure process and a development process are performed using a predetermined mask for the purpose of separating the NPN bipolar transistor 51, the PNP bipolar transistor 52, the N-channel MOS transistor 53, and the P-channel MOS transistor 54. In this way, the photosensitive resin is supplied to the NPN bipolar transistor 51 and the PNP bipolar transistor 5.
Patterning is performed so as to remain in the formation regions of the N-channel MOS type transistor 53 and the P-channel MOS type transistor 54.

Thereafter, using this photosensitive resin as an etching mask, the N ^- type silicon substrate 32 is treated with hydrogen bromide (HB
Etching is performed by a reactive ion etching apparatus using r) and chlorine (Cl ₂ ) as an etching gas to form a groove for burying the element isolation insulating film 33 shown in FIG. After that, the photosensitive resin used as the etching mask is removed.

Next, at a temperature of 1000 in a dry oxygen atmosphere.
A silicon oxide film having a thickness of 40 nm is formed on the N ⁻ -type silicon substrate 32 by performing a heat treatment at a temperature of ° C.

Next, as shown in FIG. 3, in order to form the insulating film 33 for element isolation, normal pressure using monosilane (SiH ₄ ), oxygen (O ₂ ), and phosphine (PH ₃ ) as a source gas is used. A 200 nm-thick PSG film, which is a silicon oxide film containing phosphorus, is formed over the entire surface by a chemical vapor deposition method.

Further, monosilane (SiH ₄ ), oxygen (O ₂ ), diborane (B ₂ H ₆ ) and phosphine (P
H ₃ ) as a source gas by a normal pressure chemical vapor deposition method to form a silicon oxide film B containing phosphorus and boron.
An element isolation insulating film 33 made of a PSG film is formed on the entire surface of the N ⁻ type silicon substrate 32 by the thickness thereof. This BPSG film is deposited to make the surface flat by a subsequent heat treatment.

Next, a heat treatment at a temperature of 900 ° C. is performed for 30 minutes in a nitrogen atmosphere to flatten the surface of the isolation insulating film 33.

Then, the PSG film and the BPSG film are etched back by a reactive ion etching apparatus using Freon 32 (CH ₂ F ₂ ) and Freon 23 (CHF ₃ ) as an etching gas, and an insulating film for element isolation is formed. 33 N ^-
It is formed inside the groove formed in the mold silicon substrate.

Next, the silicon oxide film on the surface of the N ^- silicon substrate 32 is removed using an etching solution consisting of water: hydrofluoric acid = 10: 1.

After that, in an oxygen atmosphere containing water vapor at a temperature of 1
A heat treatment at 000 ° C. is performed to form a 550 nm-thick silicon oxide film (not shown) used as an ion implantation blocking film.

Further, a photosensitive resin having a thickness of 0.93 μm is formed on the entire surface by a spin coating method, and is exposed using a predetermined photomask for the purpose of forming the P ⁻ -type diffusion layer 5.
The photosensitive resin is patterned by performing a developing process.

After that, using this photosensitive resin as an etching mask, the silicon oxide film is patterned by using an etching solution of water: hydrofluoric acid = 10: 1 to form P ⁻
A hole is formed in the region where the mold diffusion layer 5 is formed. After that, the photosensitive resin used as the etching mask is removed.

Next, at a temperature of 1000 in a dry oxygen atmosphere.
A heat treatment at a temperature of ° C. is performed to grow an 81 nm-thick silicon oxide film (not shown) as a buffer film at the time of ion implantation in a region where the P ⁻ type diffusion layer 5 is to be formed.

After that, boron as a P-type impurity was added at an acceleration energy of 60 KeV and an ion implantation amount of 1.2 ×.
Under the ion implantation condition of 10 ¹³ atoms / cm ^2, the impurity is introduced into the region where the P ⁻ -type diffusion layer 5 is formed.

Thereafter, heat treatment is performed at a temperature of 1140 ° C. for 2 hours to form a P ⁻ type diffusion layer 5 having a depth of 2 μm.

Next, in order to form the P ⁺ type diffusion layer 7, a photosensitive resin having a thickness of 0.93 μm is formed on the entire surface by a spin coating method, and exposed and developed using a predetermined photomask. And the NPN bipolar transistor 5
The first base forming region, the emitter forming region and the collector forming region of the PNP bipolar transistor 52 are opened.

After that, using this photosensitive resin as a blocking film for ion implantation, boron is used as a P-type impurity by an ion implantation method, and an acceleration energy of 60 KeV is applied.
And implanted into the N ⁻ type silicon substrate 32 under the conditions of 5 × 10 ¹² atoms / cm ² .

Thereafter, the photosensitive resin is removed, and a heat treatment is performed at a temperature of 1140 ° C. for 60 minutes in a nitrogen atmosphere to form a P ⁺ type diffusion layer 7.

Thereafter, a heat treatment at a temperature of 1000 ° C. is performed for 24 minutes in an oxygen atmosphere to form a gate oxide film made of a silicon oxide film having a thickness of 20 nm.

Next, as shown in FIG.
A 350 nm-thick polycrystalline silicon film is formed on the entire surface by a chemical vapor deposition method using iH ₄ ) as a source gas.

Thereafter, a photosensitive resin having a thickness of 1.1 μm is formed on the entire surface of the polycrystalline silicon film by spin coating.
Exposure processing and development processing are performed using a predetermined photomask, and patterning is performed so that the photosensitive resin remains in the formation regions of the gate electrodes 8 and 27.

Using the patterned photosensitive resin as an etching mask, the polycrystalline silicon is etched by a reactive ion etching apparatus using sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) as an etching gas. Then, the gate electrodes 8 and 27 shown in FIG. 4 are formed.

Next, in order to form the P ⁺ type diffusion layers 12 and 13, a photosensitive resin having a thickness of 0.93 μm is formed on the entire surface by a spin coating method, and exposed and developed using a predetermined photomask. The process is performed, and the region of the N-channel MOS transistor 53 and the NPN bipolar transistor 5
The pattern is formed so that the photosensitive resin remains in the region 1 and the region of the PNP bipolar transistor 52.

Then, using this photosensitive resin as an ion implantation blocking film, boron difluoride (BF ₂ ) as a P-type impurity is ion-implanted to an acceleration energy of 25 KeV, 3.0 × Under the condition of 10 ¹³ atoms / cm ² , implantation is performed on an N ⁻ -type silicon substrate 32 matching the gate electrode 27.

Thereafter, the photosensitive resin used for the ion implantation blocking film is removed. Further, in order to form the N ⁺ -type diffusion layers 10 and 11, a photosensitive resin having a thickness of 0.93 μm is formed on the entire surface, and exposure and development are performed using a predetermined photomask to form a P-channel MOS. Type transistor 54
Is formed so that the photosensitive resin is left in the region of the NPN bipolar transistor 51 and the region of the PNP bipolar transistor 52.

The patterned photosensitive resin is used as a blocking film for ion implantation, phosphorus is used as an N-type impurity at an acceleration energy of 25 KeV, and an ion implantation amount is 1.0 × 10 ¹³ atoms / cm ² . Is implanted into the P ⁻ type diffusion layer 5 that matches the gate electrode 8.

Next, as shown in FIG. 4, in order to form the sidewall 14, a chemical vapor at normal pressure using monosilane (SiH ₄ ), oxygen (O ₂ ), and phosphine (PH ₃ ) as source gases. PS with a thickness of 300 nm by the growth method
A G film is formed on the entire surface.

Then, the PSG film is etched back by a reactive ion etching apparatus using Freon 32 (CH ₂ F ₂ ) and Freon 23 (CHF ₃ ) as an etching gas, and the side walls of the gate electrodes 8 and 27 are formed. The sidewall 14 is formed.

Next, in order to form the P ⁺⁺ type diffusion layers 17 and 18 of FIG. 4, a photosensitive resin having a thickness of 0.93 μm is formed on the entire surface by a spin coating method, and a predetermined photomask is used. Exposure processing and development processing are performed, and a pattern is formed so that the photosensitive resin remains in the region of the N-channel MOS transistor 53.

The patterned photosensitive resin is used as an ion implantation blocking film, and boron difluoride (BF ₂ ) is used as a P-type impurity at an acceleration energy of 30 KeV and an implantation amount of 3.0. × 10 ¹⁵ atoms / c
Under an ion implantation condition of m ² , implantation is performed on an N ⁻ -type silicon substrate 32 where the gate electrode 27 and the sidewall 14 match.

Similarly, in order to form the N ⁺⁺ type diffusion layers 15 and 16, a photosensitive resin having a thickness of 0.93 μm is formed on the entire surface by a spin coating method, and an exposure process is performed using a predetermined photomask. A development process is performed to form a pattern so that the photosensitive resin remains in the region of the P-channel MOS transistor 54.

The patterned photosensitive resin is used as an ion implantation blocking film, arsenic is used as an N type impurity, the acceleration energy is 60 KeV, and the ion implantation amount is 3.0 × 10 ¹⁵ atoms / cm 2. Under the ion implantation condition of cm ² , implantation is performed on the P ⁻ type diffusion layer 5 where the gate electrode 8 and the sidewall 14 match.

By the above manufacturing steps, the N-channel MO
In the S-type transistor 53, the N ⁺ -type diffusion layers 10, 11 and N
The source and drain having the LDD structure can be formed by the ⁺⁺ type diffusion layers 15 and 16. Further, in the P-channel MOS transistor 54, the P ⁺ type diffusion layer 1
Sources and drains having an LDD structure can be formed by the layers 2 and 13 and the P ⁺⁺ type diffusion layers 17 and 18.

Next, as shown in FIG. 5, monosilane (S
A silicon oxide film containing phosphorus and boron by a normal pressure chemical vapor deposition method using iH ₄ ), oxygen (O ₂ ), diborane (B ₂ H 6), and phosphine (PH ₃ ) as source gases. A 550 nm-thick intermediate insulating film 19 made of a BPSG film is formed on the entire surface.

Next, a heat treatment at a temperature of 900 ° C. is performed for 30 minutes in a nitrogen atmosphere to flatten the surface of the intermediate insulating film 19.

Then, a film thickness of 1.1 μm is formed by spin coating.
Is formed on the entire surface, and an exposure process and a development process are performed using a predetermined photomask, and the photosensitive resin is patterned so as to open contact holes.

Next, using the patterned photoresist as an etching mask, CFC 32 (CH ₂ F ₂ )
The intermediate insulating film 19 is etched and opened by a reactive ion etching apparatus using chlorofluorocarbon and chlorofluorocarbon 23 (CHF ₃ ) as an etching gas to form a contact hole. After that, the photosensitive resin used as the etching mask is removed.

Next, an alloy film made of aluminum (Al), silicon (Si) and copper (Cu) is formed as a metal for wiring to a thickness of 1 μm on the entire surface by a sputtering method.

Further, a photoresist is formed on the entire surface by a spin coating method, exposure and development are performed using a predetermined photomask, and patterning is performed so that the photoresist is formed in a wiring formation region.

Next, using a patterned photoresist as an etching mask, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), and hydrogen bromide (HBr) are used as etching gases, and a reactive ion etching apparatus is used. Then, the alloy film is etched to form the source electrodes 21 and 22 and the drain electrodes 23 and 24, which are metal for wiring, in a pattern.

In the embodiment of the present invention manufactured as described above, an NPN bipolar transistor, a PNP bipolar transistor, an N-channel MOS transistor and a P-channel MOS transistor are formed on a semiconductor substrate on an insulating film.

In the BiCMOS integrated circuit shown in FIG. 5, the formation of the parasitic NPN bipolar transistor and the parasitic PNP bipolar transistor is prevented by separating the buried insulating film and the isolation insulating film, thereby preventing the occurrence of latch-up. This is a structure for suppressing. In addition, this is a structure for reducing an isolation area by digging a groove in an N ^- type silicon substrate and embedding an element isolation insulating film.

Further, the collector current and the gain bandwidth product f _T
As shown in the graph of FIG. 6 showing the relationship between, the buried insulating film and the isolation insulating film to reduce the junction capacitance parasitically formed in the collector unit, for increasing the gain-bandwidth product f _T For the structure.

[0085]

As is apparent from the above description, in the BiCMOS type semiconductor device of the present invention, the NPN bipolar transistor, the PNP bipolar transistor, the N channel MOS transistor and the P channel M
An OS transistor is formed over a semiconductor substrate over an insulating film.

As a result, it is possible to suppress the occurrence of latch-up, to further reduce the separation area, and to improve the gain bandwidth product of the bipolar transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

Is a diagram showing a comparison with the characteristics of the gain-bandwidth product f _T and the collector current of the semiconductor device, and a characteristic of the gain-bandwidth product f _T and the collector current in the prior art in the embodiment of the invention; FIG .

FIG. 7 is a cross-sectional view showing a structure of a semiconductor device and a method of manufacturing the same in a conventional technique.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 N ⁺ -type buried diffusion layer 3 P ⁺ -type buried diffusion layer 4 N ⁻ -type epitaxial layer 5 P ⁻ -type diffusion layer 6 P ^{+ -type} diffusion layer 7 P ⁺ -type diffusion layer 8 Gate electrode 9 Silicon oxide film 10 N ⁺ type diffusion layer 11 N ⁺ type diffusion layer 12 P ⁺ type diffusion layer 13 P ⁺ type diffusion layer 14 Side wall 15 N ⁺⁺ type diffusion layer 16 N ⁺⁺ type diffusion layer 17 P ⁺⁺ type diffusion layer 18 P ^{+ +} Type diffusion layer 19 intermediate insulating film 20 N ⁺⁺ type diffusion layer 21 N ⁺⁺ type diffusion layer 22 N ⁺⁺ type diffusion layer 23 source electrode 24 source electrode 25 drain electrode 26 drain electrode 27 gate electrode 28 emitter electrode 29 base electrode 30 collector electrode 31 embedded insulating film 32 N ^- -type silicon substrate 33 for element isolation insulating film 51 NPN bipolar transistor 52 PNP bipolar transistor 53 N-channel MOS-type transistor 54 P-channel MOS transistor

Claims (4)

[Claims] 1. An NPN bipolar transistor and a PN
The semiconductor device includes a P-type bipolar transistor, an N-channel MOS type transistor, and a P-channel MOS type transistor. The NPN bipolar type transistor and the PNP bipolar type transistor are separated by a buried insulating film and a device separating insulating film on a semiconductor substrate. Provided on an N ^- type silicon substrate having an N ⁺⁺ type diffusion layer at the interface with the insulating film, the N-channel MOS transistor is separated by a buried insulating film on the semiconductor substrate and an insulating film for element isolation, and the buried insulating Provided in a P ^- type diffusion layer on an N ^- type silicon substrate having an N ⁺⁺ type diffusion layer at the interface with the film, and a P-channel MOS transistor is separated by a buried insulating film on the semiconductor substrate and an isolation insulating film. is, N having N ⁺⁺ type diffusion layer at the interface between the buried insulating film ^- -type substrate of N ^- provided -type diffusion layer, N-channel MOS transistor is a source, de Has an in-become N ⁺ -type diffusion layer and the N ⁺⁺ type diffusion layer and the sidewall, and the P-channel MOS transistor source, drain and becomes P ⁺ -type diffusion layer and the P ⁺⁺ type diffusion layer and the side wall NPN bipolar transistor, PNP bipolar transistor, N-channel MOS transistor and P
A semiconductor device, wherein a channel MOS transistor is separated by a buried insulating film and an element separating insulating film. 2. An NPN bipolar transistor and a PN
The semiconductor device includes a P-type bipolar transistor, an N-channel MOS type transistor, and a P-channel MOS type transistor. Provided on an N ^- type silicon substrate having an N ⁺⁺ type diffusion layer at the interface with the insulating film, the N-channel MOS transistor is separated by a buried insulating film on the semiconductor substrate and an insulating film for element isolation, and the buried insulating Provided on a P ^- type diffusion layer on an N ^- type silicon substrate having an N ⁺⁺ type diffusion layer at the interface with the film. is, N on a semiconductor substrate having an N ⁺⁺ type diffusion layer at the interface between the buried insulating film ^- N on type silicon substrate ^- provided -type diffusion layer, NPN bipolar tiger Register and PNP bipolar transistor and N-channel MOS transistor and the P
A semiconductor device, wherein a channel MOS transistor is separated by a buried insulating film and an isolation insulating film. 3. An NPN bipolar transistor, a PNP bipolar transistor, and an N-channel MOS type transistor on a semiconductor substrate which is separated by a buried insulating film of the semiconductor substrate and has an N ⁺⁺ type diffusion layer at an interface with the buried insulating film. burying a transistor and a P-channel MOS transistor and the element isolation insulating film digging a trench in a region for separating a semiconductor substrate having an N ⁺⁺ type diffusion layer P ^- -type diffusion layer and the N ^-
Forming a p-type diffusion layer; and P ^{+ serving as} a base of an NPN bipolar transistor and an emitter and a collector of the PNP bipolar transistor.
Forming a gate diffusion film, forming a gate oxide film and a gate electrode, and forming an N ⁺ type diffusion layer and a P ⁺ type diffusion layer in a region where the gate electrode is aligned; Forming an N ⁺⁺ type diffusion layer in a region where the gate electrode of the N-channel MOS transistor is aligned with the side wall and in a region serving as an emitter of the NPN bipolar transistor; A step of forming a P ⁺⁺ type diffusion layer in a region where the gate electrode and the sidewall are aligned; forming an intermediate insulating film, opening the intermediate insulating film, and forming an emitter electrode, a base electrode, a collector electrode, a source electrode, Forming a drain electrode. 4. An NPN bipolar transistor, a PNP bipolar transistor, and an N-channel MOS type transistor on a semiconductor substrate separated by a buried insulating film of a semiconductor substrate and having an N ⁺⁺ type diffusion layer at an interface with the buried insulating film. burying a transistor and a P-channel MOS transistor and the element isolation insulating film digging a trench in a region for separating a semiconductor substrate having an N ⁺⁺ type diffusion layer P ^- -type diffusion layer and the N ^-
Forming an N ⁺⁺ type diffusion layer in a region to be an emitter of an NPN bipolar transistor; and forming a P ⁺⁺ type diffusion in a region matching a gate electrode of a P channel MOS transistor. A semiconductor, comprising: forming a layer; forming an intermediate insulating film; opening the intermediate insulating film; and forming an emitter electrode, a base electrode, a collector electrode, a source electrode, and a drain electrode. Device manufacturing method.