JPS6167274A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6167274A JPS6167274A JP18811584A JP18811584A JPS6167274A JP S6167274 A JPS6167274 A JP S6167274A JP 18811584 A JP18811584 A JP 18811584A JP 18811584 A JP18811584 A JP 18811584A JP S6167274 A JPS6167274 A JP S6167274A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- substrate
- films
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 19
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 11
- 239000000377 silicon dioxide Substances 0.000 abstract description 11
- 239000012212 insulator Substances 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 239000000243 solution Substances 0.000 abstract description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 239000007853 buffer solution Substances 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 239000012808 vapor phase Substances 0.000 abstract description 2
- 229910000927 Ge alloy Inorganic materials 0.000 abstract 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 31
- 230000005669 field effect Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000000502 dialysis Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- -1 gold-aluminum Chemical compound 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は超高周波増幅回路などに用いられる半導体装置
の製造方法に関するもので、ある。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device used in an ultra-high frequency amplifier circuit or the like.
（従来列の構成とその問題点）
近年超高局波を用いた通信電送が盛んに行なわれ、家庭
のテレビジョンもＵＨＦやＳＨＦの電波を受信するよう
になってきた。それに伴い微弱な超周波の電波を低雑音
で増幅する素子として砒化ガリウムショットキーダート
電界効果トランジスタ（以下ＧａＡｓ ＭＥＳＦＥＴと
略す）が多く使われるようになってきた。第１図は従来
のＧａＡｓ ＭＥＳＦＥＴの製造工程を示すものである
。同図において１は比抵抗の高い半絶縁性砒化ガリウム
基板、２は半絶縁性砒化ガリウム基板１上に設けたｎ型
砒化ガリウム層、３はｎ型砒化ガリウム層２とオーミッ
ク接触となる金属、４はｎ型砒化ガリウム層２とショッ
トキー接触となる金属、５は金属３および金属４を形成
するために用いられるフォトレノストである。(Conventional array configuration and its problems) In recent years, communication transmission using ultra-high frequency waves has become popular, and home televisions have come to receive UHF and SHF radio waves. Along with this, gallium arsenide Schottky dart field effect transistors (hereinafter abbreviated as GaAs MESFETs) have come to be widely used as elements for amplifying weak ultra-frequency radio waves with low noise. FIG. 1 shows the manufacturing process of a conventional GaAs MESFET. In the figure, 1 is a semi-insulating gallium arsenide substrate with high resistivity, 2 is an n-type gallium arsenide layer provided on the semi-insulating gallium arsenide substrate 1, and 3 is a metal that makes ohmic contact with the n-type gallium arsenide layer 2. 4 is a metal that makes Schottky contact with the n-type gallium arsenide layer 2, and 5 is a photorenost used to form metal 3 and metal 4.
以上のように構成されたＧａＡｓ ＭＥＳＦＥＴの製造
工程について説明する。The manufacturing process of the GaAs MESFET configured as above will be explained.
まず半絶縁性砒化ガリウム基板１上にエビタキ／ヤル成
長させたｎ型砒化ガリウム層２に７オトレノスト膜５を
塗布し、第１図（ａ）に示すようにソース・ト°レイン
電極となる領域を／’Ｐターニングする。つぎに第１図
（ｂ）に示すように砒化ガリウム層２とオーミック接触
となる金属３を基板１全面に真空蒸着し、レジスト剥離
液中に浸漬すれば、フォトレノストは溶解しフォトレジ
スト膜の金属３も同時に除去され、第１図（ｃ）に示す
ように７オトレノストのない部分だけ金属３が残る。つ
ぎに再びフォトレノストを塗布し、第１図（ｄ）に示す
ように金属３にはさまれた部分にフォトレノストを開孔
する。同じようにｎ型砒化ガリウム層２とショットキー
接触となる金属４を基板全面に蒸着しく第１図（ｅ））
レノスト剥離液中に浸漬すれば、第１図（ｆ）に示すよ
うに金属６が２つの金属３の間に形成される。これによ
って２つの金属３をソース電極およびドレイン電極、金
属６をケ゛−ト電極とするＧａＡａ ＭＥＳＦＥＴが完
成する。First, a 7-Otrenost film 5 is applied to an n-type gallium arsenide layer 2 grown by epitaxy/dialysis on a semi-insulating gallium arsenide substrate 1, and as shown in FIG. Turn /'P. Next, as shown in FIG. 1(b), a metal 3 that makes ohmic contact with the gallium arsenide layer 2 is vacuum-deposited on the entire surface of the substrate 1, and is immersed in a resist stripping solution, so that the photorenost is dissolved and the metal of the photoresist film is 3 is also removed at the same time, and as shown in FIG. 1(c), metal 3 remains only in the area where 7 othrenost is not present. Next, photorenost is applied again, and holes are made with photorenost in the portions sandwiched between the metal parts 3, as shown in FIG. 1(d). Similarly, a metal 4 that forms Schottky contact with the n-type gallium arsenide layer 2 is deposited on the entire surface of the substrate (Fig. 1(e)).
When immersed in the Lenost stripping solution, a metal 6 is formed between the two metals 3 as shown in FIG. 1(f). As a result, a GaAa MESFET is completed in which the two metals 3 are used as the source and drain electrodes, and the metal 6 is used as the gate electrode.
このＧａＡｓ ＭＥＳＦＥＴの性能はダート電極６の形
状に大きく依存し、素子の低雑音化やスイッチング時間
の短縮にはダート容量を減らすためケ゛−ト長を短縮し
ながらダート抵抗を上げないようにするためダート金属
の厚さを厚くする必要がある。The performance of this GaAs MESFET largely depends on the shape of the dart electrode 6, and in order to reduce the noise of the device and shorten the switching time, it is necessary to reduce the dart capacitance and shorten the gate length while not increasing the dart resistance. It is necessary to increase the thickness of the dart metal.
しかし、上記のような従来の製造方法では光露光法の場
合ケ゛−ト長は１ミクロンが限界であシ、１ミクロン以
下のｒ−）長をうるには電子ビーム露光法など特殊な手
段を必要とする。またｙ−ト金属の高さはレジスト以上
高くすることはできず、たとえダート長を短縮してもダ
ート抵抗が増大し、必ずしもよい結果は得られていなか
った。したがって簡単な方法で１ミクロン以下のダート
長でかつダート抵抗の低いダート電極形成法の開発が望
まれていた。However, in the conventional manufacturing method described above, the gate length is limited to 1 micron using light exposure, and special means such as electron beam exposure are required to obtain an r-) length of less than 1 micron. I need. Further, the height of the Y-t metal cannot be made higher than the resist, and even if the dart length is shortened, the dart resistance increases, and good results have not always been obtained. Therefore, it has been desired to develop a simple method for forming dart electrodes with dart lengths of 1 micron or less and low dart resistance.
（発明の目的）
本発明の目的は、従来の欠点を解消し、通常の光露光法
を用いて１ミクロン以下のｒ−ト長が容易に達成され、
かつダート抵抗を低くおさえることのできる半導体装置
の製造方法を提供することである。(Object of the Invention) The object of the present invention is to overcome the conventional drawbacks, and to easily achieve an r-total length of 1 micron or less using a conventional light exposure method.
Moreover, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress dart resistance to a low level.
（発明の構成）
本発明の半導体装置の製造方法は、半導体基板の表面に
第１の絶縁膜を付着させる工程と、この第１の絶縁膜の
一部を薄膜で覆い、この薄膜で覆われていない第１の絶
縁膜を除去する工程と、前記半導体基板の上に第２の絶
縁膜を付着させる工程と、前記薄膜および薄膜上の第２
の絶縁膜を除去する工程と、前記第１の絶縁膜と第２の
絶縁膜の境界に金属を付着させる工程とを備えたもので
ある。(Structure of the Invention) The method for manufacturing a semiconductor device of the present invention includes the steps of attaching a first insulating film to the surface of a semiconductor substrate, covering a part of the first insulating film with a thin film, and covering the first insulating film with a thin film. a step of removing a first insulating film that has not been removed; a step of attaching a second insulating film on the semiconductor substrate; and a step of removing the first insulating film that has not been
and a step of attaching metal to the boundary between the first insulating film and the second insulating film.
（実施ダｊの説明） 本発明の一実施例を第２図に基づいて説明する。(Explanation of implementation) An embodiment of the present invention will be described based on FIG. 2.
第２図は本発明による半導体装置の製造方法を示すもの
で、１は半絶縁性砒化ガリウム基板、２はｎ型砒化ガリ
ウム層、３はｎ型砒化ガリウム層２とオーミック接触と
なる金属、４はｎ型砒化ガリウム層２と７ヨソトキー接
触となる金属、５はフォトレノスト膜で、以上は第１図
の構成と同じで６る。７は第１の絶縁膜としての二酸化
シリコン膜、８は第２の絶縁膜としての一酸化シリコン
膜である。FIG. 2 shows a method for manufacturing a semiconductor device according to the present invention, in which 1 is a semi-insulating gallium arsenide substrate, 2 is an n-type gallium arsenide layer, 3 is a metal that makes ohmic contact with the n-type gallium arsenide layer 2, and 4 is a semi-insulating gallium arsenide substrate. 7 is a metal that makes a horizontal contact with the n-type gallium arsenide layer 2, 5 is a photorenost film, and 6 is the same as the structure shown in FIG. 1. 7 is a silicon dioxide film as a first insulating film, and 8 is a silicon monoxide film as a second insulating film.
以上のように構成されたＧａＡｓ ＭＥＳＦＥＴの製造
工程を説明する。比抵抗１Ｏ７０口の半絶縁性砒化ガリ
ウム基板１上に不純物濃度２ Ｘ １０” ＣＷＩ−３
、厚さ０．３μｍのｎ型砒化ガリウム層２をエピタキシ
ャル成長させ、第２図（ａ）に示すように電極である金
ケ゛ルマニウム合金３を形成するまでは第１図に示した
従来列と同じである つぎにシランの熱分解によって厚
さ０．６μｍの二酸化シリコン膜７を気相成長させ第２
図（ｂ）に示すようにフォトレジスト膜５を・ぐターニ
ングする。その後弗酸緩衝液で二酸化シリコン膜７を除
去すると横方向エツチング効果によシ第２図（ｃ）に示
すように二酸化シリコン膜の端部はわずかに７オトレジ
スト膜５の端部よシ内側となる。つぎに、第２図（ｄ）
に示すように基板表面全面に一酸化シリコン膜８を真空
蒸着法で付着させる。この基板をレジスト剥離液に浸漬
すれば、フォトレジスト膜５が溶解するとともにフォト
レジスト膜５上の一酸化シリコン膜８も同時に除去され
る。このとき二酸化シリコン膜７と−酸化シ１１コン膜
８の境界部分には二酸化シリコン膜７を除去したとき二
酸化シリコン膜７の端部がフォトレノストの内側に入り
込んだ分だけの間隙を生じ、この間隙は二酸化シリコン
膜の厚さ程度の微小なものである。つぎに、酒石酸／過
酸化水素水系の液中で砒化ガリウム層表面を清浄化した
のちアルミニウムを全面に真空蒸着し、フォトレジスト
でパターニングして二酸化シリコン膜７と一酸化シリコ
ン膜８の境界部分だけアルミニウムを残し、第２図（ｅ
）に示すようなｙ−上電極６を形成する。The manufacturing process of the GaAs MESFET configured as above will be explained. Impurity concentration 2 x 10" CWI-3 on semi-insulating gallium arsenide substrate 1 with specific resistance 1O70
The process is the same as the conventional column shown in FIG. 1 until epitaxial growth of an n-type gallium arsenide layer 2 with a thickness of 0.3 μm and formation of a gold-aluminum alloy 3 as an electrode, as shown in FIG. 2(a). Next, a silicon dioxide film 7 with a thickness of 0.6 μm is grown in a vapor phase by thermal decomposition of silane.
As shown in Figure (b), the photoresist film 5 is turned. After that, when the silicon dioxide film 7 is removed with a hydrofluoric acid buffer solution, the lateral etching effect is activated, and as shown in FIG. Become. Next, Figure 2(d)
As shown in FIG. 2, a silicon monoxide film 8 is deposited on the entire surface of the substrate by vacuum evaporation. When this substrate is immersed in a resist stripping solution, the photoresist film 5 is dissolved and the silicon monoxide film 8 on the photoresist film 5 is also removed at the same time. At this time, a gap is created at the boundary between the silicon dioxide film 7 and the -silicon oxide film 8 by the amount that the end of the silicon dioxide film 7 enters inside the photorenost when the silicon dioxide film 7 is removed. is as small as the thickness of a silicon dioxide film. Next, after cleaning the surface of the gallium arsenide layer in a tartaric acid/hydrogen peroxide solution, aluminum is vacuum-deposited on the entire surface, and patterned with photoresist to remove only the boundary between the silicon dioxide film 7 and silicon monoxide film 8. Leaving the aluminum, Figure 2 (e
) A y-upper electrode 6 as shown in FIG.
最後に第２図（ｆ）に示すように金デルマニウム合金３
上の二酸化シリコン膜７および一酸化シリコン膜８に窓
あけを行ないそれぞれソース電極、ドレイン電極として
取り出せるようにＧａＡｓ ＭＥＳＦＥＴを完成する。Finally, as shown in Figure 2(f), gold-dermanium alloy 3
A GaAs MESFET is completed by making windows in the upper silicon dioxide film 7 and silicon monoxide film 8 so that they can be taken out as a source electrode and a drain electrode, respectively.
光露光法でケ゛−ト電極を形成した従来のＧａＡａＭＥ
ＳＦＥＴと本発明の一実施例のＧａＡｓ ＭＥＳＦＥＴ
の特性の比較を表に示す。表に示すように本実施列によ
れば第１の絶縁膜の横方向エツチング効果を利用して微
小な絶縁膜間の間隙を形成し、ここにゲート金属を埋め
こむことによシ同じ光露光法を用いながらｒ−ト長で１
／３、ケ９−ト・ソース間容量で１／２、しかもｒ−）
抵抗はほとんど変らない高鴫波に適した電界効果トラン
ジスタを得ることができる。Conventional GaAaME with gate electrode formed using light exposure method
SFET and GaAs MESFET of one embodiment of the present invention
A comparison of the characteristics is shown in the table. As shown in the table, according to this embodiment, the lateral etching effect of the first insulating film is used to form a minute gap between the insulating films, and by burying the gate metal there, the same light exposure is achieved. 1 with r-t length using the method
/3, 1/2 the capacitance between the gate and the source, and r-)
A field effect transistor suitable for high voltage waves with almost no change in resistance can be obtained.
表
（発明の効果）
本発明によれば、半導体基板上の絶縁膜の一部を７オト
レジストなどの薄膜で覆い、覆われていない絶縁物を除
去し、他の絶縁物を付着させて薄膜および薄膜上の絶縁
物を除去し、絶縁物間の間隙に金属を付着させることに
よシ、ケ°−ト抵抗を増加させないでｆ−）長が短かく
ダート容量の小さい電界効果トランジスタを製作するこ
とができ、その実用的効果は犬である。Table (Effects of the Invention) According to the present invention, a part of an insulating film on a semiconductor substrate is covered with a thin film such as 7-otoresist, the uncovered insulator is removed, and another insulator is attached to form a thin film and By removing the insulator on the thin film and depositing metal in the gap between the insulators, a field effect transistor with short length and small dart capacitance can be fabricated without increasing the gate resistance. Can and its practical effect is a dog.
第１図は従来のＧａＡｓ ＭＥＳＦＥＴの製造工程を示
す断面図、第２図は本発明の一実施例におけるＧａＡｓ
ＭＥＳＦＥＴの製造工程を示す断面図である。
ｌ・・・半絶縁性砒化ガリウム基板、２・・・ｎ型砒化
ガリウム層、３・・・ｎ型砒化ガリウム層とオーミック
接触となる金属、４・・・ｎ型砒化ガリウム層とショッ
トキー接触となる金属、５・・・フォトレジスト膜、６
・・・ケ°−ト電極、７・・・二酸化シリコン膜、８・
・・−酸化ンリコン膜。
第１図
１ａ）
λ１
（Ｃ）
一一−−−一−−−一一−−一−−一二き１第１図
（ｆ）
第２図
（ａ）
一１
（Ｃ）
一一一一一一一一一一一一一一一二−Ｉ（ｅ）
（ｆ）
〜１FIG. 1 is a cross-sectional view showing the manufacturing process of a conventional GaAs MESFET, and FIG. 2 is a cross-sectional view showing the manufacturing process of a conventional GaAs MESFET.
It is a sectional view showing a manufacturing process of MESFET. l... Semi-insulating gallium arsenide substrate, 2... n-type gallium arsenide layer, 3... metal making ohmic contact with the n-type gallium arsenide layer, 4... Schottky contact with the n-type gallium arsenide layer Metal, 5... Photoresist film, 6
... Kate electrode, 7... Silicon dioxide film, 8.
... - oxidized silicon film. Figure 1 1a) λ1 (C) 11---1---11---1---12ki1 Figure 1(f) Figure 2(a) 11 (C) 1111 1111111112-I(e) (f) ~1
Claims (2)
程と、前記第１の絶縁膜の一部を薄膜で覆い、該薄膜で
覆われていない第１の絶縁膜を除去する工程と、前記半
導体基板の上に第２の絶縁膜を付着させる工程と、前記
薄膜および薄膜上の、前記第２の絶縁膜を除去する工程
と、前記第１の絶縁膜と第２の絶縁膜の境界に金属を付
着させる工程とを備えたことを特徴とする半導体装置の
製造方法。(1) A step of attaching a first insulating film to the surface of a semiconductor substrate, a step of covering a part of the first insulating film with a thin film, and removing the first insulating film not covered with the thin film. , a step of attaching a second insulating film on the semiconductor substrate, a step of removing the thin film and the second insulating film on the thin film, and a step of removing the first insulating film and the second insulating film. A method for manufacturing a semiconductor device, comprising the step of attaching metal to a boundary.
リコン膜であることを特徴とする特許請求の範囲第（１
）項記載の半導体装置の製造方法。(2) Claim (1) characterized in that the thin film is a photoresist and the second insulating film is a silicon monoxide film.
) The method for manufacturing a semiconductor device according to item 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18811584A JPS6167274A (en) | 1984-09-10 | 1984-09-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18811584A JPS6167274A (en) | 1984-09-10 | 1984-09-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6167274A true JPS6167274A (en) | 1986-04-07 |
Family
ID=16217965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18811584A Pending JPS6167274A (en) | 1984-09-10 | 1984-09-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167274A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4824800A (en) * | 1987-05-08 | 1989-04-25 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor devices |
| US5252843A (en) * | 1989-09-01 | 1993-10-12 | Fujitsu Limited | Semiconductor device having overlapping conductor layers |
-
1984
- 1984-09-10 JP JP18811584A patent/JPS6167274A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4824800A (en) * | 1987-05-08 | 1989-04-25 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor devices |
| US5252843A (en) * | 1989-09-01 | 1993-10-12 | Fujitsu Limited | Semiconductor device having overlapping conductor layers |
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