JPS58116774A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the high frequency characteristic of a semiconductor device by constructing to have non-vertical property and hence a slope on the side surface of a mesa layer, thereby narrowing the gate length. CONSTITUTION:A channel layer 3 is formed on an arsenided gallium (GaAs) substrate 1, and a photoresist film 4 is coated on the layer 3, thereby forming a mask layer. When it is then etched with an etchant which contains 1-2% of hydrogen peroxide in aqueous solution having 2-8% of potassium hydroxide, the lateral etching distance becomes 3-4mum to the etching distance of longitudinal direction of 1mum, and the mesa layer 3' becomes oblique surface. After the film 4 is then removed, a gold-germanium layer 5 is formed on the source and drain regions. Thereafter, it is heat treated, thereby forming an alloying region 6 and completing a source and a drain.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, 0 (2) Background of the technology Gallium arsenide (EA) has a higher mobility of electrons and holes than silicon (81). Because of its large size, it is advantageous for high frequencies and high switching speeds.Also, arsenide GaAs is used for chromium(or)II.
When I is included, it becomes semi-insulating, so n! l! Forming a single crystal layer of gallium arsenide (GaAs), leaving this single crystal layer on the device formation region, and removing it from the device isolation region to form a mesa shape is extremely advantageous from the point of view of device isolation. In order to prevent stray capacitance from increasing when
It is preferable that the field effect transistor is formed on a semi-insulating substrate.11 A field effect transistor made of gallium arsenide (GaAa) has a gate and a gate on an n-type single crystal layer formed in a mesa shape on a semi-insulating substrate. Generally, a source and drain are formed, and a gate electrode is formed relatively long so as to straddle the mesa step portion and extend to the semi-insulating layer. The nll1 single crystal layer is formed for the purpose of crystal matching and for the purpose of preventing upward diffusion of impurities contained in the substrate.
It is desirable to form the 79277 layer on the substrate.

The thickness of the n-type single crystal layer is about aooo 0OOX is required.

(3) Prior art and problems The advantage of field effect transistors made of gallium arsenide (Gats) is their high speed;
It is desirable that the distance between drains, especially the gate length, be as short as possible. However, in the prior art, as described above, the gate electrode must be formed over a mesa with a height of about 7,000 square meters. On the other hand, in general, as for etching technology, the vertical etching method has been developed, but the non-vertical etching method has not. The gate electrode tends to become discontinuous at this stepped portion.In order to prevent this disconnection, the height of the gate electrode is changed as high as possible by 1.2 μm8, but the stepped portion Since the gate electrode window is cut and as a result, the desired pinch-off voltage cannot be obtained, the gate length cannot be made very narrow, and conventionally it required a length of 2μ! Approximately 7 parts with a two-tiered structure
, attempts have been made to halve the height difference between 0OOX and
No significant effect was observed, and it is not very effective in reducing gate length.
Conventionally, it was thought that it was unavoidable that a gate length of about 2 μm or more was required. This means that the advantages of gallium arsenide (Ga) field effect transistors are not fully exploited, and the advantages of gallium arsenide (Ga) field effect transistors are not fully exploited.
oaAs) field effect transistors have been desired to be developed.

(4) Purpose of the invention The purpose of the present invention is this 'g! There is one thing that answers your request.
An object of the present invention is to provide a method for manufacturing a gallium arsenide (GaAs) field effect transistor that can have a narrow gate length, have good high frequency performance, and have a high switch tendering speed.

(5) Structure of the Invention The present invention achieves the above object by making the side surfaces of the mesa-like layer non-vertical, that is, inclined. ) Chrome (O
Gallium arsenide (GaAs), which has medium insulating properties, contains
), preferably an i-type arsenide gallium atom (
Form a 79277 layer made of single crystal (GaAs), (b) form a channel layer made of n-type gallium arsenide (GaAs) single crystal on the above substrate or layer 7, and ) After forming a mask layer by coating and drying a masking material such as a photoresist on the above channel layer, this mask layer is removed from areas other than the element formation area using a lithography method to form the element formation area of the channel layer. To form a mask for etching, to )! The above r
Chemical etching is performed on the channel layer in the region not etched by the etching mask, and the channel layer and the 79277 layer or the upper layer of the substrate are formed into a mesa with sloped sides in the device formation region. (e) Selectively apply a metal layer such as gold/germanylum/gold (Mu-Go/Mu-U) to the source/drain electrode formation region of the mesa-like layer. After formation, heat treatment is performed to alloy this region to form a source/drain, and (to) aluminum (^t
), etc., to form a gate.

If the concentration of potassium hydroxide is less than 2%, sufficient etching correlation will not be obtained, and if it exceeds 8%, the quality of the photoresist serving as a mask will be deteriorated. On the other hand, if hydrogen peroxide is less than 1%1, the etching speed is sufficient.
I can't get it and it's not possible? This will lead to uneven turns. If the hydrogen peroxide in the vessel exceeds 2%, it is difficult to obtain a gently sloped slope.

The feature of the above structure is that when an etching solution having the above composition is used, the etching rate is 2.000'A.
Although it is not necessarily fast as it is less than /min, there are cases where the etching surface is inclined and the side surfaces of the mesa-shaped channel layer are not vertical but inclined. The above composition is compared to the composition of etching solutions commonly used in the prior art (approximately 25% hydrogen peroxide (contains H, O)).
Although the content of hydrogen peroxide (HsOs) is small, if the content of hydrogen peroxide (HsOs) is further reduced to 1% or less, the slope of the etched surface becomes extremely slow (as the slope becomes less uniform, the slope angle becomes uneven, making it difficult to use industrially). It has been confirmed that this is not possible.

In addition, in the case of the etching solution commonly used in the above-mentioned conventional technology, the etching speed is a, ooo XZ minutes!
However, the lowest etching speed that can be used industrially is 50
0m/min! be.

Inferred from this phenomenon, in the case of the etching solution according to the present invention, it is presumed that the etching effect due to the etching solution seeping into the interface between the etching mask made of photoresist and the channel layer has a large effect. .

(6) Embodiments of the Invention Hereinafter, with reference to the drawings, a method for manufacturing a live conductor device, particularly a gallium arsenide (GaAa) field effect transistor, according to an embodiment of the present invention will be explained, and the structure and unique effects of the present invention will be explained. to clarify.

Refer to Fig. 1. Medium insulating gallium arsenide (GaAa) substrate containing a-m (Or) to'' ~ 1017/cR''N&l
On top, using a vapor phase epitaxial growth method using Ga+^θ013+ Hts as a reaction system, a type 1 gallium arsenide (Game) single crystal layer is formed to a thickness of about 3 to 5 μm to form a 79 sofa layer, and then, Sulfur with n-type impurity 1 (
A channel layer 3 is formed by forming an arsenide IJ & Lamb (GaAs) single crystal layer having a thickness of about 0.2 to 1 .mu.m containing 8.times.10" to 3.times.10.sup.17/- of GaAs.

Referring to Figure 2, he applied a photoresist such as OMR83 manufactured by Tokyo Ohka Co., Ltd. to the entire surface and pre-baked it at (400°C) for (400 minutes) to form a photoresist film 4.
This was removed from areas other than the area on which the stamp was formed using the roughy method, and a post bake was performed at 145° C. for 9 minutes to form an etching mask.

Refer to Figure 3. Chemical etching is carried out to a depth of about 7.00X using an aqueous solution containing 5 parts by weight of potassium hydroxide (KOH) and a solution containing 1.51 parts by weight of hydrogen peroxide (H,O) as an etching solution. In this case, the etching speed is 1, ooo~
11500X/min, which is much slower than the 3,000 OOA/min in the case of aqueous solutions containing 15% hydrogen peroxide (H!O) used in the prior art;
The horizontal etching distance is 3 for the etching distance of voice m.
4 μm, and the side surface of the mesa layer 3' becomes a slope with a gentle slope as shown in the figure. In this embodiment, the angle is approximately 16°.

4(a) and 4(b) After dissolving and removing the etching mask 4, a so-called etching process 7 is performed.
A gold-germanium/gold (Au-Gs/Au) layer 5 with a thickness of about 4000 A is selectively formed on the source/drain regions using the TO7 method. That guy, 450℃
Heat treatment is performed for 2 minutes to a degree of 1% to form an alloyed region 6 and complete the source/drain.

Refer to FIG. 5(a), M 5 (1:+) diagram. Using the so-called lift-off method, an aluminum (^t) layer 7 with a width of about 1 μm is selectively deposited on the gate region at a thickness of about 7,000 OOA.
The gate electrode is formed at a height of .

At this time, as mentioned above, the slope of the side surface of the mesa 3 is 16
Since the width varies by degrees, disconnection will not occur even if the width is as narrow as 1 μm. Note that the distances between the source and the gate and between the gate and the drain must be approximately 1.5 μm or more, but this is a factor mainly determined by the limit of alignment carbohydrates.

(7) Effects of the Invention As explained above, according to the present invention, a method for manufacturing a gallium arsenide (GaAa) field effect transistor with a narrow gate length, good high frequency characteristics, and high switching speed is provided. can be provided.

[Brief explanation of drawings]

Section 1.2.3.4(a), 4(b), 5(a), 5(b)
) is a cross-sectional view or a plan view of the main steps of the method for manufacturing an arsenide IJzium field effect transistor according to an embodiment of the present invention. 1... Medium insulating substrate, 2... 79277 layers, 3...
・n [arsenide gallium layer (channel layer), 3'...
Mesa layer, 4... Etching mask, 5... Gold.
Germanium/gold layer (source/drain current 1k), 6
... Alloyed region, 7... Alionium gourd layer (gate electrode).

Claims (1)

[Claims] A gallium arsenide single crystal layer is formed on a semi-insulating substrate, an etching mask is formed in the element formation region on the gallium arsenide single crystal layer, and an aqueous solution containing potassium hydroxide in the range of 291 to 896 is used. The arsenide film I in the areas not covered by the etching mask is removed using a solution containing hydrogen peroxide in the range of 1 to 2.
J & Lam Chemically etching the single crystal layer to create etched and non-etched areas? - slope across;
A method of manufacturing a semiconductor device, comprising the step of thereafter forming a metal layer extending from the gallium arsenide single crystal layer onto a semi-insulating substrate.