JPH0574814A - Manufacture of schottky-gate type field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce source series resistance in a Schottky-gate type FET. CONSTITUTION:An N-GaAs active layer 2, an Al film 3 and an SiO2 film 4 are formed successively onto a semi-insulating GaAs substrate 1. The SiO2 film 4 is patterned in a gate shape, the Al film 3 is patterned while using the film 4 as a mask, and the Al film 3 is side-etched. An AuGe/Ni/Au film 6 is formed onto the whole surface as the SiO2 film 4 is left as it is, and source- drain electrodes 6a, 6b are shaped on both sides of the Al film 3 as a gate electrode by the SiO2 film 4 by separating the AuGe/Ni/Au film 6. Accordingly, a source-drain interelectrode distance can be set at a small value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky gate type field effect transistor, and more particularly to a method for manufacturing a source / drain electrode which makes ohmic contact with a semiconductor and a gate electrode which makes Schottky junction.

[0002]

TECHNICAL BACKGROUND AND PROBLEMS OF THE INVENTION A Schottky gate field effect transistor in which a Schottky gate electrode and an ohmic source / drain electrode are formed on a compound semiconductor utilizes a high mobility of an active layer. It is used as an ultra high frequency transistor. In the Schottky gate type field effect transistor, the source series resistance Rs is a factor that affects the transistor characteristics such as operating frequency and noise figure. If the source series resistance Rs is reduced, the operating frequency of the Schottky gate field effect transistor can be increased and the noise figure can be reduced.

The source series resistance Rs is caused by the contact resistance of the source electrode and the resistance of the n-active layer between the source and the gate. As a measure for reducing these resistance components, the gate of the refractory metal is used as a mask for ion formation. N by injection
A self-aligned process for forming a ⁺ layer and a recess gate structure are known.

In any of the processes, it is essential to form the n ⁺ layer by a method of reducing the source series resistance Rs by bringing the low resistance n ⁺ layer close to the vicinity of the gate electrode.
Since the contact position of the source electrode and the distance between the gate electrodes are determined by ordinary mask alignment accuracy, there is a limit only in reducing the series resistance Rs by lowering the resistance of the n ⁺ layer.

[0005]

It is an object of the present invention to provide a method of manufacturing a Schottky gate type field effect transistor which can further reduce the source series resistance Rs in order to further improve high frequency characteristics. is there.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a gate material to be a Schottky gate is coated on an n-active layer on a compound semiconductor substrate, and side etching occurs to the Schottky gate material using a mask material made of an insulating film as a mask. Etching up to. After that, ohmic so that the entire surface is covered.
The source / drain material and the insulating film are sequentially deposited, and the insulating film on the outermost surface is etched until only the ohmic source / drain material above the Schottky gate is exposed. The exposed ohmic source / drain material is etched until the mask material used as the mask for forming the Schottky gate is exposed to insulate and separate the source electrode and the drain electrode.

As described above, the distance between the ohmic source / drain electrode and the Schottky gate electrode is controlled to the distance determined by the side etch amount of the Schottky gate electrode, which is shorter than that of the conventional structure. As a result, the source series resistance Rs is reduced, and the high frequency characteristics of the Schottky gate type field effect transistor are further improved.

[0008]

Therefore, if the manufacturing method of the present invention is applied to the manufacturing process of the Schottky gate electrode and the ohmic source / drain electrode of the Schottky gate field effect transistor, the source series resistance Rs can be further reduced. The characteristics of the field effect transistor can be further improved.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A to 1D are sectional views in the order of steps showing the manufacturing steps of a first embodiment of the present invention used for manufacturing a Schottky gate type field effect transistor.

As shown in FIG. 1A, first, n-GaAs having a carrier concentration capable of forming an active layer of a Schottky gate field effect transistor by epitaxial growth or ion implantation on a semi-insulating GaAs substrate 1.
A layer 2 is formed and an Al film 3, for example a Schottky gate material, is deposited on this n-GaAs layer 2 by vapor deposition. Further, the SiO ₂ film 4 is SiH by plasma CVD.
_A film is formed using _4, H _2, N ₂ O gas. Here, the SiO ₂ film 4 may be an insulating film, and may be SiNx or the like.

Then, SiO ₂ is removed by ordinary photolithography.
A gate-shaped resist pattern 5 is formed on the film 4, and the resist 5 is used as a mask in a CF ₄ etching gas with a CF ₄ etching gas using a RIE (reactive ion etching) apparatus.
As shown in (b), until the Al film 3 is exposed, SiO ₂
The film 4 is etched.

Then, as shown in FIG. 1 (c), SiO
_{2 The} Al film 3 is etched by wet etching with H ₃ PO ₄ using the film 4 as a mask until side etching occurs. The resist 5 used as the etching mask for the SiO ₂ film 4 in FIG. 1B may be removed by ashing using O ₂ gas before and after the etching of the Al film 3.

Then, as shown in FIG. 1 (d), the entire surface is turned on.
AuGe / as the source / drain electrode material
The Ni / Au film 6 is formed. At this time, S which becomes a mask
iO ₂The width of the film 4 is larger than the line width of the gate 3 on the above side.
Since it is made large by etching, the gate electrode 3
And AuGe / Ni / Au film 6 are separated by self-alignment
To be done. Then, as shown in FIG. 1E, for example, E
SiH by CR-CVD_Four, O₂, Using Ar gas
SiO with a flat surface₂The film 7 is formed.

Then, as shown in FIG.
Until the drain electrode material, that is, the AuGe / Ni / Au film 6 is exposed on the surface, the SiO ₂ film 7 on the surface is removed from the surface by H
Etching is performed by wet etching using a F or (HF + NH ₄ F) mixed solution. By this etching, the surface of the AuGe / Ni / Au film 6 located on the gate electrode 3 is exposed.

Then, as shown in FIG. 1 (g), the exposed Au is
Au / Ge / Ni / A on both sides of the Ge / Ni / Au film 6 sandwiching the gate electrode with the (I ₂ + KI) etchant.
Etch until the u electrode material is isolated. By this etching, the source electrode 6a and the drain electrode 6b are formed on both sides of the gate electrode 3 by the SiO ₂ film 4 in a self-aligned manner. At this time, the AuGe / Ni / Au film in the remaining region of the SiO ₂ film 7 is not etched.

Even in the state shown in FIG. 1 (g), Si
O ₂ film 4 and the SiO ₂ film 7 serves as a surface protective film, but further SiO ₂ or SiN on the surface as shown in FIG. 1 (h)
If the protective film 8 such as the x film is deposited, the reliability is further improved.

As described above, the distance between the ohmic source / drain electrode and the Schottky gate electrode is controlled to the distance determined by the side etch amount of the Schottky gate electrode, which is shorter than the conventional structure. As a result, the source series resistance Rs is reduced, and the high frequency characteristics of the Schottky gate type field effect transistor are further improved.

Next, a second embodiment of the present invention will be described with reference to FIG. 2A to 2D are sectional views in the order of steps showing the manufacturing steps of the second embodiment of the present invention used for manufacturing the Schottky gate type field effect transistor.

First, as shown in FIG. 2A, an n-GaAs layer 2 having a carrier concentration which can be an active layer of a Schottky gate field effect transistor by epitaxial growth or ion implantation on a semi-insulating GaAs substrate 21.
2 is formed, and an Al film 23 is deposited on the n-GaAs layer 22 as a Schottky gate material by vapor deposition.
Then, as shown in FIG. 2B, a gate-shaped resist pattern 25 is formed on the structure shown in FIG.

Next, using the resist 25 as a mask, H
_The Al film 23 is etched by wet etching with ₃ PO ₄ . At this time, the Al film 23 is etched until side etching occurs, and the resist pattern 2 is formed.
The structure shown in FIG. 2C is obtained in which the line width (gate length) of the Al film 23 is smaller than the line width of 5.

Subsequently, while leaving the resist pattern 25, an AuGe / Ni / Au film 26 is formed as an ohmic source / drain electrode material on the entire surface to obtain the structure shown in FIG. At this time, the Al film 2 to be the gate electrode
There are gaps on both sides of 3 due to side etching, and the gap separates the Al film 23 and the AuGe / Ni / Au film 26 from each other. Next, as shown in FIG.
A SiO ₂ film 27 having a flat surface is formed by ECR-CVD using SiH ₄ , O ₂ and Ar gas. Then, as shown in FIG. 2F, the SiO ₂ film 27 is used from the surface by using HF or (HF + NH ₄ F) until the AuGe / Ni / Au film 26 is exposed on the Al film 23 which becomes the Schottky gate. Etch back by wet etching. Further, as shown in FIG.
The AuGe / Ni / Au film 26 exposed on the surface is formed by (I ₂ +
Etching is performed until the AuGe / Ni / Au electrode material on both sides of the gate electrode (Al film) 23 sandwiched by KI) is isolated. By this etching, the gate electrode 23
A source electrode 26a and a drain electrode 26b made of the AuGe / Ni / Au film 26 are formed on both sides of the. Further, at this time, the SiO remaining on the AuGe / Ni / Au film 26
_{2 The} film 27 acts as an etching mask.

After that, the resist mask 25 left on the gate electrode 23 is removed by O ₂ ashing or a resist remover, etc., and SiO _{2 is} removed as shown in FIG.
A Schottky gate field effect transistor is formed by forming a surface protective film 28 such as a film or a SiNx film.
In FIG. 2H, before removing the resist mask 25, SiO ₂ on the source and drain electrodes 26a and 26b is removed.
Although the case where the surface protection film 28 is formed after the film 27 is completely removed by etching with HF or the like is shown, the surface protection film 28 is further left with the SiO ₂ film 27 on the source / drain electrodes 26a and 26b left. May be formed.

Also in this embodiment, as in the first embodiment, the source-gate electrode distance can be set to a smaller value by setting the side etching amount of the Al film 23 to a smaller value, and the source series resistance can be reduced. It is possible to reduce Rs. Further, the source and drain electrodes can be formed by the resist mask 25 in a self-aligned manner with the gate electrode 23.

In the first and second embodiments described above, an example using Al as the Schottky gate electrode is shown.
Other materials such as Ti, Pt, Au, and Mo can be used to form the Schottky junction with n-GaAs. In that case, etching may be performed by an appropriate etching method for each electrode material. In addition, AuGe / Ni / A is used for the ohmic source / drain electrodes.
Although the u film is used, any material that allows ohmic contact with the GaAs substrate may be used, and AuGe / Au or the like is also possible.

Furthermore, in the above first and second embodiments,
After forming the ohmic drain electrode, for example, as shown in FIG.
(G), in the process step shown in FIG. 2 (g), in order to obtain an ohmic contact between the ohmic source / drain electrodes and the underlying n-GaAs substrate, alloying at a temperature of about 400 ° C. in a H ₂ gas atmosphere. It is advisable to apply heat treatment.

In the first and second embodiments, if a high melting point metal material such as Ti / W is used for the gate electrode material, a step before the ohmic source / drain material is deposited on the entire surface, for example, as shown in FIG. In the process step shown in FIG. 1 (c) and FIG. 2 (c), ion implantation and activation annealing are performed using this heat-resistant gate as a mask, so that n ⁺ having a high carrier concentration for ohmic contact is formed under the source / drain electrodes. Therefore, the source series resistance Rs can be further reduced.

The ECR-C formed in the steps shown in FIGS. 1E and 2E in the first and second embodiments.
The SiO ₂ films 7 and 27 formed by VD may be an insulating film such as a resist or SiNx as long as it is a material that can be a mask for etching the ohmic source / drain electrode material. However, as shown in FIGS. 1 (e) and 2 (e), when the surface is not flat like the SiO ₂ film formed by ECR-CVD, the results are shown in FIGS. 1 (f) and 2 (f). In the step shown, before exposing only the ohmic source / drain electrode material on the gate material by etch back, it is necessary to make the surface flat by a method such as mechanically polishing the surface.

[Brief description of drawings]

1A to 1H are cross-sectional views in order of steps, for explaining a first embodiment of the present invention.

2A to 2H are sectional views in order of the processes, for explaining a second embodiment of the present invention.

[Explanation of symbols]

1, 21 Semi-insulating GaAs substrate 2, 22 GaAs active layer 3, 23 Al film Schottky gate electrode material 4 SiO ₂ film 5, 25 resist 6, 26 AuGe / Ni / Au film (ohmic source / drain electrode material) 7,27 SiO ₂ film 8,28 Surface protection film

Front page continued (72) Inventor Yoshiki Ueno 1-1, Showa-cho, Kariya city, Aichi prefecture

Claims (1)

[Claims] 1. A step of depositing a gate electrode material on the entire surface of a semiconductor substrate, a step of forming a mask material in a gate shape, and a step of etching the gate electrode from the end of the mask to the inside with the mask. , A step of continuously depositing the source / drain electrode material and the insulating film while leaving the mask, and removing the surface insulating film so that the source / drain electrode material is exposed only on the gate electrode, and then exposing. And a step of removing the source / drain electrode material described above until the source electrode and the drain electrode are electrically separated from each other.