JPS6246073B2 - - Google Patents
Info
- Publication number
- JPS6246073B2 JPS6246073B2 JP20903182A JP20903182A JPS6246073B2 JP S6246073 B2 JPS6246073 B2 JP S6246073B2 JP 20903182 A JP20903182 A JP 20903182A JP 20903182 A JP20903182 A JP 20903182A JP S6246073 B2 JPS6246073 B2 JP S6246073B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- film
- gate
- dry etching
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 238000001020 plasma etching Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000010931 gold Substances 0.000 description 13
- 239000007789 gas Substances 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はゲートにシヨツトキー障壁を用いたい
わゆるシヨツトキーゲート型電界効果トランジス
タの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a so-called Schottky gate field effect transistor using a Schottky barrier in the gate.
ゲートにシヨツトキー障壁を用いた電界効果ト
ランジスタ（FET）においては、ゲート長及び
ソース・ゲート間に存在するソース直列抵抗がそ
の特性を決定づける大きな要因となつている。す
なわち、ゲート長（lg）と、FETの信号伝搬遅
延時間（tpd）との間には
tpd∝lg2
なる関係があるため、lgを短かくするほどtpdが
小さくなり、高速動作が可能となる。また、ソー
ス直列抵抗（Rs）については、FETの真性相互
コンダクタンスをgmo、実際の相互コンダクタン
スをgmとすれば
gm＝gmo／（１＋gmoRs）
なる関係があり、Rsが大きいほどgmを小さくし
てしまう。さらに、lgとgmoの間には
gmo∝１／lg
なる関係がある。
In a field effect transistor (FET) using a Schottky barrier at the gate, the gate length and the source series resistance existing between the source and gate are major factors that determine its characteristics. In other words, there is a relationship between the gate length (lg) and the FET signal propagation delay time (tpd): tpd∝lg 2 , so the shorter lg, the smaller tpd becomes, enabling high-speed operation. . Regarding source series resistance (Rs), if the FET's intrinsic transconductance is gmo and the actual transconductance is gm, then there is a relationship as follows: gm = gmo/(1 + gmoRs), and the larger Rs is, the smaller gm is. . Furthermore, there is a relationship between lg and gmo: gmo∝1/lg.
すなわちFETの動作速度を速くするために
は、ゲート長lgを短くし、かつソース直列抵抗
Rsを小さくする必要がある。 In other words, in order to increase the operating speed of the FET, the gate length lg should be shortened and the source series resistance should be reduced.
It is necessary to reduce Rs.
しかしながら、ゲート長を短くすることは従来
のフオトエツチングの技術に限界があり、１μｍ
以下のゲート長を得ることは困難とされている。 However, there is a limit to reducing the gate length with conventional photoetching technology, which is 1 μm.
It is considered difficult to obtain a gate length below.
そこで従来用いられてきた方法として、第１図
に示すように、耐熱性金属でゲート電極３を形成
し、これをマスクとしてゲートの両脇にイオン注
入を行ない、高濃度層４，５を形成してRsを低
減する方法がある。図中、１は例えば半絶縁性
GaAs基体、２はｎ型GaAs層である。しかし、こ
の方法ではアニール時の高濃度層４，５の不純物
再拡散によりゲート電極３と高濃度層４，５が重
なるため、ゲート容量が増大し、かつドレイン耐
圧が4V程度と低くなつてしまう。 Therefore, as shown in FIG. 1, the conventional method used is to form a gate electrode 3 with a heat-resistant metal, and use this as a mask to implant ions on both sides of the gate to form high concentration layers 4 and 5. There is a way to reduce Rs. In the figure, 1 is, for example, semi-insulating
GaAs base, 2 is an n-type GaAs layer. However, in this method, the gate electrode 3 and the high concentration layers 4 and 5 overlap due to impurity re-diffusion in the high concentration layers 4 and 5 during annealing, which increases the gate capacitance and lowers the drain breakdown voltage to about 4V. .
また、別の例として、第２図に示すようにゲー
ト電極３をエツチングする際にオーバーエツチン
グをかけてゲート長を短縮し、さらにエツチング
マスクであるフオトレジスト６をそのままイオン
注入のマスクとして用いて高濃度層４，５を形成
する方法がある。しかしこの方法では、ゲート電
極のエツチングに従来のウエツトエツチング法や
等方的なプラズマエツチング法等を用いた場合に
は、金属膜の膜厚分布によりオーバーエツチング
の量が異なつてしまい、ゲート長の精密な制御が
難しい。さらに、イオン注入の際には、面チヤン
ネリングの効果等を避けるため、基板を５〜10゜
傾けることが多く、この方法を用いた場合には、
ゲート電極にソース領域もしくはドレイン領域の
どちらか一方が必要以上に近接してしまう可能性
もある。 As another example, as shown in FIG. 2, when etching the gate electrode 3, over-etching is applied to shorten the gate length, and the photoresist 6, which is an etching mask, is used as it is as a mask for ion implantation. There is a method of forming the high concentration layers 4 and 5. However, with this method, when a conventional wet etching method or isotropic plasma etching method is used to etch the gate electrode, the amount of overetching varies depending on the thickness distribution of the metal film, resulting in an increase in the gate length. It is difficult to control precisely. Furthermore, during ion implantation, the substrate is often tilted at an angle of 5 to 10 degrees to avoid the effects of surface channeling.
There is also a possibility that either the source region or the drain region becomes closer to the gate electrode than necessary.
本発明は以上の点にかんがみなされたもので、
高度なリソグラフイ技術を使用せずにサブミクロ
ンまでのゲート長の短縮ができ、さらにソース直
列抵抗が小さくかつドイレン耐圧の高いシヨツト
キーゲート型FETを製造する方法を提供するも
のである。
The present invention has been made in view of the above points,
The present invention provides a method for manufacturing a Schottky gate type FET that can shorten the gate length to submicrons without using advanced lithography technology, has a low source series resistance, and has a high drain breakdown voltage.
本発明は要約すれば、異方性と等方性のドラ
イエツチング技術をこの順に連続的に組み合わせ
てゲート電極金属膜をエツチングすることによ
り、制御性よくマスク寸法よりわずかに小さいゲ
ート長を得ること、次にマスクを残したままス
テツプカバレージに優れた堆積法により絶縁膜を
形成した後、異方性ドライエツチングを行ない、
ゲート電極の側面即ちマスクのひさしの下にのみ
この絶縁膜を残し、この状態でイオン注入により
低抵抗ソース、ドレイン領域を形成すること、を
特徴とする。
In summary, the present invention is to obtain a gate length slightly smaller than the mask dimension with good controllability by etching a gate electrode metal film by sequentially combining anisotropic and isotropic dry etching techniques in this order. Next, an insulating film is formed using a deposition method with excellent step coverage while leaving the mask, and then anisotropic dry etching is performed.
The method is characterized in that the insulating film is left only on the side surfaces of the gate electrode, that is, under the eaves of the mask, and in this state, low-resistance source and drain regions are formed by ion implantation.
本発明によれば、ドライエツチング技術の組合
せによりサブミクロンまで制御性よくゲート長を
短縮することができる。またゲート電極の側面に
絶縁膜をつけた状態でイオン注入を行う結果、ゲ
ート電極とソース、ドレイン領域の間を制御性よ
く微小間隔だけ離すことができ、従つてゲート容
量が小さく、高速動作が可能で、かつドレイン耐
圧の高いシヨツトキ−ゲート型FETが得られ
る。
According to the present invention, the gate length can be shortened to submicrons with good controllability by combining dry etching techniques. In addition, as a result of performing ion implantation with an insulating film attached to the side surface of the gate electrode, it is possible to separate the gate electrode and the source and drain regions by a minute distance with good controllability, resulting in small gate capacitance and high-speed operation. Therefore, a short key gate type FET with high drain breakdown voltage can be obtained.
以下、基板にGaAsを用いた実施例について、
第３図を参照して詳細に説明する。例えば、クロ
ム（Cr）をドープした半絶縁性GaAs基体１１に
活性層となるｎ型GaAs層１２を成長させた基板
を用い、この表面にゲート電極となる耐熱性金属
膜としてタングステン（Ｗ）膜１３を4000Åの厚
さに全面被着し、更にそのゲート電極となる部分
に耐エツチングマスクとして１μｍ幅の金
（Au）膜１４を約2000Åの膜厚で形成する（第３
図ａ）。この際、Au膜１４のパターニングにはリ
フトオフ法を用いれば、微細パターンを精度よく
形成できる。
Below, regarding an example using GaAs for the substrate,
This will be explained in detail with reference to FIG. For example, a substrate is used in which an n-type GaAs layer 12 that becomes an active layer is grown on a semi-insulating GaAs substrate 11 doped with chromium (Cr), and a tungsten (W) film is formed on the surface of this substrate as a heat-resistant metal film that becomes a gate electrode. A gold (Au) film 14 with a width of 1 μm and a thickness of about 2000 Å is formed on the portion that will become the gate electrode as an etching-resistant mask.
Diagram a). At this time, if a lift-off method is used for patterning the Au film 14, a fine pattern can be formed with high precision.
次にこのAu膜１４をマスクとして、Ｗ膜１３
を平行平板型反応性イオンエツチング（RIE）装
置により完全にエツチングする（第３図ｂ）。エ
ツチングガスとしてはCF4、流量は20c.c.／min、
エツチングガス圧は0.05Torrで、高周波電力は
200Wである。この条件でのＷ膜１３のエツチン
グ速度は300Å／minであり、エツチングは完全
な異方性で進行する。なお、Au膜１４、GaAs層
１２との選択比はそれぞれ〜８、〜10と充分に得
られている。このRIEにひきつづき、通常の円筒
型プラズマエツチング装置にてＷ膜１３をエツチ
ングする。エツチングガスとしてはCF4とO2の混
合ガスを用い、流量はそれぞれ15c.c.／min、５
c.c.／min、エツチングガス圧は0.1Torrで、高周
波電力は100Wである。円筒型プラズマエツチン
グ装置では、Ｗ膜１３は等方的にエツチングさ
れ、エツチング速度は100Å／minである。この
条件下で20分間エツチングすると、Au膜１４と
GaAs層１２はまつたくエツチングされないた
め、Ｗ膜１４の側壁が後退してAu膜１４のひさ
し（Δｘ）が0.2μｍ形成される（第３図ｃ）。 Next, using this Au film 14 as a mask, the W film 13
is completely etched using a parallel plate reactive ion etching (RIE) device (Figure 3b). Etching gas was CF 4 , flow rate was 20c.c./min.
The etching gas pressure is 0.05 Torr, and the high frequency power is
It is 200W. The etching rate of the W film 13 under these conditions is 300 Å/min, and the etching progresses with complete anisotropy. Note that the selectivity with respect to the Au film 14 and the GaAs layer 12 is sufficiently obtained as ~8 and ~10, respectively. Following this RIE, the W film 13 is etched using a normal cylindrical plasma etching device. A mixed gas of CF 4 and O 2 was used as the etching gas, and the flow rates were 15 c.c./min and 5 c.c./min, respectively.
cc/min, etching gas pressure is 0.1 Torr, and high frequency power is 100W. In the cylindrical plasma etching apparatus, the W film 13 is etched isotropically at an etching rate of 100 Å/min. After etching for 20 minutes under these conditions, the Au film 14
Since the GaAs layer 12 is not etched completely, the side wall of the W film 14 recedes, and the eaves (Δx) of the Au film 14 are formed by 0.2 μm (FIG. 3c).
このように、まず異方性ドライエツチングであ
るRIEでＷ膜の側壁を垂直に加工した後、等方性
ドライエツチングであるプラズマエツチングでサ
イドエツチングをかける方法をとつているため、
サイドエツチ量（Δｘ）の制御が非常に精密にで
きる。また、すべてドライエツチング工程である
ため、ウエハ面内及びウエハ間の均一性も非常に
よい。例えば、この状態で２インチφウエハ全面
でゲート長を測定した所、Ｗ膜の膜厚分布が±
700Å程度であつたにもかかわらず、ゲート長は
0.6μｍ±0.05μｍであつた。さらにAu膜のひさ
しΔｘは面内でほとんどバラツキがなく、±0.05
μｍの分布はAu膜のパターンを形成した時点で
のバラツキと考えることができる。 In this way, we first process the side walls of the W film vertically using RIE, which is anisotropic dry etching, and then perform side etching using plasma etching, which is isotropic dry etching.
The side etching amount (Δx) can be controlled very precisely. Furthermore, since the entire process is a dry etching process, the uniformity within the wafer surface and between wafers is also very good. For example, when we measured the gate length over the entire surface of a 2-inch φ wafer in this state, we found that the film thickness distribution of the W film was ±
Even though it was about 700Å, the gate length was
It was 0.6 μm±0.05 μm. Furthermore, the eaves Δx of the Au film has almost no variation within the plane, ±0.05
The distribution of μm can be considered to be a variation at the time when the pattern of the Au film is formed.
上記のようにゲート電極を形成した後、減圧
CVD（LPCVD）法によりSi3N4膜１５を〜6000Å
堆積する。この方法はステツプカバレージが非常
に良いため、基板上の凹凸を完全にカバーできる
（第３図ｄ）。この後、全面にCF4ガスによるRIE
を行なう。この結果、RIEの異方性のためにAu
膜１４のひさしの下部にのみSi3N4膜１５が残る
（第３図ｅ）。 After forming the gate electrode as above, reduce the pressure
Si 3 N 4 film 15 ~6000Å by CVD (LPCVD) method
accumulate. Since this method has very good step coverage, it is possible to completely cover the irregularities on the substrate (FIG. 3d). After this, RIE the entire surface with CF4 gas.
Do this. As a result, Au
The Si 3 N 4 film 15 remains only under the eaves of the film 14 (FIG. 3e).
この状態で 28Si+イオンを、加速電圧
200KeV、ドーズ量３×1013cm-3でイオン注入
し、800〜850℃で15分間のアニールを行つて低抵
抗のソース領域１６、ドレイン領域１７を形成し
た後、ソース、ドレイン領域１６，１７にAuGe
合金からなるオーミツク電極１８，１９を形成し
た（第３図ｆ）。 In this state, 28 Si + ions are
After ion implantation at 200KeV and a dose of 3×10 13 cm -3 and annealing at 800 to 850°C for 15 minutes to form low resistance source and drain regions 16 and 17, AuGe
Ohmic electrodes 18 and 19 made of an alloy were formed (FIG. 3f).
この結果、ゲートのマスク寸法が１μｍである
にもかかわらず、実際のゲート長が0.6μｍと短
く、また、ソース、ドレインとゲート間が0.2μ
ｍと小さいためソース直列抵抗もゲート容量も十
分に小さく、高速動作が可能で、かつドレイン耐
圧が10V以上という高性能のFETが得られた。し
かもFET特性はウエハ面内及びウエハ間でもバ
ラツキが少なく、非常に均一性のよいものであつ
た。 As a result, although the gate mask size is 1 μm, the actual gate length is as short as 0.6 μm, and the distance between the source, drain, and gate is 0.2 μm.
Because the FET is small, the source series resistance and gate capacitance are sufficiently small, high-speed operation is possible, and a high-performance FET with a drain breakdown voltage of 10 V or more was obtained. Moreover, the FET characteristics had very good uniformity with little variation within the wafer surface and between wafers.
また、比較例として上記実施例中のAu膜の部
分にAl2O3膜を用い、第３図ｃの状態で、イオン
注入し常圧CVD法によるSiO2でパツシベーシヨ
ンした後、熱処理してFETを形成した。これを
上記実施例と比較すると、上記実施例のものの方
が、ゲート電極自身の抵抗が３割程度低く、また
ソース直列抵抗のバラツキも1/2程度に小さかつ
た。比較例の場合、直列抵抗のバラツキはイオン
注入時に基板を７゜傾けているためと考えられる
が、ゲート電極の側壁にSi3N4膜を形成した上記
実施例のものは、このSi3N4膜がイオン注入のマ
スクとなるため、基板を傾けてもバラツキが小さ
くなつている。さらに、同じ理由から、ドレイン
耐圧も、比較例の場合で６〜12Vに対し、上記実
施例のものでは10〜12Vとバラツキが小さくなつ
ていた。 As a comparative example, an Al 2 O 3 film was used in place of the Au film in the above example, and in the state shown in Fig. 3c, ions were implanted, passivation was performed with SiO 2 by atmospheric pressure CVD, and heat treatment was performed to form an FET. was formed. Comparing this with the above embodiment, in the above embodiment, the resistance of the gate electrode itself was about 30% lower, and the variation in the source series resistance was about 1/2 smaller. In the case of the comparative example, the variation in series resistance is thought to be due to the substrate being tilted at 7 degrees during ion implantation, but in the above example in which a Si 3 N 4 film was formed on the side wall of the gate electrode, this Si 3 N Since the 4- layer film serves as a mask for ion implantation, variations are reduced even when the substrate is tilted. Further, for the same reason, the drain breakdown voltage was 6 to 12 V in the comparative example, whereas the variation in the drain breakdown voltage was 10 to 12 V in the above example, with small variations.
また、比較例のものは、熱処理時のひさしの部
分のパツシベーシヨンの不完全さに起因する不良
品率が非常に高かつたが、上記実施例のものにつ
いては、不良品はほとんどなかつた。 In addition, the comparative examples had a very high rate of defective products due to imperfection of the passivation of the eaves during heat treatment, but the samples of the above examples had almost no defective products.
本発明は上記実施例に限られない。例えばゲー
ト電極用金属膜はＷに限らず耐熱性でかつドライ
エツチングが可能な金属であればよく、Moや
WN、WSi等を用い得る。さらに耐エツチングマ
スクもAuに限らず、800℃の高温で下のゲート金
属と反応せず、ドライエツチングのマスクとなれ
ばよく、例えばPt等を用いてもよい。またSi3N4
膜の代りに同様の堆積法によるSiO2膜を用いる
ことができる。その他エツチングガスや膜の堆積
方法も所期の目的を達成できるものであれば、上
記実施例のものに限られない。 The present invention is not limited to the above embodiments. For example, the metal film for the gate electrode is not limited to W, but any metal that is heat resistant and can be dry etched may be used, such as Mo or
WN, WSi, etc. can be used. Further, the etching-resistant mask is not limited to Au, but may be made of Pt or the like as long as it does not react with the underlying gate metal at a high temperature of 800° C. and can be used as a dry etching mask. Also Si 3 N 4
Instead of the film, a SiO 2 film can be used by a similar deposition method. Other etching gases and film deposition methods are not limited to those of the above embodiments as long as they can achieve the intended purpose.
さらに上記実施例は基板がGaAsである場合に
ついて示したが、Siや他の化合物半導体について
も電極用金属やドナー不純物を変更するだけで適
用可能である。 Furthermore, although the above embodiments have been described for the case where the substrate is GaAs, the present invention can also be applied to Si or other compound semiconductors by simply changing the electrode metal or donor impurity.
第１図および第２図は従来法によるシヨツトキ
ーゲート型FETの断面図、第３図ａ〜ｆは本発
明の一実施例のシヨツトキーゲート型FETの製
造工程を示す断面図である。
１１……半絶縁性GaAs基板、１２……ｎ型
GaAs層、１３……Ｗ膜（ゲート電極）、１４……
Au膜（耐エツチングマスク）、１５……LPCVD
−Si3N4膜、１６……ソース領域、１７……ドレ
イン領域、１８，１９……オーミツク電極。
1 and 2 are sectional views of a Schottky gate type FET according to a conventional method, and FIGS. 3 a to 3 f are sectional views showing the manufacturing process of a Schottky gate type FET according to an embodiment of the present invention. . 11...Semi-insulating GaAs substrate, 12...n type
GaAs layer, 13... W film (gate electrode), 14...
Au film (etching resistant mask), 15...LPCVD
-Si 3 N 4 film, 16... source region, 17... drain region, 18, 19... ohmic electrode.
Claims (1)
ゲート金属膜を全面に形成する工程と、この金属
膜上に耐エツチングマスクを形成する工程と、異
方性ドライエツチング法で前記金属膜を選択的に
エツチング除去し、続いて等方性ドライエツチン
グ法により残された金属膜の側壁を後退させて前
記耐エツチングマスクのひさしを形成する工程
と、前記耐エツチングマスクを残した状態でステ
ツプカバレージのよい堆積法により全面に絶縁膜
を堆積する工程と、堆積した絶縁膜を異方性ドラ
イエツチング法によりエツチングして前記耐エツ
チングマスクのひさし下にのみ残置させる工程
と、残された絶縁膜と前記金属膜をマスクとして
イオン注入して低抵抗のソースおよびドレイン領
域を形成する工程と、これらソースおよびドレイ
ン領域にオーミツク電極を形成する工程とを具備
したことを特徴とするシヨツトキーゲート型電界
効果トランジスタの製造方法。 ２ 前記半導体基板は半絶縁性GaAs基体にｎ型
GaAs層を成長させたものであり、前記ゲート金
属膜はＷ膜であり、前記耐エツチングマスクは
Au膜であり、前記絶縁膜は減圧CVDによるSi3N4
膜であり、前記異方性ドライエツチング法はCF4
ガスを用いた反応性イオンエツチングであり、前
記等方性ドライエツチング法はCF4＋O2ガスを用
いたプラズマエツチングである特許請求の範囲第
１項記載のシヨツトキーゲート型電界効果トラン
ジスタの製造方法。[Scope of Claims] 1. A step of forming a gate metal film that forms a Schottky barrier on the entire surface of a semiconductor substrate, a step of forming an etching-resistant mask on this metal film, and a step of etching the metal by an anisotropic dry etching method. selectively removing the film by etching, and then receding the sidewalls of the remaining metal film by isotropic dry etching to form the eaves of the etching-resistant mask; and with the etching-resistant mask remaining. a step of depositing an insulating film over the entire surface by a deposition method with good step coverage; a step of etching the deposited insulating film by an anisotropic dry etching method to leave it only under the eaves of the etching-resistant mask; A Schottky gate comprising the steps of forming low-resistance source and drain regions by ion implantation using a film and the metal film as a mask, and forming ohmic electrodes on these source and drain regions. Method of manufacturing type field effect transistor. 2 The semiconductor substrate is a semi-insulating GaAs base with an n-type
A GaAs layer is grown, the gate metal film is a W film, and the etching-resistant mask is a
The insulating film is made of Si 3 N 4 by low pressure CVD.
The anisotropic dry etching method uses CF 4
Manufacturing a Schottky gate type field effect transistor according to claim 1, wherein the isotropic dry etching method is a reactive ion etching method using a gas, and the isotropic dry etching method is a plasma etching method using a CF 4 +O 2 gas. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20903182A JPS5999776A (en) | 1982-11-29 | 1982-11-29 | Manufacture of schottky gate type electric field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20903182A JPS5999776A (en) | 1982-11-29 | 1982-11-29 | Manufacture of schottky gate type electric field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5999776A JPS5999776A (en) | 1984-06-08 |
| JPS6246073B2 true JPS6246073B2 (en) | 1987-09-30 |
Family
ID=16566107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20903182A Granted JPS5999776A (en) | 1982-11-29 | 1982-11-29 | Manufacture of schottky gate type electric field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999776A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022071U (en) * | 1988-06-17 | 1990-01-09 | ||
| JPH0415108Y2 (en) * | 1987-01-12 | 1992-04-06 |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6081872A (en) * | 1983-10-11 | 1985-05-09 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPS6143481A (en) * | 1984-08-08 | 1986-03-03 | Oki Electric Ind Co Ltd | Manufacture of schottky gate field effect transistor |
| JPH0812868B2 (en) * | 1984-08-27 | 1996-02-07 | 沖電気工業株式会社 | Method for manufacturing compound semiconductor device |
| JPS6181672A (en) * | 1984-09-28 | 1986-04-25 | Nec Corp | Manufacture of semiconductor device |
| JPS6196735A (en) * | 1984-10-17 | 1986-05-15 | Toshiba Corp | Conductor pattern forming process |
| JPS61108175A (en) * | 1984-11-01 | 1986-05-26 | Toshiba Corp | Semiconductor device and manufacture thereof |
| EP0208795A1 (en) * | 1985-07-12 | 1987-01-21 | International Business Machines Corporation | Method of fabricating a self-aligned metal-semiconductor FET |
| JPS62156878A (en) * | 1985-12-28 | 1987-07-11 | Nec Corp | Semiconductor device |
| US4689869A (en) * | 1986-04-07 | 1987-09-01 | International Business Machines Corporation | Fabrication of insulated gate gallium arsenide FET with self-aligned source/drain and submicron channel length |
| JPS62243359A (en) * | 1986-04-15 | 1987-10-23 | Matsushita Electric Ind Co Ltd | Compound semiconductor device |
| JP2557432B2 (en) * | 1987-12-25 | 1996-11-27 | 富士通株式会社 | Field effect transistor |
| JP5098166B2 (en) * | 2005-12-12 | 2012-12-12 | 日亜化学工業株式会社 | Nitride semiconductor laser device and manufacturing method thereof |
-
1982
- 1982-11-29 JP JP20903182A patent/JPS5999776A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0415108Y2 (en) * | 1987-01-12 | 1992-04-06 | ||
| JPH022071U (en) * | 1988-06-17 | 1990-01-09 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5999776A (en) | 1984-06-08 |
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