JPS6143481A - Manufacture of schottky gate field effect transistor - Google Patents
Manufacture of schottky gate field effect transistorInfo
- Publication number
- JPS6143481A JPS6143481A JP16488084A JP16488084A JPS6143481A JP S6143481 A JPS6143481 A JP S6143481A JP 16488084 A JP16488084 A JP 16488084A JP 16488084 A JP16488084 A JP 16488084A JP S6143481 A JPS6143481 A JP S6143481A
- Authority
- JP
- Japan
- Prior art keywords
- film
- schottky gate
- gate
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 150000001875 compounds Chemical class 0.000 claims abstract description 11
- 238000005507 spraying Methods 0.000 claims abstract description 6
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000010030 laminating Methods 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 4
- 239000010937 tungsten Substances 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 4
- 239000002344 surface layer Substances 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 230000003213 activating effect Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はダート金属として高融点金属であるタングステ
ン（以下Ｗという）ｆ、用いたショットキダート電界効
果トランジスタ（以下ＦＥＴという）の製造方法に関す
るものである。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a Schottky dart field effect transistor (hereinafter referred to as FET) using tungsten (hereinafter referred to as W) f, which is a high melting point metal, as a dart metal. It is.
（従来の技術）
従来、化合物半導体基板とショットキ障壁を形成する金
属は多くの種類が知られ、その中でも特にＷは高融点で
低抵抗であるため良好なンヨットキ障壁を形成すること
のできる金属として知られている。半導体基板にＷ膜を
積層する方法は、文献特公昭４５−７３７４号公報に記
載されている。(Prior Art) Conventionally, many types of metals are known to form a Schottky barrier with a compound semiconductor substrate. Among them, W is a metal that can form a good Schottky barrier because of its high melting point and low resistance. Are known. A method for laminating a W film on a semiconductor substrate is described in Japanese Patent Publication No. 7374/1983.
一般にＷを半導体基板上に積層する方法は、ｗｌ熱分解
するか、まだは水素還元する化学蒸着法が用いられてい
る。Generally, W is deposited on a semiconductor substrate by thermal decomposition or chemical vapor deposition which involves hydrogen reduction.
（発明が解決しようとする問題点）
しかしながら、前述したようなＷ膜の積層方法では、化
合物半導体基板表面を洗浄してこの基板上にＷを積層し
ても、平坦に積層できなかったシ、Ｗ内に炭素や酸素が
混入して積層されＷの高融点で低抵抗であるという性質
を悪化させ、さらＫＷ−Ｇａ Ａ ｓのショットキ特性
を劣化させるという欠点があった。(Problems to be Solved by the Invention) However, in the above-described W film stacking method, even if the surface of a compound semiconductor substrate is cleaned and W is stacked on the substrate, the W film cannot be stacked flatly. There is a drawback that carbon and oxygen are mixed into W and are stacked, which deteriorates the high melting point and low resistance properties of W, and further deteriorates the Schottky characteristics of KW-GaAs.
（問題点を解決するための手段）
そこで本発明は、化合・物半・導体基板上に保護膜とし
てシリコン（以下Ｓｉという）を所定の厚さ積層し、こ
の表面にフッ化タングステン（以下瀞゛６という）ある
いは靜 と水素（以下Ｈ２という）とを吹き付けること
Ｋよシ、前記Ｓｉ膜を除去すると供に前記基板上にＷ膜
を積層し、とのＷ膜を・ぞターンニングすることによっ
てショットキゲート１形成したものである。(Means for Solving the Problems) Therefore, the present invention consists of laminating silicon (hereinafter referred to as Si) to a predetermined thickness as a protective film on a compound/compound semiconductor/conductor substrate, and depositing tungsten fluoride (hereinafter referred to as "Si") on the surface of this layer. (referred to as "6") or by spraying hydrogen (hereinafter referred to as H2), the Si film is removed, a W film is laminated on the substrate, and the W film is turned. The Schottky gate 1 was formed by the following method.
（作用）
この発明によれば以上のように、化合物半導体基板上に
Ｗ膜を積層する前にＳｉを積層し、この表面にＷＦ
あるいはｗＦ′６とＨ２とを吹き付け２ＷＦ ＋ ３
Ｓｉ ４３ＳｉＦ４＋ ２Ｗという安定な反応を利用し
てＷ膜を積層しているので平坦で低抵抗なＷ膜が積層で
きる。(Function) According to the present invention, as described above, Si is laminated before laminating the W film on the compound semiconductor substrate, and WF is applied to the surface of the Si layer.
Or spray wF'6 and H2 2WF + 3
Since the W film is stacked using the stable reaction of Si 43SiF4+ 2W, flat and low-resistance W films can be stacked.
（実施例）
第１図（ａ）〜（ｄ）は本発明の１実施例を説明するた
めのＦＥＴの断面図である。(Embodiment) FIGS. 1(a) to 1(d) are cross-sectional views of an FET for explaining one embodiment of the present invention.
まず第１図（、）に示すように、ＱａＡｓ半絶縁性基板
ｌにｎ型活性層２を形成し、Ｓｉ膜３を蒸着法によシ、
全面に１００Ｘ程度堆積させる。First, as shown in FIG. 1(,), an n-type active layer 2 is formed on a QaAs semi-insulating substrate l, and a Si film 3 is deposited by vapor deposition.
Deposit about 100X over the entire surface.
次に第１図（ｂ）に示すようにｗＦ′６とＨ２とを３５
０℃程度の温度にした基板１表面に吹き付けＷ膜４を析
出させる。ここでＷ６とＨ２とを吹き付けることによシ
、まず
２Ｗ６＋３Ｓｉ→３ ＳｉＦ４＋ ２Ｗという反応が生
じ、基板ｌ上のＳｉ膜が除去されると供にＷ膜が薄く析
出され、次に、
宵６＋Ｈ２→Ｗ＋６ＨＦ
という反応が生じ、所定の厚さまでＷ膜を析出させる。Next, as shown in FIG. 1(b), wF'6 and H2 are set to 35
A sprayed W film 4 is deposited on the surface of the substrate 1 at a temperature of about 0°C. By spraying W6 and H2 here, the reaction 2W6+3Si→3SiF4+ 2W occurs, and as the Si film on the substrate 1 is removed, a thin W film is deposited, and then, the reaction 2W6+3Si→3SiF4+ 2W occurs. A reaction of W+6HF occurs, and a W film is deposited to a predetermined thickness.
さらにイオン阻止能が高く、耐ドライエツチ性を有する
Ｎｉ膜をＷ膜３上積層し、ダート・七り ：一ンニ
ハターンニンクシテダートハタ」導体５を形成する。Further, a Ni film having high ion-blocking ability and dry etching resistance is laminated on the W film 3 to form a conductor 5.
次に第１図（ｃｌに示すように、ケ゛−ドパターン体５
をマスクとしてＷ膜４のエツチングを行いＷダート６を
形成し、ケ゛−ト・ぞターン体５とＷケ゛−トロとをマ
スクとし、てイオン注入することにより素子領域であっ
てケ゛−１領域でない領域にｎ＋領域７を形成し、ケ゛
−トハターン体５ｆ！：除去する。Next, as shown in FIG.
Using the W film 4 as a mask, the W film 4 is etched to form a W dirt 6. Using the gate/zoom body 5 and the W catheter as a mask, ions are implanted into the element region, which is the Key 1 region. An n+ region 7 is formed in the non-containing region, and a gate pattern body 5f! :Remove.
次にｎ領域７の活性化アニールを行ったのち、第１図（
ｄ）に示すように？領域７１１：にオーミック電極８を
形成する。Next, after activation annealing of the n region 7 is performed, as shown in FIG.
As shown in d)? An ohmic electrode 8 is formed in the region 711.
尚、本発明においてＳｉ膜３は蒸着法により積層したが
、スパッタ法等の他の積層方法と用いてもよい。In the present invention, the Si film 3 is laminated by vapor deposition, but other lamination methods such as sputtering may be used.
また、Ｗ膜４はｗＦ′６とＨ２とを表面に吹き付けて析
出したがＷＦ６のみを吹き付けることによってもＷ膜を
形成することができる。Furthermore, although the W film 4 was deposited by spraying wF'6 and H2 onto the surface, the W film can also be formed by spraying only WF6.
本発明の実施例によればＳｉ膜３が基板ｌの表面の保護
膜として働らき基板ｌ上に平坦で炭素や酸素等の不純物
を含まない低抵抗なＷ膜４を形成することができる。According to the embodiment of the present invention, the Si film 3 acts as a protective film on the surface of the substrate 1, and a flat W film 4 having low resistance and containing no impurities such as carbon or oxygen can be formed on the substrate 1.
さらに、ＳｉとｗＦ′６との反応を利用しているので、
荀゛６とＨ２との反応だけを利用したＷ膜の析出方法に
比べ、基板がより低温度の状態でもＷ膜４を析出するこ
とができる。Furthermore, since the reaction between Si and wF'6 is utilized,
Compared to a method for depositing a W film that utilizes only the reaction between the core 6 and H2, the W film 4 can be deposited even when the substrate is at a lower temperature.
（発明の効果）
以上、説明したようにこの発明によれば平坦で不純物を
含まない低抵抗な／ヨツトキク゛−トが比較的容易に形
成できる利点があり、よりよい特性のショットキゲート
ＦＩＩＥＴを製造することができる。(Effects of the Invention) As described above, the present invention has the advantage that a flat, impurity-free, low-resistance/cross-cut circuit can be formed relatively easily, and a Schottky gate FIIET with better characteristics can be manufactured. be able to.
第１図（、）〜（ｄ）は、本発明の１実施例を説明する
ためのＦＥＴの構造断面図である。
１・・・半絶縁性ＧａＡｓ基板、２・・・ｎ型活性層、
３・・・Ｓｉ膜、４・・・Ｗ膜、５・・・グートノ２タ
ーン体、６・・・Ｗゲート、７・・・ｎ領域、８・・・
オーミック電極。FIGS. 1(a) to 1(d) are structural sectional views of an FET for explaining one embodiment of the present invention. 1... Semi-insulating GaAs substrate, 2... N-type active layer,
3...Si film, 4...W film, 5...Gutno two-turn body, 6...W gate, 7...n region, 8...
Ohmic electrode.
Claims (1)
と、該活性層上にショットキ障壁をなすショットキゲー
トと、該活性層上であって該ショットキゲートの両側に
オーミック接触をなす電極とを備えたショットキゲート
電界効果トランジスタの製造方法において、 前記活性層を含む前記化合物半導体基体上に所定の厚さ
のシリコン膜を積層する工程と、該シリコン膜を積層し
た該化合物半導体基体にフッ化タングステンあるいはフ
ッ化タングステンと水素とを吹き付けることによシ該シ
リコン膜を除去するとともに該化合物半導体基体上にタ
ングステン膜を析出させる工程と、該タングステン膜を
パターンニングすることによりショットキゲートを形成
する工程とを備えてなることを特徴とするショットキゲ
ート電界効果トランジスタの製造方法。[Scope of Claims] A compound semiconductor substrate, an active layer on the surface layer of the compound semiconductor substrate, a Schottky gate forming a Schottky barrier on the active layer, and ohmic contacts on both sides of the Schottky gate on the active layer. A method for manufacturing a Schottky gate field effect transistor comprising a Schottky gate field effect transistor, comprising: laminating a silicon film of a predetermined thickness on the compound semiconductor substrate including the active layer; and the compound semiconductor substrate on which the silicon film is laminated. A step of removing the silicon film by spraying tungsten fluoride or tungsten fluoride and hydrogen on the substrate and depositing a tungsten film on the compound semiconductor substrate, and forming a Schottky gate by patterning the tungsten film. 1. A method of manufacturing a Schottky gate field effect transistor, comprising the step of forming a Schottky gate field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16488084A JPS6143481A (en) | 1984-08-08 | 1984-08-08 | Manufacture of schottky gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16488084A JPS6143481A (en) | 1984-08-08 | 1984-08-08 | Manufacture of schottky gate field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6143481A true JPS6143481A (en) | 1986-03-03 |
Family
ID=15801660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16488084A Pending JPS6143481A (en) | 1984-08-08 | 1984-08-08 | Manufacture of schottky gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6143481A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5050881A (en) * | 1973-09-04 | 1975-05-07 | ||
| JPS5776833A (en) * | 1980-09-04 | 1982-05-14 | Applied Materials Inc | Heat resistant metal depositing method and product thereof |
| JPS57152168A (en) * | 1981-03-13 | 1982-09-20 | Nec Corp | Manufacture of schottky barrier gate field effect transistor |
| JPS57152166A (en) * | 1981-03-13 | 1982-09-20 | Nec Corp | Manufacture of schottky barrier gate field effect transistor |
| JPS5999776A (en) * | 1982-11-29 | 1984-06-08 | Toshiba Corp | Manufacture of schottky gate type electric field effect transistor |
-
1984
- 1984-08-08 JP JP16488084A patent/JPS6143481A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5050881A (en) * | 1973-09-04 | 1975-05-07 | ||
| JPS5776833A (en) * | 1980-09-04 | 1982-05-14 | Applied Materials Inc | Heat resistant metal depositing method and product thereof |
| JPS57152168A (en) * | 1981-03-13 | 1982-09-20 | Nec Corp | Manufacture of schottky barrier gate field effect transistor |
| JPS57152166A (en) * | 1981-03-13 | 1982-09-20 | Nec Corp | Manufacture of schottky barrier gate field effect transistor |
| JPS5999776A (en) * | 1982-11-29 | 1984-06-08 | Toshiba Corp | Manufacture of schottky gate type electric field effect transistor |
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