JPS5999776A - Manufacture of schottky gate type electric field effect transistor - Google Patents

Abstract

PURPOSE:To form source and drain regions with low resistance by a method wherein a gate electrode metal is etched by means of assembling anisotropic and isotropic dry etching processes in this order to make a gate length a little shorter than the mask dimension and then the sides of an electrode metal are coated with an insulating film to implant ion in a substrate on both sides. CONSTITUTION:A W layer 13 with specified shape to be a gate electrode is formed on a semiinsulating GaAs substrate 11 with an n type GaAs active layer 12 and the W layer 13 is covered with an Au mask 14 and then anisotropic dry etching using gas and isotropic dry etching using mixed gas of CF4 and O2 are performed to leave an electrode 13 a little shorter than the mask 14 below the mask 14. Next overall surface is coated with an Si3N4 film 15 and the film 15 is left only on the sides of the electrode 13 under the mask 14 by means of anisotropic etching using CF4 gas to form source and drain regions 16, 17 by means of implanting Si<+> ion in the layer 12 on both sides. Through these procedures, an FET with high drain withstand voltage may be produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a so-called Schottky dart type field effect transistor using a Schottky barrier in the dirt.

[Technology, background and problems of the invention]

In a field effect transistor (FET) using a Schottky barrier in its gate, the dart length and the source series resistance existing between the source and the dart are major factors that determine its characteristics. That is, the gate length (t
g) and the signal propagation delay time (tpd) of the FET has the following relationship: tpd Cx-1g2 Therefore, the shorter 7g is, the smaller tpa becomes, and high-speed operation becomes possible. Regarding the source series resistance (Rs), if the intrinsic mutual conductance of the FET is gmo and the actual mutual conductance is gm, then there is a relationship as follows: gm = gmo / (1+4moRs), and the larger Rs is, the smaller the gm is. It ends up. Furthermore, between tg and gmo there are gmOoc l /, /
=g There is a relationship.

That is, in order to increase the operating speed of Ii''ET, it is necessary to shorten the dart length tg and reduce the source series resistance Ra. However, shortening the r-t length is difficult to achieve with conventional photoetching. Due to technical limitations, it is difficult to obtain a dart length of 1 μm or less.

Therefore, as shown in Fig. 1, the conventional method used is to form a dirt electrode 3 using heat-resistant goldfish, and using this as a mask, ions are implanted on both sides of the dart to form a highly concentrated layer. There is a method to reduce Rs by forming 4,5. In the figure, 1 is, for example, a semi-insulating GaAs substrate, and 2 is an n-type GaAs substrate.
It is a layer. However, in this method, the dirt capacitance becomes thicker and thicker due to the diffusion of impurities in the high-concentration layers 4 and 5 during annealing, and the dirt capacitance becomes thicker and thicker due to the presence of the first electrode 3 and the high-concentration layer 4゜b. Sweat is coming off as low as 4V.

As another example, as shown in Figure 2, the dart electrode 3
There is a method of shortening the gate length by over-etching when etching, and then using the photoresist 6, which is an etch mask, as it is as a mask for ion implantation to form a high concentration layer 4.5. . However, in this method, if a conventional wet etching method or an isotropic plasma etching method is used for etching the electrode, the amount of overetching will vary depending on the thickness distribution of the gold film. Precise control of dirt length is 11iff.
L. Furthermore, during ion implantation, the substrate is often tilted by 5 to 10 degrees in order to avoid the effect of in-plane tunneling. When this method is used, either the source region or the drain region is attached to the dart electrode There is also a possibility that they may end up being closer together than necessary.

[Purpose of the invention]

The present invention was developed in consideration of the above points, and it is possible to shorten the dart length to submicrons without using advanced phosphorography technology, and furthermore, the Schottky r-) type has low source series resistance and high drain breakdown voltage. FET'ff
:Provides a manufacturing method.

[Summary of the invention]

In summary, the present invention consists of: 1. By sequentially combining anisotropic and isotropic dry etching techniques in this order to etch the cathode metal film, it is possible to etch an etching film slightly smaller than the mask dimension with good controllability. Obtaining the gate length. Next, an insulating film is formed using a deposition method with excellent step coverage while leaving the mask, and after photo-etching, anisotropic dry etching is performed to extend the sides of the gate electrode, that is, the mask. The feature is that this P edge film is left only under the base plate, and in this state, low resistance source and drain regions are formed by ion implantation.

〔Effect of the invention〕

According to the present invention, the dart length can be shortened to 10 microns with good controllability by combining dry etching techniques. As a result of performing ion implantation with an insulating film placed on the side surface of the dirt electrode, it is possible to separate the dirt electrode and the source and drain regions by a very small distance with good controllability. A Schottky gate type FET that is capable of high-speed operation and has a high drain breakdown voltage can be obtained.

[Embodiments of the invention]

Hereinafter, an example using GaAs for the substrate will be explained in detail with reference to FIG. For example, chromium (Cr)
A tungsten (W) film 13 is used as a heat-resistant metal film to form a dirt electrode on the surface of a substrate in which an n-type GaAs layer 12 which becomes an active layer is grown on a semi-insulating GaAs substrate 11' doped with A gold 1 (Au) film 14 with a width of 1 μm and a thickness of about 200 mm is formed on the entire surface of the dirt electrode and the gap as an etching-resistant mask. Figure (a))'. At this time, Au film 1
If a lift-off method is used for the shunting of '4, a fine pattern can be formed with high precision.

Next, using the Au#J4 as a mask, the W film 13 is completely etched using a parallel plate reactive ion etching (RIE) device (FIG. 3(b)).

Etching gas: CF4, flow rate 20a
c/min.

The etching gas pressure was 0.05 Torr and the high frequency power was 200W. Under these conditions, the etching rate of the W film 13 is 300X/min, and the etching progresses with complete anisotropy. Note that the Au film 14 and the GaA's layer 12
The selection ratio of Kichi is 5 to 1. ~1 o and enough blades were obtained. And □o”Continuing from arE, it is a normal cylindrical plug”! 7'+: W film 13J' is etched using a notching device. A mixed gas of CF4 and 02 was used as the etching gas, each with a flow rate of 15 CC/'rn'in'.
+ ``5 CI:/'mi'n + Retaining gas pressure is 0.ITor'r, high frequency oil: force i +:' i
In a two-cylindrical plasma etching system with 0oW,
The W film 13 is etched unilaterally, and the etching rate is OOi/min. When etching is carried out for 20 minutes under these conditions 1F'', the Au film 14 and the GaAs layer 12 are not etched at all, and the side wall of the W film 14 temporarily retracts, causing the very large Δχ opening of the Au film j4 to become O, mm μm. It is formed (Fig. 3('c)).'
□□ After processing the side wall of the W film vertically using RIE, which is anisotropic dry etching, method of side etching using plasma etching using isotropic dry etching. Because we are taking
The amount of zide (ΔX) can be controlled very precisely.

Because it is a dry ethosing process, the uniformity within one wafer surface and between wafers is very good. for example,
In this state, when the dart length was measured over the entire surface of the 2-inch φ sea urchin, the dart length was 0.6 μm±005 μm even though the film thickness distribution of the W film was approximately ±700×.

At the same time, the eaves ΔX of the Au film has no fluctuation in the plane of 11 mm, and the distribution of ±0.05 μm is considered to be 9 variations in the Au film at the time the pattern is formed.

As mentioned above, the electrodeposition is formed and the nucleation is carried out by low pressure CV.
Si3N4 film 15 ~ 6 by D (LPCVD) method
000X deposit. Since this method has very good stain resistance, it is possible to completely remove the unevenness on the substrate with a force of N4- (Fig. 3(d)). After that, the entire surface is covered with CF4 gas.
Go through K1°. 2o result, 8. . A for anisotropy
The Si3N4 film 15 remains only under the eaves of the U film 14 (FIG. 3(e)).

In this state, 1.28st+ ions were added. Acceleration voltage 200ke
Ion implantation was carried out at a dose of 3×1013 6 and 8
Anneal for 15 minutes at 00-850°C to form low resistance source region 16. After forming the drain region 17, the source and drain regions J6. Ohmic electrodes 18 and 19 made of AuGe alloy were formed on Z 7 (see Fig. 3).
f)).

As a result, although the dart mask dimension is 1 μm, the actual dart length is as short as O: 6 μm, which is a sweet
The distance between the source, drain and dart is small at 0.2μm, and the source series resistance and dart capacitance are sufficiently small5, enabling high-speed operation! A high-performance FET was obtained in which the drain current Ef was equal to or higher than i''OV.Furthermore, the FET characteristics were highly uniform with little variation within the plane and between the substrates. .

As a comparative example, hi was applied to the Au film part in the above example.
Using the 2o, film, in the state shown in FIG. 3(e), ions were implanted, passivation was performed with 5IO2 by atmospheric pressure CVD, and heat treatment was performed to form an FET'i. Comparing this with the above embodiment, in the above embodiment, the resistance of the r7 electrode itself was about 30% lower, and the unevenness of the north series resistance was about 1/2 smaller. In the case of the comparative example, the variation in series resistance is thought to be due to the substrate being tilted by 7° during ion implantation, but Si 3N4 was applied to the side wall of the dart electrode.
In the above embodiment in which a film is formed, this 513N4 film serves as a mask for ion implantation, so even if the substrate is tilted, the variation remains small. Further, for the same reason, the drain breakdown voltage also showed small variations, being 6 to 12 V in the comparative example, and 10 to 12 V in the above example.

In addition, the comparative examples had a very high rate of defective products due to incomplete passivation of the eaves during heat treatment, while the samples of the above examples had almost no defective products.

The present invention is not limited to the above embodiments. For example, the metal film for the gate electrode is not limited to W, but any metal that is heat resistant and capable of dry etching may be used, and M, WN, or wst % may be used. Furthermore, the sequential etching mask is not limited to Au.
It is sufficient that it does not react with the underlying dirt metal at a high temperature of 00° C. and serves as a mask for dry etching, and for example, PT or the like may be used. In addition, 513N4 film was replaced with 5
A t02 film can be used. The etching gas and film deposition method are not limited to those of the above embodiments as long as they can achieve the intended purpose.

Further, although the above embodiments have been described with reference to the case where the substrate is GaAa, it is also possible to apply the present invention to -St or other compound semiconductors by simply changing the electrode metal or the donor impurity.

[Brief explanation of drawings]

FIGS. 1 and 2 are cross-sectional views of a Schottky dart type FET according to a conventional method, and FIGS. 3(a) to (f) are cross-sectional views showing the manufacturing process of a Schottky gate type FET according to an embodiment of the present invention. It is. 11- Semi-insulating GaAs substrate, 12- n-type GaA
s layer, 13...W film (dart electrode), 14...Au
Film (etching resistant mask), 15...LPCVD -
5t3N4 film, 16... Source region, 17... Drain region, 18°19... Ohmic electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3 L Figure 3

Claims (2)

[Claims] (1) A process of forming a dirt metal film to form a Schottky barrier on the entire surface of the semiconductor substrate, a process of forming an etching-resistant mask on this metal film, and selecting the metal film using an anisotropic dry etching method. a step of removing the metal film by etching, and then receding the side wall of the remaining metal film by an isotropic dry etching method to form the eaves of the etching-resistant mask; and a step with the etching-resistant mask remaining. a step of depositing an insulating film over the entire surface using a deposition method with good coverage; a step of etching the deposited insulating film using an anisotropic dry etching method to leave the remaining insulating film only under the eaves of the etching-resistant mask; and a step of forming a low-resistance source and drain/region by ion implantation using the metal film as a mask, and a step of forming an ohmic electrode in the source and drain regions. A method for manufacturing a Schottky dart field effect transistor. . (2) The semiconductor substrate is a semi-insulating GaAs base with an n-type GaAs layer grown on it, the gate metal film is a W film, and the etching-resistant mask is an Au film.
The insulating film is made of 513N4 by low pressure CVD.
The anisotropic dry etching method is reactive ion etching using CF4 gas, and the isotropic dry etching method is reactive ion etching using CF4 gas. 7 of Claim 1, which is glazma etching using +02 gas.
A method for manufacturing an Amatutkygut type field effect transformer.