JPH0812868B2 - Method for manufacturing compound semiconductor device - Google Patents
Method for manufacturing compound semiconductor deviceInfo
- Publication number
- JPH0812868B2 JPH0812868B2 JP59176835A JP17683584A JPH0812868B2 JP H0812868 B2 JPH0812868 B2 JP H0812868B2 JP 59176835 A JP59176835 A JP 59176835A JP 17683584 A JP17683584 A JP 17683584A JP H0812868 B2 JPH0812868 B2 JP H0812868B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- gaas
- schottky
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 150000001875 compounds Chemical class 0.000 title claims description 4
- 238000000034 method Methods 0.000 title description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 25
- 238000004544 sputter deposition Methods 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 description 33
- 238000007740 vapor deposition Methods 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 9
- 230000004913 activation Effects 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 101150097381 Mtor gene Proteins 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） この発明は化合物半導体素子の製造方法に関し、特に
GaAsショットキゲート電界効果トランジスタ（以下GaAs
MESFETという）の製造方法に関する。TECHNICAL FIELD The present invention relates to a method for producing a compound semiconductor device, and in particular,
GaAs Schottky gate field effect transistor (hereinafter GaAs
Called MESFET).
（従来の技術） GaAs MESFETの１つのタイプとして耐熱性金属ゲート
を用いたものが知られている。(Prior Art) As one type of GaAs MESFET, one using a heat-resistant metal gate is known.
耐熱性金属ゲートとして用いられるタングステン（以
下Ｗという）は、GaAs MESFETのイオン注入領域の活性
化熱処理にも耐えることができ、また低抵抗で良好なシ
ョットキ特性を示す。Ｗ膜は電子ビーム蒸着法によって
形成でき、また、特公昭44−18655号公報に記載されて
いるように、スパッタ法によっても形成できる。Tungsten (hereinafter referred to as W) used as a heat-resistant metal gate can withstand the activation heat treatment of the ion-implanted region of GaAs MESFET, has low resistance, and exhibits excellent Schottky characteristics. The W film can be formed by an electron beam vapor deposition method, and can also be formed by a sputtering method as described in JP-B-44-18655.
（発明が解決しようとする問題点） Ｗ膜の蒸着は、電子ビーム法よりもスパッタ法による
蒸着の方が容易であるけれども、蒸着条件によってGaAs
MESFETの特性は変動する欠点があった。(Problems to be Solved by the Invention) Although it is easier to deposit a W film by a sputtering method than by an electron beam method, GaAs may be deposited depending on the deposition conditions.
The characteristic of MESFET has the drawback that it fluctuates.
従ってこの発明の目的は、密着性、ショットキ特性及
び逆方向電流電圧特性などが良好なGaAs MESFETの製造
方法を提供することにある。Therefore, an object of the present invention is to provide a method of manufacturing a GaAs MESFET having good adhesion, Schottky characteristics, reverse current-voltage characteristics, and the like.
（問題点を解決するための手段） この発明はGaAs半導体基体のｎ型活性層とショットキ
障壁をなすＷ膜を、基板温度が100℃〜450℃、スパッタ
圧が1mTorr〜12mTorr、蒸着レートが毎分150Å〜1000Å
である条件下で、スパッタ蒸着し、選択的に除去するこ
とによりMESFETのショットキゲートを形成するものであ
る。(Means for Solving Problems) The present invention provides a W film that forms a Schottky barrier with an n-type active layer of a GaAs semiconductor substrate, a substrate temperature of 100 ° C. to 450 ° C., a sputtering pressure of 1 mTorr to 12 mTorr, and a deposition rate of Min 150Å ~ 1000Å
Under certain conditions, the Schottky gate of MESFET is formed by sputter deposition and selective removal.
（作用） GaAs MESFETの良好性を決める密着性、ショットキ特
性及び逆方向電流電圧特性などは多くの要因に影響され
るが、特にＷ膜のスパッタ蒸着時における基板温度、ス
パッタ圧力、蒸着レートが重要である。(Function) Adhesion, Schottky characteristics, and reverse current-voltage characteristics that determine the goodness of GaAs MESFETs are affected by many factors, but the substrate temperature, sputtering pressure, and deposition rate during W film sputtering deposition are particularly important. Is.
GaAs基体にショットキ障壁をなすＷ膜をスパッタ蒸着
法によって形成する場合、基体からのゲート金属膜の剥
離が生ずることがある。この原因はGaAs基体とＷ膜の密
着性や薄膜効果による内部応力に関係している。これら
の密着性や薄膜効果はスパッタ蒸着時の基体温度に影響
され、室温でＷ膜をGaAs基体に蒸着した場合約1000Å程
度膜厚のＷ膜のGaAs基体に対する引っ張り応力は1.7×1
010dyn/cm2であり、これに対し基体温度150℃で蒸着し
た場合９×109dyn/cm2と約半分に減少させることができ
る。しかし、さらに基体温度を上げると、基体中のAs原
子を蒸発させることになり、500℃以上においては、こ
の現象は顕著である。また蒸着時の基体温度はＷ膜の抵
抗率にも影響し、この抵抗率は、25℃では大きく、温度
を上げることにより低くなり、100℃以上の温度ではほ
ぼ一定となる。従ってGaAs基体にＷ膜をスパッタ蒸着す
る際の基体温度は、100℃〜450℃の温度領域が良い。When the W film forming the Schottky barrier is formed on the GaAs substrate by the sputter deposition method, the gate metal film may be separated from the substrate. This cause is related to the adhesion between the GaAs substrate and the W film and the internal stress due to the thin film effect. These adhesion and thin film effect are affected by the substrate temperature during sputter deposition, and when a W film is deposited on a GaAs substrate at room temperature, the tensile stress of a W film with a thickness of about 1000Å to a GaAs substrate is 1.7 × 1
It is 0 10 dyn / cm 2 , whereas in the case of vapor deposition at a substrate temperature of 150 ° C., it can be reduced to about half, which is 9 × 10 9 dyn / cm 2 . However, when the temperature of the substrate is further increased, As atoms in the substrate are vaporized, and this phenomenon is remarkable at 500 ° C. or higher. The substrate temperature during vapor deposition also affects the resistivity of the W film, which is large at 25 ° C., decreases with increasing temperature, and becomes almost constant at temperatures above 100 ° C. Therefore, the substrate temperature when the W film is sputter-deposited on the GaAs substrate is preferably in the temperature range of 100 ° C to 450 ° C.
またGaAs MESFETのショットキ特性は、スパッタ蒸着
時のスパッタ圧に影響される。第２図はスパッタ圧1mTo
rrと24mTorrとで蒸着したＷ膜を用いたショットキキ障
壁の800℃,15分の高温熱処理後の電流電圧特性を表わし
た図であり、GaAs基体のｎ型活性層とＷ膜との接触面積
は８×10-5cm2であり、Ｗ膜厚は1000Åである。第２図
よりスパッタ圧1mTorrで形成したＷ膜はｎ値が1.14、バ
リア高さφＢは0.72Vであり、これに対し24mTorrで形成
したＷ膜はｎ値が1.11、バリア高さφＢは0.66Vとな
り、1mTorrで形成した方がバリア高さは高く好ましい。
スパッタ圧24mTorr以下で形成したＷ膜のバリア高さφ
Ｂは、ｎ型活性層の活性化アニール温度の上昇にともな
ってゆるやかに高くなる。この活性化アニールは一般に
800℃程度で行われ、800℃の活性化アニールにおいて、
バリア高さφＢが0.7Vを越えるためにはスパッタ圧を12
mTorr以下にしなければならない。しかしながらスパッ
タ圧を0.5mTorr以下にした場合、スパッタ蒸着装置にお
けるプラズマの発生が困難となる。従ってGaAs MESFET
の良好なショットキ特性を形成するためのスパッタ圧は
0.5mTorr〜12mTorrの圧力範囲が良い。The Schottky characteristic of GaAs MESFET is affected by the sputtering pressure during sputter deposition. Figure 2 shows sputter pressure 1mTo
FIG. 3 is a diagram showing current-voltage characteristics of a Schottky barrier using a W film deposited with rr and 24 mTorr after high-temperature heat treatment at 800 ° C. for 15 minutes, showing the contact area between the n-type active layer of the GaAs substrate and the W film. Is 8 × 10 -5 cm 2 and the W film thickness is 1000Å. From Fig. 2, the n-value of the W film formed with a sputtering pressure of 1 mTorr is 1.14 and the barrier height φ B is 0.72 V, whereas the n-value of the W film formed with 24 mTorr is 1.11 and the barrier height φ B is It becomes 0.66V, and it is preferable to form it at 1 mTorr because the barrier height is high.
Barrier height φ of W film formed at a sputtering pressure of 24 mTorr or less
B gradually increases as the activation annealing temperature of the n-type active layer rises. This activation anneal is generally
It is performed at about 800 ℃, and at 800 ℃ activation annealing,
To increase the barrier height φ B to 0.7 V, the sputtering pressure must be 12
Must be less than or equal to mTorr. However, when the sputter pressure is set to 0.5 mTorr or less, it becomes difficult to generate plasma in the sputter deposition apparatus. Therefore GaAs MESFET
The sputtering pressure for forming good Schottky characteristics of
Good pressure range from 0.5mTorr to 12mTorr.
またスパッタ蒸着の蒸着レートは、逆方向電流電圧特
性に影響を与える。第３図はショットキゲートとなるＷ
膜のスパッタ蒸着レートを、毎分120Åと500Åで形成し
たGaAs MESFET電流電圧特性を示す図である。この図に
示されるように、蒸着レートは特に逆方向電流電圧特性
に影響を与え、120Å程度の低い蒸着レートで形成した
Ｗショットキゲートの逆方向特性は著しく劣化するの
で、蒸着レートは少なくとも150Å以上にする必要があ
る。このように蒸着レートは高い方が良いが、蒸着レー
ト毎分1000Å以上でＷ膜を形成した場合、Ｗ膜には著し
いピンホールが生じるため微細パターン形成には適しな
い。従って良好なGaAs MESFETを形成するにはＷ膜の蒸
着レートは毎分150Å〜1000Åが良い。In addition, the deposition rate of sputter deposition affects the reverse current-voltage characteristics. Figure 3 shows W as a Schottky gate
It is a figure which shows the GaAs MESFET current-voltage characteristic formed with the sputtering deposition rate of a film | membrane 120Å and 500Å / min. As shown in this figure, the vapor deposition rate particularly affects the reverse current-voltage characteristic, and the reverse characteristic of the W Schottky gate formed at a low vapor deposition rate of about 120 Å is significantly deteriorated, so the vapor deposition rate is at least 150 Å or more. Need to As described above, the higher the vapor deposition rate is, the better, but when the W film is formed at a vapor deposition rate of 1000 Å / min or more, remarkable pinholes are generated in the W film, which is not suitable for forming a fine pattern. Therefore, in order to form a good GaAs MESFET, the deposition rate of the W film is preferably 150Å to 1000Å / min.
（実施例） 第１図（ａ）〜（ｃ）本発明の実施例を説明するため
のGaAs MESFETの構造断面図であり、以下図面に沿って
説明する。(Embodiment) FIGS. 1A to 1C are structural cross-sectional views of a GaAs MESFET for explaining an embodiment of the present invention, which will be described below with reference to the drawings.
まず第１図（ａ）に示すように半絶縁性のGaAs基板１
の表面にｎ型活性層２を選択的に形成し、その上にスパ
ッタ装置を用いて、基板温度150℃、Arガスのスパッタ
圧1mTorr、蒸着レート毎分500Åの条件のもとに、Ｗ膜
３を1000Å程度蒸着する。First, as shown in FIG. 1 (a), a semi-insulating GaAs substrate 1
The n-type active layer 2 is selectively formed on the surface of the W film, and a W film is formed on the n-type active layer 2 under the conditions of a substrate temperature of 150 ° C., an Ar gas sputtering pressure of 1 mTorr, and a vapor deposition rate of 500 Å / min. Evaporate 3 to about 1000Å.
次に第１図（ｂ）で示すように、Ｗ膜３の上にNi等の
イオン阻止能のある金属のゲートパターン体４を形成
し、ゲートパターン体４をマスクとしてＷ膜３をサイド
エッチングしてゲート電極５を形成する。しかる後、ゲ
ートパターン体４をマスクとしてイオン注入することに
よりn+領域６を形成し、ゲートパターン体４を除去す
る。しかる後、表面にプラズマCVD法により図示しないS
i3N4膜を1000Å程度厚さに被覆し、As圧雰囲気中で800
℃、20分のn+領域６の活性化アニールを行い、このSi3N
4膜を除去する。Next, as shown in FIG. 1B, a gate pattern body 4 made of a metal having an ion blocking ability such as Ni is formed on the W film 3 and the W film 3 is side-etched using the gate pattern body 4 as a mask. Then, the gate electrode 5 is formed. Thereafter, the gate pattern body 4 is used as a mask to perform ion implantation to form an n + region 6, and the gate pattern body 4 is removed. After that, S (not shown) is formed on the surface by the plasma CVD method.
i 3 N 4 film is coated to a thickness of about 1000Å, and 800
° C., subjected to activation annealing of the n + region 6 of the 20 minutes, the Si 3 N
4 Remove the film.
次に第１図（ｃ）で示すように、n+領域上にオーミッ
ク電極７を形成し、GaAs MESFETを得る。Next, as shown in FIG. 1C, an ohmic electrode 7 is formed on the n + region to obtain a GaAs MESFET.
本発明の実施例によれば、ショットキ障壁をなすＷ膜
３を、基板温度150℃、スパッタ圧1mTorr、蒸着レート
毎分500Åで、スパッタ蒸着しているので、基板１から
ゲート電極５の剥離を防ぎ、ショットキ特性や逆方向電
流電圧特性の良好なGaAs MESFETを得ることができる。According to the embodiment of the present invention, the W film 3 forming the Schottky barrier is sputter-deposited at the substrate temperature of 150 ° C., the sputter pressure of 1 mTorr, and the deposition rate of 500 Å / min. It is possible to obtain a GaAs MESFET having excellent Schottky characteristics and reverse current-voltage characteristics.
また本発明の実施例ではアニール時の保護膜として、
プラズマCVD法により形成したSi3N4膜を用いているの
で、第１表に示すような良好なショットキ特性を示す。In the embodiment of the present invention, as a protective film during annealing,
Since the Si 3 N 4 film formed by the plasma CVD method is used, it exhibits good Schottky characteristics as shown in Table 1.
（発明の効果） この発明は以上説明したように、GaAs基体のｎ型活性
層上にスパッタ装置を用いて、基板温度150℃、Arガス
のスパッタ圧1mTorr、蒸着レート毎分500Åの条件のも
とにＷ膜を形成し、このＷ膜を選択除去してショットキ
ゲートを形成しているので、密着性、ショットキ特性及
び逆方向電流電圧特性などが良好なGaAs MESFETを得る
ことができる。 (Effects of the Invention) As described above, the present invention uses a sputtering apparatus on the n-type active layer of a GaAs substrate and uses a substrate temperature of 150 ° C., an Ar gas sputtering pressure of 1 mTorr, and a vapor deposition rate of 500Å / min. Since the W film is formed at the same time and the W film is selectively removed to form the Schottky gate, it is possible to obtain a GaAs MESFET having excellent adhesion, Schottky characteristics, reverse current-voltage characteristics, and the like.
第１図（ａ）〜（ｃ）は本発明の１実施例を説明するた
めの構造断面図、第２図はスパッタ圧を1mTorrと24mTor
rとで蒸着したＷショットキゲートFETの電流電圧特性を
表わす図、第３図は、スパッタ蒸着レートを毎分120Å
と500Åとで蒸着したＷショットキゲートFETの電流電圧
特性を表わす図である。 １……GaAs基板、２……ｎ型活性層、３……Ｗ膜、４…
…ゲートパターン体、５……ゲート電極、６……n+領
域、７……オーミック電極。1 (a) to 1 (c) are structural cross-sectional views for explaining one embodiment of the present invention, and FIG. 2 shows sputter pressures of 1 mTorr and 24 mTor.
Fig. 3 shows the current-voltage characteristics of W Schottky gate FETs deposited with r and Fig. 3. The sputtering deposition rate is 120Å / min.
It is a figure showing the current-voltage characteristic of W Schottky gate FET vapor-deposited by and 500Å. 1 ... GaAs substrate, 2 ... n-type active layer, 3 ... W film, 4 ...
… Gate pattern, 5 …… gate electrode, 6 …… n + region, 7 …… ohmic electrode.
フロントページの続き (56)参考文献 特開 昭57−152166（ＪＰ，Ａ) 特開 昭57−152168（ＪＰ，Ａ) 特開 昭59−99776（ＪＰ，Ａ) 特開 昭56−147434（ＪＰ，Ａ) 特開 昭58−177469（ＪＰ，Ａ)Continuation of the front page (56) Reference JP-A-57-152166 (JP, A) JP-A-57-152168 (JP, A) JP-A-59-99776 (JP, A) JP-A-56-147434 (JP , A) JP-A-58-177469 (JP, A)
Claims (1)
該GaAs基板にタングステンからなるゲート金属膜をスパ
ッタリング法により被着し、該ゲート金属膜を選択的に
除去してショットキゲート電極を形成する工程と、該シ
ョットキゲート電極の両側にオーミック電極を形成する
工程とを備えた化合物半導体素子の製造方法において、 前記スパッタリング法を、基板温度を100℃〜450℃、ス
パッタ圧を0.5mTorr〜12mTorr、被着レートを150Å／分
〜1000Å／分の条件下で行うことを特徴とする化合物半
導体素子の製造方法。1. A step of forming an n-type active layer on a GaAs substrate,
A step of forming a Schottky gate electrode by depositing a gate metal film made of tungsten on the GaAs substrate by a sputtering method, and selectively removing the gate metal film, and forming ohmic electrodes on both sides of the Schottky gate electrode. In the method for producing a compound semiconductor device comprising a step, the sputtering method, substrate temperature 100 ℃ ~ 450 ℃, sputter pressure 0.5mTorr ~ 12mTorr, deposition rate 150 Å / min ~ 1000 Å / min under the conditions A method of manufacturing a compound semiconductor device, which comprises:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59176835A JPH0812868B2 (en) | 1984-08-27 | 1984-08-27 | Method for manufacturing compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59176835A JPH0812868B2 (en) | 1984-08-27 | 1984-08-27 | Method for manufacturing compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6155966A JPS6155966A (en) | 1986-03-20 |
| JPH0812868B2 true JPH0812868B2 (en) | 1996-02-07 |
Family
ID=16020666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59176835A Expired - Lifetime JPH0812868B2 (en) | 1984-08-27 | 1984-08-27 | Method for manufacturing compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812868B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56147434A (en) * | 1980-04-18 | 1981-11-16 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPS57152168A (en) * | 1981-03-13 | 1982-09-20 | Nec Corp | Manufacture of schottky barrier gate field effect transistor |
| JPS57152166A (en) * | 1981-03-13 | 1982-09-20 | Nec Corp | Manufacture of schottky barrier gate field effect transistor |
| JPS58177469A (en) * | 1982-04-09 | 1983-10-18 | Fujitsu Ltd | Method and device for formation of thin film |
| JPS5999776A (en) * | 1982-11-29 | 1984-06-08 | Toshiba Corp | Manufacture of schottky gate type electric field effect transistor |
-
1984
- 1984-08-27 JP JP59176835A patent/JPH0812868B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6155966A (en) | 1986-03-20 |
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