JPH0551177B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and more specifically to a GaAs shot gate field effect transistor (GaAs MESFET) for microwave use using a shot barrier junction as a gate electrode.
This invention relates to an improvement in the manufacturing method of.

[Conventional technology]

GaAs MESFETs have already been put into practical use as microwave transistors that break through the characteristic limits of Si bipolar transistors. Like this
The high-frequency characteristics of GaAs MESFETs can be improved by shortening the gate length and reducing parasitic resistance. Therefore, a gate length of 0.5 to 1.0 μm is usually used in a GaAs MESFET for the C to X band. Conventionally, a gate with a short gate like this
GaAs MESFETs are made using the following method.
That is, as shown in FIG. 2a, an n-type GaAs active layer 211 formed on a semi-insulating GaAs substrate 210
A photoresist 212 having an opening of 0.5 to 1.0 μm is provided on the surface, and in order to reduce the source resistance and improve the drain breakdown voltage, the active layer 211 at the opening is dug by chemical etching (recess formation), and then directly above the photoresist 212 is formed. After forming a gate electrode 214 by a so-called lift-off method in which a shot metal 213 is vapor-deposited over the entire surface and the photoresist 212 is removed to leave the metal only in the opening, a source electrode 215 and a drain electrode are formed as shown in FIG. 2b. 216
By depositing and lifting off an ohmic metal in the same manner as in Fig. 2a,
This is a method to obtain the basic structure of GaAs MESFET.

[Problem that the invention seeks to solve]

However, such conventional methods have the following drawbacks. In other words, in the lift-off method, the gate metal is deposited with the organic photoresist attached, so heating the substrate at a temperature sufficient to remove moisture adhering to the surface of the active layer causes deformation of the resist pattern. In addition, impurities evaporate from the photoresist and contaminate the GaAs surface, making it difficult to obtain good shot characteristics with good reproducibility. Also, the finer the pattern, the more difficult it is for the etching solution to enter during the recess formation process.
The saturation drain current I _DSS increases as the gate length decreases.
The disadvantage is that the variation within the wafer surface becomes large. Furthermore, in the conventional method, an increase in gate resistance is unavoidable as the gate length is shortened, and this impedes an increase in gain and efficiency. Further, providing the source and drain electrodes close to the gate electrode requires mask alignment, but misalignment occurs when this mask alignment is performed. This misalignment is not reproducible, and the direction and magnitude vary each time. This misalignment directly affects the source resistance, etc., and can affect high frequency characteristics. That is,
There is a drawback that the device characteristics are greatly affected by the alignment accuracy of the mask.

An object of the present invention is to provide a new method for manufacturing field effect transistors that eliminates these conventional drawbacks.

[Means for solving problems]

The method for manufacturing a field effect transistor of the present invention includes:
After forming a first insulating film in which the source, drain, and gate electrode forming portions are selectively opened on the semiconductor active layer on the semi-insulating semiconductor substrate, only the gate electrode forming portions are opened from the first insulating film. A step of coating with a second insulating film having a high etching rate, and forming a low resistance semiconductor layer on the source and drain electrode forming portions using the first and second insulating films as masks, and then forming the second insulating film. selectively removing the metal, and then depositing a metal on the entire surface to form a shot junction with the semiconductor active layer, selectively covering the gate electrode forming part with photoresist, and removing the exposed unnecessary metal. By doing so, the method includes the step of forming a gate electrode having a T-shaped cross section in the opening of the gate electrode forming portion.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In this example, C to X band
This will be explained in detail using GaAs MESFET as an example.

FIGS. 1A to 1G are sectional views of main parts shown in order of manufacturing steps to explain an embodiment of the present invention.

As shown in Figure 1a, first the semi-insulating
An n-type GaAs operating layer 11 (electron concentration n10 ¹⁷ cm ^-3 , thickness t0.2 μm) is epitaxially grown on a GaAs substrate 10, and a plasma CVDSiN film 12 that will serve as a mask when forming a gate electrode later is formed on it, for example. Form to a thickness of approximately 0.2 μm. When forming the SiN film 12, for the purpose of increasing the etching selectivity in the buffer HF (HF: 6NH ₄ F) with the SiO ₂ film 17 to be formed later and providing a masking effect,
As an example, the substrate temperature is 350° C., N ₂ , NH ₃ , and SiH ₄ gases are flowed into 70, 6, and 6 SCCM reaction chambers, respectively, and the reaction chamber pressure is 1 Torr and RF power is 100 W. The etching rate of the SiN film 12 formed under these conditions in buffer HF was approximately 100
Å/min, and that of the SiO ₂ film 17 to be formed later is approximately 6000 Å/min.

Next, a photoresist (for example,
After coating Shipley's trademark AZ1350, the opening width of the gate electrode forming portion 13 is approximately 0.5 μm, for example, and the source electrode forming portion 14 is formed by a normal photo process.
For example, the distance between the drain electrode forming portion 15 and the drain electrode forming portion 15 is approximately
The photoresist layer 16 is patterned to have a thickness of 2.5 μm. Next, using the photoresist layer 16 as a mask, the SiN film 12 is etched by reactive ion etching (RIE) using CF ₄ gas to expose the active layer 11 . After removing the photoresist layer 16, the entire surface is covered, as shown in FIG. 1b.
Cover with a CVDSiO ₂ film 17 (eg, about 0.2 μm thick). The SiO ₂ film 17 is formed by a conventional thermal decomposition method using SiH ₄ and O ₂ gas at a substrate temperature of 400°C.
Next, as shown in FIG.
3 is selectively covered with a photoresist (for example, AZ1350 manufactured by Shipley) 18, and then etched by the RIE described above to expose the active layer 11 of the source and drain electrode forming portions 14 and 15 (FIG. 1d). ).

Next, a low-resistance GaAs layer (n ⁺ layer) 1 with an electron concentration of approximately 2×10 ¹⁸ cm ^-3 is grown using hydride vapor phase epitaxy.
9 is formed to have a thickness of about 0.2 μm, for example. At this time
The n ⁺ layer 19 does not grow on the SiO ₂ film 17 or the SiH film 12 at all, but grows faithfully in accordance with the pattern of the SiO ₂ film 17. This n ⁺ layer 19 functions to reduce the contact resistance of the source and drain electrodes that will be formed later and to alleviate electric field concentration at the end of the drain electrode. Next, SiO ₂ film using buffer HF17
remove. At this time, the etching speed of the SiO film 12 is slow, about 1/60, so it is hardly etched.
Only the SiO ₂ film 17 is selectively removed. next,
As shown in FIG. 1f, for example, Al20 is deposited over the entire surface as a metal forming a shot junction with the active layer. At this time, in order to obtain good shottability characteristics, it is desirable to heat the substrate to about 200° C. before depositing Al20. Next, the gate electrode forming portion 13
selectively covered with photoresist (AZ1350) 21,
By removing unnecessary Al using an H ₃ PO ₄ based etching solution, a gate electrode 22 having a T-shaped cross section as shown in FIG. 1g is formed. Finally, as a metal for forming an ohmic contact with the n ⁺ layer 19 by a normal photo process, for example,
After depositing and lifting off AuGe/Ni, alloying is performed to form a source electrode 23 and a drain electrode 24 with low contact resistance, thereby completing the basic structure of a GaAs MESFET as shown in FIG. 1g.

In the above embodiments, the case where Al is used as the gate metal has been described, but it goes without saying that other heat-resistant gate metals such as TiW, NSi, etc. can be used in the same way.

〔Effect of the invention〕

As explained above, according to the present invention
By using the GaAs MESFET manufacturing method, the inorganic SiN film and SiO ₂ film serve as a mask during gate formation, making it possible to heat the substrate to a sufficient temperature before gate metal evaporation. Since there is no evaporation of impurities or contamination, not only can good shot characteristics be obtained with good reproducibility, but also a fine gate electrode with a T-shaped cross section can be formed, making it possible to significantly reduce gate resistance. In addition, since the distance between the source, drain, and gate electrodes is determined by a single photomask, regardless of the mask alignment accuracy, it is possible to eliminate the variations in characteristics caused by misalignment that conventionally occur. Furthermore, the introduction of a selective n ⁺ layer eliminates the need for conventional recess formation, which suppresses deterioration of the uniformity of the saturated drain current across the wafer surface, resulting in excellent high-frequency characteristics and uniform characteristics. It has become possible to mass produce devices with good reproducibility.

[Brief explanation of the drawing]

Figures 1a to 1g are cross-sectional views of the main parts of the device in the main steps shown in order to explain one embodiment of the present invention, and Figures 2a and b are conventional GaAs MESFETs.
FIG. 3 is a cross-sectional view of a main part of the device in main steps shown in the order of steps to explain the manufacturing method of the device. 10...Semi-insulating GaAs substrate, 11...n type
GaAs operating layer, 12...SiN film, 13...gate electrode forming part, 14...source electrode forming part, 1
5... Drain electrode forming part, 16... Photoresist, 17... SiO ₂ film, 18... Photoresist,
19...n ⁺ layer, 20...Al, 21...photoresist, 22...gate electrode, 23...source electrode, 24...drain electrode, 210...semi-insulating
GaAs substrate, 211... n-type GaAs operating layer, 21
2...Photoresist, 213...Shot metal, 214...Gate electrode, 215...Source electrode, 216...Drain electrode.

Claims (1)

[Scope of Claims] 1. After forming a first insulating film in which source, drain, and gate electrode forming portions are selectively opened on a semiconductor active layer on a semi-insulating semiconductor substrate, only the gate electrode forming portion is formed. A step of coating with a second insulating film having a higher etching rate than the first insulating film, and forming a low resistance semiconductor layer in the source and drain electrode forming portions using the first and second insulating films as masks. , selectively removing the second insulating film, and then depositing a metal on the entire surface to form a shot junction with the semiconductor active layer; and selectively covering the gate electrode forming portion with photoresist and exposing it. forming a gate electrode having a T-shaped cross section in the opening of the gate electrode forming portion by removing the unnecessary metal. 2. The first insulating film is a plasma CVDSiN film,
2. The method of manufacturing a field effect transistor according to claim 1, wherein the second insulating film is a CVDSiO ₂ film.