JPS62190771A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To form a gate electrode with a T-shaped cross-section, and to eliminate the dispersion of characteristics due to the displacement of positioning by forming a first insulating film, in which source-drain and gate electrode forming sections are bored selectively, onto a semiconductor operating layer and removing an exposed unnecessary metal through a specific process. CONSTITUTION:A photo-resist layer 16 is patterned through a normal photo- process so that the opening width of a gate-electrode forming section 13 takes a value such as approximately 0.5mum and a space between a source-electrode forming section 14 and a drain-electrode forming section 15 a value such as approximately 2.5mum. The photo-resist layer 16 is removed, and the whole surface is coated with a CVDSiO2 film 17. The gate-electrode forming section 13 is coated selectively with a photo-resist 18, and operating layers 11 in the source and drain electrode forming sections 14, 15 are exposed through etching. A low-resistance GaAs layer 19 is shaped, and a metal forming a Schottky junction with the operating layer such as Al 20 is evaporated on the whole surface. The gate-electrode forming section 13 is coated selectively with a photo- resist 21, and unnecessary Al is removed by using an etching liquid, thus shaping a gate electrode 22 with a T-shaped cross-section.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and more specifically to a method for manufacturing a field effect transistor of the microwave phase GaAs Schottky type field effect transistor (GaAsM field effect transistor) using a Schottky barrier junction as a gate electrode. ]n8FET).

[Conventional technology]

G a As ME S F ET is Si A (
Ho/F I has already been put into practical use as a microwave transistor that breaks through the characteristic limits of Lancistors. Such a noble dl 4 of GaAsME8FET? The performance can be improved by shortening the gate length and reducing parasitic resistance. GaAsMB8FET for C~X band
Generally, a gate length of 0.5 to 1.0 μm is used. Conventionally, G with such a short gate
The aAsME8FET is manufactured in the following manner. That is, as shown in FIG. 2(a), semi-insulating G a A
ngGaAll operating layer 21 formed on the s-substrate 210
A photoresist 212 having an opening of 0.5 to 1.0 μm is provided on one surface, and the active layer 211 at the opening is dug by chemical etching (recess formation) in order to reduce source resistance and improve drain breakdown voltage. Thereafter, a gate electrode 213 is deposited on the entire surface from directly above, and the photoresist 212 is removed (thereby leaving the metal only in the openings, a so-called lift-off method is used to form a gate electrode 214, and then a second gate electrode 214 is formed.
As shown in FIG. 2(b), the source electrode 215 and the drain electrode 216 are formed by vapor-depositing ohmic metal in the same manner as in FIG. 2(a).
By lift-off and forming, GaAsME8F
This is a method to obtain the basic structure of ET.

[Problems to be Solved by the Invention] However, such conventional methods have the following drawbacks. That is, in the 1J7 to-off method, the gate metal is deposited with an organic photoresist attached, so heating the substrate at a temperature sufficient to remove moisture adhering to the surface of the active layer causes deformation of the resist pattern. In addition, impurities evaporate from the photoresist and contaminate the GaAs surface, making it impossible to obtain good etching characteristics with good reproducibility.Also, the finer the pattern, the more the etching solution is used in the recess formation process. Therefore, as the gate length is shortened, the variation in the saturation drain current In5s within the wafer surface becomes larger. This prevents high gain and high efficiency.Furthermore, providing source and drain electrodes close to the gate electrode requires mask alignment; This misalignment is not reproducible (and the direction and size vary each time. This misalignment directly affects the source resistance, etc., and causes variations in high frequency characteristics. In other words, it depends on the mask alignment accuracy. This has the disadvantage that device characteristics are greatly affected.

An object of the present invention is to provide a new method for manufacturing field effect transistors that eliminates these conventional drawbacks.

[Means for solving problems]

A method of manufacturing a field effect transistor according to the present invention is as follows.

Source on semiconductor active layer on semi-insulating semiconductor substrate.

After forming a first insulating film selectively opening the drain and gate electrode forming portions, a second insulating film having a higher etching rate than the first insulating film is etched only for the gate electrode forming portions.
and a step of covering with an insulating film.

After forming a low resistance semiconductor layer in the source and drain electrode formation portions using the first and second insulating films as masks, the second insulating film is selectively removed, and then the semiconductor active layer and the semiconductor layer are formed. The opening of the gate electrode formation area is formed by applying the metal that forms the Schittke junction over the entire surface, selectively covering the gate electrode formation area with photoresist, and removing the exposed unnecessary metal. and forming a gate electrode having a T-shaped cross section.

〔Example〕

An embodiment of the present invention will be described below with reference to one drawing. This embodiment will be explained in detail by taking C-X band GaAsME8PET as an example.

FIGS. 1(a) to 1(g) are sectional views of main parts shown in order of manufacturing steps to explain one embodiment of the present invention.

i1 As shown in Figure (a), first, semi-insulating GaA
An n-type GaAs operating layer 11 (electron concentration n
':: 10 "[-" l thickness t':: 0.2μ weight)
is epitaxially grown, and a plasma CVD 8iN film 12 having a thickness of, for example, about 0.2 μm is formed thereon to serve as a mask when forming a gate electrode later. When forming the 8iN film 12, for the purpose of increasing the etching selectivity in the buffer HF (HF: 6NH4F) with the 5ins film 17 to be formed later and providing a masking effect, for example, Nz and NHs were used at a substrate temperature of 350°C.

8iHa gas was flowed into 70, 6, and 6 SCCM reaction chambers under the conditions of a pressure of one reaction chamber of ITorr and an RF power of 100 W. 8iN film 1 formed under these conditions
buffer f of 2 (the etching rate in F is about 10
9 K7min, and 8i0z film 1 to be formed later
7 is about 60001/min.

Next, a photoresist (for example, 5hip) is applied on the 8iN film 12.
After coating AZ1350 (Trademark AZ1350 of Ley Corporation), the width of the opening of the gate electrode forming portion 13 is approximately 0.5 μm, for example, and the distance between the source electrode forming portion 14 and the drain electrode forming portion 15 is approximately 2.0 μm, for example, by a normal photo process. The photoresist layer 16 is patterned to have a thickness of 5 μm. Next, using the photoresist layer 16 as a mask, SiN was etched by reactive ion etching (RIE) using CF4 gas.
Film 12 is etched to expose active layer 11. After removing the photoresist layer 16, the entire surface is coated with CV D S 1OzlIfi 17 (eg, about 0.2 μm thick), as shown in FIG. 1(b). The 8i0z film 17 is formed by a conventional thermal decomposition method using 8iHi and 02 gas at a substrate temperature of 400°C. Next, as shown in FIG. 1C, the gate electrode forming portion 13 is selectively covered with a photoresist (for example, 5hipley Z1350) 18, and then the source and drain electrodes are etched using the RIB described above. Active layer 1 of forming part 14.15
1 (Fig. 1(d)).

Next, using the hydride vapor phase epitaxy method, the electron concentration was reduced to approximately 2.
A low resistance GaAs layer (n+ layer) 19 of X 1G "7" is formed to have a thickness of about 0.2 μm, for example. This tn+ layer 19 does not grow at all on the 8i (h film 17 and 8iN film 12), but grows faithfully according to the pattern of the 8i0z film 17. The SiOx film 17 is removed using the buffer IF.At this time, the etching rate of the 8iN film 12 is approximately 1/60. Since it is slow, only the 8i0z film 17 is selectively removed without being etched.

Next, as shown in FIG. 1(f), for example, Al2O is vapor-deposited over the entire surface as a metal forming a Vvs-Stock junction with the active layer. At this time, A! 2
It is desirable to heat the substrate to about 200° C. before evaporation. Next, the gate electrode forming portion 13 is selectively covered with a photoresist (AZ1350) 21, and unnecessary AI is removed using an HsPO4-based etching solution, so that a cross-sectional shape as shown in FIG. 1(g) is obtained. A T-shaped gate electrode 22 is formed. Finally, 5, by depositing, for example, AuGe/Ni as a metal to form an ohmic contact with the n+ layer 19 by a normal photo process, and after lift-off, alloying is performed to form a source electrode 23 and a drain electrode 24 with low contact resistance. The basic structure of a GaAs ME8FET as shown in FIG. 1 (gl) is completed.

In one or more embodiments, the gate metal is AI! Although we have explained the case using other heat-resistant gate metals 1
Of course, it is also possible to use TiW, WSi, etc., for example.

〔Effect of the invention〕

As explained above, GaAsME8FE according to the present invention
If the manufacturing method of T is used, the inorganic SiN film and 8 ioz film serve as a mask during gate formation.
It is possible to heat the substrate to a sufficient temperature before gate metal deposition, preventing the evaporation of impurities from the photoresist as in conventional methods.
Since there is no contamination, good shuttling characteristics are achieved with good reproducibility (
Not only that, but also a fine gate electrode with a single-shaped cross section can be formed, which makes it possible to significantly reduce gate resistance, and the distance between the source, drain, and gate electrodes depends on the mask alignment accuracy. Related (,1
Since the determination is made using a single photomask, it is possible to eliminate the variation in characteristics due to misalignment that previously occurred.Furthermore, by introducing the selective n layer, the conventional recess formation is no longer necessary, so the saturation drain can be reduced. Since deterioration in the uniformity of current across the wafer surface can be suppressed, it has become possible to mass-produce elements with excellent high-frequency characteristics and uniform characteristics with good reproducibility.

[Brief explanation of drawings]

Figures 1 (a) to (g) are cross-sectional views of the main parts of the element in the main steps shown in order to explain one embodiment of the present invention, and Figures 2 (a) and (b) are conventional GaAsMB
FIG. 2 is a cross-sectional view of a main part of the element in main steps shown in the order of steps to explain the manufacturing method of the 8FET. 10... Semi-insulating Ga As substrate, 11...
. . . n-type GaAs operating layer, 12 . . . 8iN film, 13 . . . gate electrode forming part, 14 .
-・Source electrode forming part. 15... Drain electrode forming part, 16...
...Photoresist, 17...--8i0z film, 18
・−・・Photoresist, 19・・・・n+ layer,
20...AI, 21...photoresist, 22...gate electrode, 23...source electrode, 24...drain electrode, 21O... −・
...Semi-insulating GaAs substrate, 211...N-type GaAs operating layer, 212...Photoresist, 2
13...Shitki metal, 214...
Gate electrode, 215...Source electrode, 216.
...Drain electrode. $1 group

Claims (2)

[Claims] (1) After forming a first insulating film in which the source, drain, and gate electrode forming portions are selectively opened on the semiconductor active layer on the semi-insulating semiconductor substrate, only the gate electrode forming portions are opened in the first insulating film. A step of coating with a second insulating film having a higher etching rate than the insulating film, and forming a low-resistance semiconductor layer in the source and drain electrode forming portions using the first and second insulating films as masks, and then forming the second insulating film. selectively removing the insulating film, and then depositing a metal on the entire surface to form a Schottky junction with the semiconductor active layer, and selectively covering the gate electrode forming portion with photoresist, removing the exposed unnecessary portion of the insulating film. A method for manufacturing a field effect transistor, comprising the step of forming a gate electrode having a T-shaped cross section in the opening of the gate electrode forming portion by removing metal. (2) the first insulating film is a plasma CVDSiN film;
2. The method for manufacturing a field effect transistor according to claim 1, wherein the second insulating film is a CVDSiO_2 film.