JPS62156877A - Schottky gate field effect transistor and manufacture of the same - Google Patents

Abstract

PURPOSE:To increase a mutual conductance and improve noise characteristics by a method wherein an operating layer is composed of 1st and 2nd parts and impurity quantity per unit area of the 2nd operating layer part is larger than that of the 1st operating layer part and both ends of a Schottky electrode metal are extended to reach the parts above the productions of end surfaces of source and drain electrodes adjoining to it. CONSTITUTION:By composing an operating layer of two parts whose impurity concentrations are different from each other and by forming a gate electrode so as to be expanded above the high concentration operating layer part with an insulating film between, the space between the gate electrode and the ohmic electrode of an MESFET can be sufficiently reduced so that series resistances between the gate and the source and between the gate and the drain can be reduced. With this constitution, a sufficient gain margin can be ensured and improvement of radio frequency characteristics such as noise characteristics can be sufficiently expected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a Schottky gate field effect transistor and a method of manufacturing the same. More specifically, the present invention relates to a Schottky gate field effect transistor with excellent noise characteristics and a method of manufacturing the same with high yield.

BACKGROUND OF THE INVENTION A field effect transistor is a semiconductor device that has two electrodes called a source and a drain that are ohmically connected to a semiconductor substrate, and a control electrode called a gate.
They have become widely used today to replace the classic bipolar transistor. Among the above electrodes, the source and drain correspond to the cathode and anode in a vacuum tube, respectively, while the gate functions as a grid, and is called a channel, which is provided between the source and drain to electrically connect them. The resistance of the conductive layer is
The current between the drain and source can be controlled by controlling the voltage applied to the gate.

Compared to bipolar transistors, this field-effect transistor has a high input impedance, has less low-frequency noise, has a relationship between input voltage and output current close to a square-law characteristic, and produces less high-order high-frequency distortion. , cross-modulation distortion is also small when two signals are input at the same time.
It has various advantages, such as high temperature stability because the temperature dependence of current is negative, and small fluctuations in characteristics because it is a majority carrier element.

Such field effect transistors include a junction field effect transistor (JFET) that uses a pn junction in the gate and an insulated gate field effect transistor (JFET) that uses an insulating film between the gates.
IGFET), and the latter generally uses an oxide film as an insulating film, so M
OS (Metal-Oxide-Semicond
uctor) FET. These are classified as p-type or n-type depending on the type of channel.
In addition, there are two types of operation modes: depletion mode and enhancement mode; the latter has the feature that the drain electrode and gate bias have the same polarity, and due to the insulated gate structure, the integrated circuit is directly connected to the output of the previous stage. becomes possible. Furthermore, since the source and drain electrodes can be formed on the same plane, there is no need to separate the elements in the case of integrated circuits.

Therefore, an integrated circuit having an insulated gate FET such as a MOSFET as a component has a significantly simple structure, and the manufacturing process is correspondingly simplified.

Incidentally, a Schottky gate field effect transistor is a variation of the above-mentioned junction FET, and unlike a junction FET whose electrode is a pn junction, it is constructed of a Schottky junction formed by contact between a metal and a semiconductor. and
M E S (Metal Sem1-conduct
or) Also called FET. Therefore, in the present invention, this will be abbreviated as MESFET hereinafter.

The semiconductor material used in this MESFET is Si.
In addition to Ga, III-V compound semiconductors such as S and InP are used and are said to be particularly useful in ultra-high frequency, high performance devices such as microwaves.

The structure of a conventionally proposed MESFET is as shown in the attached FIG. 2. That is, the semi-insulating semiconductor substrate 1
an active layer 2 disposed thereon, a gate electrode 3 provided on the active layer 2, and a source electrode 4 and a drain electrode 5 ohmically connected to the active layer 2 on both sides of the gate electrode 3. Consists of.

However, since the conventional MESFET having the structure shown in FIG. 2 has a large resistance value between the gate 3 and the source 4 or between the gate 3 and the drain 4,
It has serious drawbacks, such as not being able to obtain a sufficiently large value of the transconductance axis (m), and deteriorating noise characteristics due to the large gate-source series resistance. Especially when the absolute value of the pinch-off voltage (V) is small or when the normally-off type, that is, the enhancement type MESFE
For T, the following equation (■): where: ■ device built-in voltage; ε: dielectric constant of semiconductor crystal; q: charge element; Nd: carrier concentration; a: carrier concentration as indicated by the thickness of the active layer. Since the thickness a of the Nd or active layer must be kept to a small value, the series resistance between the gate and the source becomes larger, posing an extremely serious problem.

Therefore, as one measure to solve these drawbacks, as shown in Figure 3, high concentration impurity atoms are implanted into the active layer region between the gate and source and between the gate and drain. A method has been proposed to reduce the series resistance of

In FIG. 3, a gate electrode 3 and a highly doped active layer region 10 are shown.
SiN films 11 and 5i are used to separate the
An n2 film 12 is provided. In particular, the SiN film also functions as a protective film when the active layer 2 and the active layer 10 formed by ion implantation into the semi-insulating semiconductor substrate 1 are activated by annealing.

This conventional MESFET, for example, first has a semi-insulating substrate 1.
A pattern having an opening in a portion corresponding to the active layer region is formed thereon, and using this as a mask, a first ion implantation is performed to form the first active layer 2, and then an insulating film 11 is formed. Next, a T-shaped resist pattern is formed in the gate region, and ions are implanted using this as a mask to form the active layer 10. The second insulating film 12 is formed by a vapor deposition method, a sputtering method, etc., the resist is removed by lift-off, the ion implantation region is activated and the crystallinity is restored by annealing, a resist mask is formed, and the source electrode 4 and the first insulating film 11 in the drain electrode 5 region
After removing the second insulating film 12, an ohmic metal is deposited to form a source electrode 4 and a drain electrode 5 in the above regions. Next, the portions of the first insulating layer 11 not covered by the second insulating film 12 are removed by etching to form the gate electrode 3, thereby obtaining a MESFET having the structure shown in FIG.

However, in the case of the configuration shown in FIG. 3, the alignment accuracy in the manufacturing process is ±0.3 to 0.
The distance between the gate and the ohmic electrode must be approximately 1 to 1.5 μm, which is relatively low at 5 μm, and as a result, the series resistance cannot be lowered to a level sufficient for high frequency operation. Furthermore, the gate-source and gate-drain distances vary widely due to alignment errors, which causes variations in gate-source resistance, so the manufacturing yield of devices is not very satisfactory. There wasn't.

Problems to be Solved by the Invention As mentioned above, MESFETs have various advantages over classical bipolar transistors, so they have recently become widely used as so-called field effect transistors. Among them, it is said to be useful in high-frequency, high-performance devices such as microwaves, and to improve high-frequency operation, II
The use of IV group compound semiconductors and the like is being considered and extensive research is being conducted.

However, the previously proposed MESFET structures (see Figures 2 and 3) have various drawbacks as mentioned above, and in order to put them into practical use, further improvements must be made to achieve more satisfactory characteristics. It is necessary to make it a thing.

Therefore, an object of the present invention is to
The object of the present invention is to overcome the various drawbacks of T and provide a MESFET whose device characteristics are improved to a degree sufficient for practical use.

Another object of the present invention is to mass produce MESFETs having the above-mentioned excellent characteristics with a high yield.
An object of the present invention is to provide a method for manufacturing an SFET.

Means for Solving the Problems In view of the current state of MESFETs as described above, the inventors of the present invention have conducted various studies and studies to solve the above-mentioned drawbacks of MESFETs. The present invention was completed based on the finding that forming the wafer is extremely effective in achieving the above object.

That is, the Schottky gate field effect transistor of the present invention includes a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate, and a source electrode, a gate electrode, and a drain electrode formed on the active layer. A Schottky gate field effect transistor, wherein the operating layer is composed of a first portion formed under the gate electrode and a second portion formed on both sides of the first portion in contact with the first portion. , the amount of impurities per unit area of the second active layer is larger than the amount of impurities per unit area of the first active layer, and further, both ends of the Schottky electrode metal are an extension of the end surfaces of the source and drain electrodes adjacent to each other. It is characterized by having a structure that is formed so as to reach above the line.

In the MESFET of the present invention, the gate electrode is
For example, it includes a portion in contact with the first operating layer and a portion in contact with the first and second operating layers via an insulating film.

The configuration of the MESFET of the present invention is illustrated in, for example, the attached FIG.
) can be best understood by referring to That is, a semi-insulating semiconductor substrate 20, for example, Cr, O-doped GaAs, re-doped I
Various semiconductor substrates made semi-insulating by doping various impurities such as nP, a first operating layer 21, a second operating layer 22, and a gate electrode provided on the first operating layer 21. 23, for example, Ti/Pt/heu, etc., and a source electrode 24 and a drain electrode 25, which are ohmically connected on the second active layer 22, for example, an 8U-Ge alloy. In this embodiment, the gate electrode 23 is in contact with the first operating layer 21 and extends over the second operating layer 22 via insulating layers 26 and 27 on both sides thereof.

In the MESFET of the present invention, a gate metal is first formed, the insulating film is removed by etching using this as a mask, openings for forming the source and drain electrodes are formed, and an ohmic metal is deposited to form the gate electrode. Advantageously, this can be achieved by the method of the present invention, which is characterized in that the ohmic electrode is formed in a self-aligned manner with respect to the ohmic electrode.

The method of the present invention can be carried out, for example, according to the steps shown in FIGS. 1(a) to (d). First, on the semi-insulating semiconductor substrate 20, for example, various epitaxial growth methods (halide vapor phase epitaxy, organometallic epitaxial growth method (OMM)) are applied.
CVD), molecular beam epitaxial growth (MBE), and ion implantation (this can also be performed on the epitaxial layer after it has been formed).
An active layer 21 is formed. Furthermore, using the multilayer resist 28 as a mask, ions are implanted at a high concentration to form the first
A second active layer 22 is formed on both sides of the active layer 21 . These active layers are formed by first forming an epitaxial layer with a relatively low impurity concentration as the first active layer 21 over the entire substrate 20, and then forming a second active layer using a resist mask.
It is also possible to carry out the operation and drawing by doping the region to be formed with a higher concentration.

When using the ion implantation method, the crystallinity of the semiconductor crystal (substrate) subjected to the ion implantation operation is significantly disturbed in the implanted region, especially in the second active layer into which high concentration ions are implanted. In this case, it will be in an almost amorphous state, so either perform a treatment to restore this amorphous state, or apply a protective film (for example, an amorphous film such as SiN, 5in2.5iNO, etc.) in advance, and then perform the ion implantation operation. By doing so, it is possible to prevent amorphization or, in the case of compound semiconductors, evaporation of high vapor pressure components. Thus, the impurity-doped active layer is subjected to an activation heat treatment (generally 800 to 9
000°C) and then completed (see Figure 1(a)).

In addition, when the active layer is first formed by epitaxial growth and then the highly concentrated active layer is formed using ion implantation, impurities such as Cr diffuse from the substrate, resulting in a large number of impurity atoms at the interface between the substrate and the active layer. The characteristics of the resulting MESFET, especially the drain current drift and I.

sV. Since a so-called looping phenomenon, such as hysteresis in characteristics, may occur, the active layer is usually grown after a high purity, high resistance buffer layer has been grown to a thickness of 1 to 5 μm.

In the operation shown in FIG. 1(a), the SiN film 26 is placed on the substrate.
Although an example was shown in which a film was formed, as mentioned above, a pond film may also be used, and there are no restrictions on the material, thickness, etc., as long as it can prevent surface deterioration. Further, when performing the crystallinity recovery treatment as described above, this protective film is not necessary. Any such configuration is within the scope of the present invention and is not limited to what is shown.

Next, according to FIG. 1(b), a second layer of insulating film 27 such as 5i02 is formed by sputtering or the like on the intermediate product in the state shown in FIG. 1(a), and the resist 28 is removed by lift-off. As a result, an opening for a Schottky junction is formed, and the first insulating film 26 in the opening is removed using the insulating film 27 as a mask to expose the first active layer. Here, when the insulating film 26 is made of SiN, the above operation can be performed by dry etching using an etching gas such as CF4 using a plasma etching apparatus. Further, even when a protective film other than SiN is used, the same process can be performed according to a known method.

A metal film for a gate electrode is deposited in the region including the opening thus formed by a film forming method such as a vapor deposition method, a sputtering method, or an ion blasting method, and then a gate electrode 23 is formed by a lift-off method, a photoetching method, or the like.

The gate metal materials include Ti/Pt/Δu, P
t/Pd/Ni, Pd/Ni/Rh.

Any conventionally known material having good Schottky bonding properties such as Ni/uSRh/Au can be appropriately selected and used.

After forming the gate electrode in this manner, a resist layer 29 is formed using an IJ coating.

This forms part of the mask used to form openings for forming source and drain electrodes, which will be described below.
On the side opposite to the end adjacent to the gate electrode, the source
It functions to define a drain formation region. It also plays the role of ensuring an insulation distance between each element formed on the substrate 20. Therefore, this resist is made of a material that is resistant to the etching of the insulating film, such as 0F.
It is preferable to select from PR800 or the like.

Furthermore, as shown in FIG. 1C, using the gate electrode 23 and resist layer 29 formed as described above as a mask, the insulating films 27 and 26 (if present) are removed by, for example, reactive ion etching technology. The highly concentrated active layer (second active layer) 22 is exposed, openings are provided for forming source and drain electrodes, and then ohmic metal is deposited in the openings by various methods such as evaporation, sputtering, ion blasting, etc. After lift-off and alloying, an ohmic electrode is formed in a self-aligned manner with the gate electrode. As this ohmic metal, for example, Au
-Ge system, 8u-Ge/Ni, Ni-Ge system, heu-
Examples include Cr type and Au-Pt-Cr type.

] January M, E S F E useful as high frequency, high performance purple
The conventional problem with T is that due to its structure and manufacturing method limitations, the resistance value between the gate and source or between the gate and drain is large, making it difficult to provide a sufficient resistance value. , and noise characteristics deteriorated due to the large series resistance between the gate and source, especially in the latter case, when the progressive value of the pinch-off voltage was small or in the case of a no-7 re-off type MESFET. Since the carrier concentration or the thickness of the active layer had to be reduced, the series resistance between the gate and the source was large, which had a great negative effect on the noise characteristics.

However, all of these drawbacks found in conventional MESFETs can be overcome by changing the configuration to the one shown in Figure 1 (represented by the mountain), that is, by configuring the active layer into two parts with different impurity concentrations. This problem could also be solved by configuring the gate electrode to extend over the high-concentration active layer via the insulating film.

Furthermore, by having the above configuration, the ME
Since it has become possible to sufficiently reduce the distance between the gate electrode and ohmic electrode of SFET, it is possible to reduce the series resistance between the gate and source and between the gate and drain, and as a result, secure a sufficient gm value. Now I can do it. Further, as a matter of course, improvement in high frequency characteristics such as noise characteristics can be fully expected.

In addition, in the MESFET manufacturing method of the present invention, alignment accuracy is greatly improved compared to the conventional manufacturing method explained based on FIG. By adopting a self-aligned method that uses the previously formed gate electrode as a mask during formation, it is possible to eliminate this problem and reduce the series resistance between the gate and ohmic electrode to a level sufficient for high-frequency operation. Ta. Furthermore, by employing this self-aligned method, variations in resistance between the gate and source are eliminated, resulting in a significant improvement in device manufacturing yield.

Example The following is a list of MESFETs of the present invention according to examples.

The manufacturing method will be explained in more detail below. but,
The scope of the invention is not limited by the following examples.

Example 1 ME according to the present invention according to the configuration shown in FIG.
SFET was fabricated. First, a semi-insulating GaΔS substrate was used as a semi-insulating substrate, and a SiN layer was applied as a protective film on top of the semi-insulating GaΔS substrate.
A film was deposited to a thickness of 1,000 μm, and a first active layer was formed via the protective film by ion implantation.

Implanted ions: Sl Implanted concentration + 2 x 10”/c
PR800) is formed on the gate electrode formation region, and ions are implanted on both sides to form a second active layer into which ions are implanted at a high concentration.

Implanted ions: Si Implanted concentration = 2×1013/Ci SiO□ by sputtering using the above resist as a mask
A film was formed to a thickness of 2000 nm, an opening for a Schottky junction was formed on the first active layer by a lift-off method, annealing was performed, and then an SiO□ insulating film was used as a mask to form an opening on the active layer. The SiN film in the opening was removed using a plasma etching device using CF as an etching gas to expose the first active layer, and then Ti/Pt/8U was deposited in the region including the opening, followed by lift-off. A gate electrode was formed using the method.

Next, using a separate resist film (OFPR800), a resist pattern is formed according to the IJ Sogelafy method so as to define the end portions of the source and drain electrodes other than the portion adjacent to the gate electrode.

Furthermore, using the thus obtained gate electrode and resist film as a mask, the insulating film is etched by reactive ion etching. Here, CF4 is used as etching gas.
Using +02 gas, gas pressure 2 x 1O-2 Torr
Etching was performed under r.

Finally, 8u-Ge/Ni was deposited as an ohmic metal.

After lift-off and forming source and drain electrode patterns, ohmic metal alloying is performed to form ohmic electrodes, that is, source and drain electrodes in self-alignment with the gate electrode.
I humiliated ESFET.

In the MESFET thus obtained, the distance between the gate electrode and the ohmic electrode can be made sufficiently small, and the series resistance between the gate and source and between the gate and drain can be greatly reduced, and the high frequency characteristics can be improved. did it.

Effects of the Invention As explained in detail above, by configuring the MESFET as shown in FIG. 1(d) of the present invention, the problem of the gate-source or gate-drain The problem is that the mutual conductance gm is small due to the large resistance value of the gate.
The deterioration of noise characteristics caused by the large series resistance between sources can be advantageously resolved.

Furthermore, according to the MESFET manufacturing method of the present invention, a gate electrode is first formed, and the gate electrode pattern is used as a mask to form self-aligned source/drain electrodes, which eliminates the manufacturing process found in conventional methods. We were able to almost solve the serious problem of having to increase the distance between the gate and ohmic electrode due to the low accuracy of the alignment described above, which made it impossible to obtain sufficient series resistance for high-frequency operation. Further, since the electrodes are formed in a self-aligned manner, alignment errors are small, and as a result, variations in gate-source resistance are also small, making it possible to achieve a significantly improved device manufacturing yield.

As described above, the present invention can be said to be extremely useful from an industrial standpoint.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are cross-sectional views schematically showing each process for explaining the manufacturing method of MESFET of the present invention, and FIG. 2 is a cross-sectional view for explaining the structure of a conventional MESFET. FIG. 3 is a schematic cross-sectional view of MESFE obtained by another conventional manufacturing method.
FIG. 2 is a schematic cross-sectional view for explaining the configuration of T and its drawbacks. [Main reference numbers] ■, 20... Semi-insulating semiconductor substrate, 2.21... Active layer, 3, 23... Gate electrode, 4.24... Source electrode, 5.25...・Drain electrode, 10, 22...high concentration operating layer,

Claims (7)

[Claims] (1) In a Schottky gate field effect transistor comprising a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate, and a source electrode, a gate electrode, and a drain electrode formed on the active layer, the above operation is performed. The layer is composed of a first portion formed under the gate electrode and a second portion formed on both sides of the first portion, and the second active layer has a The structure has a structure in which the amount of impurities is larger than the amount of impurities per unit area of the first active layer, and further, both ends of the Schottky electrode metal reach above the extension line of the end surfaces of the adjacent source and drain electrodes. The above-mentioned Schottky gate field effect transistor. (2) The Schottky according to claim 1, characterized in that the gate electrode consists of a portion in direct contact with the first operating layer and a portion in contact with the first and second operating layers via an insulating film. Gate field effect transistor. (3) a semi-insulating semiconductor substrate, a first active layer formed on the surface thereof, a second active layer provided on both sides of the first active layer and having a higher impurity concentration than the first active layer; A source electrode and a drain electrode ohmically connected on the active layer and in contact with the first active layer and via an insulating film,
A method for manufacturing a Schottky gate field effect transistor comprising a second active layer and a gate electrode in contact with the second active layer, the method comprising: etching the insulating film using the formed gate electrode as a mask; form an opening at the top;
A method of manufacturing the Schottky gate field effect transistor, comprising the step of depositing an ohmic metal to form source and drain electrodes in the opening in self-alignment with the gate electrode. (4) The method according to claim 3, wherein the first operating layer and the second operating layer are formed by ion implantation. (5) Claim 3, characterized in that the first active layer is formed by vapor phase epitaxial growth.
The method described in section. (6) The method according to claim 5, characterized in that the second operating layer is formed by implanting ions into both sides of the gate electrode formation region of the first operating layer. (7) The gate electrode material is Ti/Pt/Au, Pt/
Pd/Ni, Pd/Ni/Rh, Ni/Au or Rh
/Au Claims 3 to 6
The method described in any one of paragraphs.