JP2000150540A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the distortion of high frequency signal with good reproducibility even with a high frequency device of short gate length, by changing an effective film thickness and carrier concentration in an active region in the direction of gate finger. SOLUTION: At the formation of an n-GaAs layer, an FET fabrication region is divided into a region A and a region B, and an n-GaAs layer is formed in the region A by two times of ion implantation. Since a carrier concentration is different between the regions (a) and (b), the extension of a depletion layer from a gate finger part is different when a constant voltage is applied to a gate electrode 3, resulting in difference in pinch off voltage between the regions (a) and (b) with changes in current near pinch off becoming smaller. A rapid change in mutual conductance near the pinch off is prevented to reduce a signal distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency field-effect transistor, and more particularly to a high-frequency field-effect transistor with reduced distortion of a high-frequency signal.

[0002]

2. Description of the Related Art With the recent digitization of communication systems and the increase in the number of channels, high-frequency field-effect transistors (hereinafter referred to as "FETs") used in these communication systems have been required to reduce distortion of high-frequency signals. Strongly required. Generally, in order to operate an FET with high efficiency, a drain current (Id) when a bias is applied to a gate electrode is a current value of about several% of a maximum drain current (a current when no bias is applied to the gate electrode). In other words, the gate bias voltage (Vg) becomes equal to the pinch-off voltage (V
It is set to be in the vicinity of p).

[0003]

When the FET is operated under such a bias condition, the gate input voltage reaches Vp when the input of the high-frequency signal to the gate electrode is at a relatively low level. In the vicinity where the gate input voltage reaches Vp, the transconductance (gm) changes abruptly, causing distortion of the high-frequency output signal and deteriorating the signal.

In order to solve this problem, it is necessary to smooth the change in gm near Vp.
One solution to this problem is to use a structure in which the gate length is changed in the middle of the gate finger portion of the gate electrode as shown in FIG. 7, according to IEEE 1996 Microwave and Millimeter-W.
It is reported in ave Monolithic Circuits Symposium Proceedings p.43-46. That is, in the middle of the gate finger portion, Lg
By reducing the gate length from 1 to Lg2, Vp is changed according to the length of the gate length by utilizing the difference in the short channel effect due to the difference in gate length, thereby realizing a configuration in which FETs having different Vp are connected in parallel. To improve the distortion characteristics.

[0005] However, as a result of investigations by the present inventors, in a device requiring high gain, for example,
Since it is necessary to further shorten the gate length of the gate finger portion so that the gate length (Lg1) is 0.5 μm or less to Lg2, the gate finger portion is formed to have a different gate length in the middle of the gate finger portion. This is difficult in terms of processing accuracy, and it has been found that it is difficult to obtain a gate finger portion having desired characteristics with good reproducibility. Therefore, the present invention has been made to solve such a problem,
It is an object of the present invention to provide an FET capable of reducing distortion of a high-frequency signal with high reproducibility even in a high-frequency device having a short gate length.

[0006]

Accordingly, the present inventors have conducted intensive studies and have noticed that the controllability of the carrier concentration and the film thickness of the active region is high, and the carrier concentration and the effective film thickness of the active region in the direction of the gate finger. It has been found that by changing the thickness, Vp in the direction of the gate finger can be changed to reduce the distortion of a high-frequency signal, and the present invention has been completed.

That is, according to the present invention, a source region, a drain region and an active region sandwiched therebetween are provided on a semiconductor substrate, a source electrode is provided on the source region, and a drain electrode is provided on the drain region. A field effect transistor provided with a gate electrode having a gate finger portion extending over the active region so as to be sandwiched between the source electrode and the drain electrode, wherein the gate electrode portion is located below the gate finger portion of the gate electrode. At least one of the carrier concentration and the effective film thickness of the active region is made different along the gate finger portion so that the pinch-off voltage required to cut off the active region has a different region in the gate finger portion. Which is a high-frequency field effect transistor. By having such a structure of the active region, the extension of the depletion layer from the gate finger portion when a constant voltage is applied to the gate electrode varies depending on the region, and the pinch-off voltage (Vp) also varies. As a result, the normal F
Since the pinch-off does not occur simultaneously over the entire area of the gate finger as in the case of ET, the current (Id
The change in s) is small, and a rapid change in the mutual conductance (gm) near the pinch-off can be prevented. Accordingly, signal distortion can be reduced, and in particular, high frequency characteristics of the high frequency field effect transistor can be improved.

As means for reducing such signal distortion, Japanese Unexamined Patent Application Publication No. Hei 9-115926 discloses a technique in which the source / drain electrodes are formed so as to have different shapes depending on the regions, and the source resistance of the transistor is made different. It has been proposed to use a structure in which two FETs having different points are connected in parallel. However, according to the inventors' studies,
In the above proposal, since it is indispensable to provide two regions, that is, a region where the distance between the gate electrode and the source electrode is short and a region where the distance is long, a decrease in gain occurs in a region where the distance is long,
It has been found that there is a certain limit in improving the characteristics of the FET. On the other hand, in the present invention, since the signal distortion is reduced by using the film thickness and the carrier concentration having good controllability, the present invention can be easily applied to a high-frequency FET having a short distance between the source / gate electrodes. The pinch-off voltage can be controlled relatively easily with a high accuracy.

Preferably, the active region is formed from at least two regions having different carrier concentrations stepwise along the gate finger portion. This is because, by providing two or more active regions having different carrier concentrations, the extension of the depletion layer in each region can be made different, and the pinch-off voltage can be made different in each region.

[0010] The carrier concentration of the active region may be varied stepwise in a region below the gate finger. This is because the pinch-off voltage can be formed differently in each region by changing the carrier concentration in the region below the gate finger portion.

[0011] The carrier concentration of the active region may be varied stepwise in a region other than the lower portion of the gate finger portion. Since the depletion layer extending from the gate finger is extended toward the drain electrode by the electric field in the active region, even if the carrier concentration below the gate finger is uniform, the carrier concentration in the region beside the gate finger is different. This is because the pinch-off voltage can be formed differently in each region.

It is preferable that the carrier concentration in the active region is formed so as to be varied stepwise by selective ion implantation with different implantation amounts. This is because the thickness and the carrier concentration can be easily controlled by using ion implantation.

It is preferable that the active region is formed of at least two regions having different effective film thicknesses stepwise along the gate finger portion. This is because the pinch-off voltage can be formed differently in such a region by providing regions having different effective film thicknesses.

The effective film thickness of the active region is such that a lower layer region of a conductivity type opposite to that of the active region is provided below the active region, and the carrier concentration of the lower region is changed along the gate finger portion. Thus, the thickness of the depletion layer extending into the active region from the junction surface between the lower region and the active region may be changed to be different.
By using such a structure, the thickness of the depletion layer extending from the interface between the active region and the lower region of the active region toward the active region can be changed depending on the region, and the effective film thickness of the active region can be changed. It is.

The effective film thickness of the active region may be differently formed by changing the depth of the active region by performing selective ion implantation at different implantation energies. This is because the thickness of the active region can be controlled with high precision by changing the implantation energy to form the active region.

The effective film thickness of the active region may be formed differently by changing the depth of the active region in a region other than the lower portion of the gate finger portion.
The depletion layer extending from the gate finger portion is pulled toward the drain electrode by the electric field of the active region and extends. This is because they can be formed differently.

The effective film thickness of the active region may be differently formed by changing the film thickness of the active region by etching. This is because changing the film thickness by etching makes it possible to apply the present invention to a field-effect transistor in which each layer is formed by epitaxial growth.

The etching may be a recess etching. This is because the FET according to the present invention can be manufactured by a simple manufacturing process by simultaneously changing the film thickness of each region using the recess etching.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a top view of the high-frequency FET according to the present embodiment, and FIG. 2 is a cross-sectional view. In the figure, the same reference numerals as those in FIG.
The same or corresponding parts are shown, and 4 is semi-insulating GaAs
Substrate, 5 is a p-GaAs layer, 6 is an n ⁺ -GaAs layer, 7
Denotes an n'-GaAs layer, and 8 denotes an n-GaAs layer. Here, the n ⁺ -GaAs layer 6 constitutes a source / drain region, the n'-GaAs layer 7 and the n-GaAs layer 8
An active region sandwiched between the source / drain regions is formed.

Here, in the FET according to the present embodiment, as shown in FIG.
Are divided in a direction perpendicular to the gate finger portion, and are referred to as a region A and a region B, respectively. A region sandwiched between the source region below the source electrode 1 and the drain region below the drain electrode 2 is an active region.
The regions included in the region B are referred to as a region a and a region b, respectively. The carrier concentration of the active region differs between the region a and the region b.

FIG. 2 is a sectional view of the FET shown in FIG. 1 in a direction perpendicular to the gate finger portion. As shown in FIG. 2, the active region is specifically formed of an n-GaAs layer 8 below the gate finger portion of the gate electrode 3 and n'-GaAs layers 7 provided on both sides thereof. The concentrations of both the n-GaAs layer 8 and the n′-GaAs layer 7 are different between the region a and the region b.

Next, a method of manufacturing the FET according to the present embodiment will be described with reference to FIG. First, as shown in FIG. 3A, the entire region (region A and region B) of the FET fabrication region on the semi-insulating GaAs semiconductor substrate 4
Then, Mg ions and Si ions are sequentially implanted using an ion implantation technique, so that the p-GaAs layer 5 and the n-G
An aAs layer 8 is formed. Further, a resist mask (not shown) is formed in a region other than the region A by photolithography, and Si ions are selectively ion-implanted only in the region B. It is preferable that the implantation depth of the ion implantation is substantially equal to that of the n-GaAs layer 8. As described above, the region B of the n-GaAs layer 8 is formed by one ion implantation, while the n-GaAs layer 8 is formed.
The region A of the As layer 8 is formed by two ion implantations.
For this reason, the region A is more ion-implanted than the region B.
The amount of i-ions increases. Thereafter, the implanted layer is activated by annealing at 800 ° C. for 20 minutes. This gives n
-For the GaAs layer 8, the carrier concentration in the region A is
It is formed to be higher than the carrier concentration in the region B.

Next, for example, as shown in FIG.
A gate metal material such as WSi is
A gate finger portion of the gate electrode 3 is formed in a predetermined region by photolithography and reactive ion etching (RIE) by depositing the entire surface of the wafer to a thickness of 0 °.

Next, as shown in FIG. 3C, a resist mask (not shown) is formed by photolithography, and Si is ion-implanted using the resist mask and the gate finger portion of the gate electrode as a mask. , N′-GaAs layer 7 is formed. When the amount of Si injected in this step is relatively large, the carrier concentration of the n′-GaAs layer 7 is substantially the same in the regions a and b. The carrier concentration in the region a becomes higher than the carrier concentration in the region b due to the influence of the concentration difference between the region A and the region B formed in the step.

Next, as shown in FIG. 3D, a resist mask (not shown) is formed by photolithography, and an n ⁺ -GaAs layer 6 is formed by implanting Si ions. An annealing process is performed to activate each ion implantation layer.

Next, as shown in FIG. 3E, a resist mask (not shown) is formed by photolithography,
A source electrode 1 and a drain electrode 2 having a laminated structure of, for example, AuGe / Ni / Au are formed by vapor-depositing a drain electrode metal material and lifting off, thereby completing the FET according to the present embodiment.

As described above, in the manufacturing method according to the present embodiment, when the n-GaAs layer 8 is formed, the FET fabrication region is divided into two regions, the region A and the region B. The n-GaAs layer 8 is formed by ion implantation. Therefore, since the carrier concentration is different between the region a and the region b, the extension of the depletion layer from the gate finger portion when a constant voltage is applied to the gate electrode 3 is different, and the pinch-off voltage (Vp ) Will be different. As described above, when Vp is different between the region a and the region b,
The change in the current (Ids) near the pinch-off becomes small, and the transconductance (g) near the pinch-off
m) can be prevented from changing suddenly, and signal distortion can be reduced.

In this embodiment, the implantation conditions for the regions A and B of the n-GaAs layer 8 are different.
Similar effects can be achieved by changing the implantation conditions of the p-GaAs layer 5 or the n′-GaAs layer 7. That is, the p- layer formed below the n-GaAs layer 8 is formed.
By forming the carrier concentration of the GaAs layer 5 to be higher in the region B than in the region A, the thickness of the depletion layer extending from the interface between the p-GaAs layer 5 and the n-GaAs layer 8 to the n-GaAs layer 8 side Can be made thicker in the region b than in the region a. As a result, the effective film thickness of the active region becomes thicker in region a than in region b, and Vp is increased in both regions.
Will be different.

Further, by making the implantation energy of the n-GaAs layer 8 higher in the region A than in the region B, the film thickness of the n-GaAs layer 8 formed by ion implantation is larger in the region A than in the region B. Can be formed. As a result, the effective film thickness of the active region is larger in the region a than in the region b, and Vp is different between the two regions.

Further, the formation of the n-GaAs layer 8 is performed in the region A,
The processing is performed uniformly without distinguishing the region B, and the S shown in FIG.
The i-implantation process is performed separately for the region A and the region B, and n′-Ga
The same effect can be obtained by making the carrier concentration of the As layer 7 higher in the region a than in the region b. That is, the depletion layer is extended by being pulled from the lower portion of the gate finger toward the drain electrode 2 by the electric field of the active region. N 'provided beside
The carrier concentration of the GaAs layer 7 (particularly, the drain electrode 2
The same effect can be obtained by forming the n′-GaAs layer 7 on the side differently in the region a and the region b).

Embodiment 2 A second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the case where the present invention is applied to a planar FET is described. In the present embodiment, a case where the present invention is applied to a recessed FET as shown in FIG. 4 will be described.

In FIG. 4, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In the FET according to the present embodiment, GaAs
p-GaAs layer 5 and n-GaAs on s semi-insulating substrate 4
After sequentially forming the layer 8 and the n ⁺ -GaAs layer 6, a recess is formed using a resist mask or the like. In this manufacturing process, as in the first embodiment, the n-GaAs layer 8 is formed by ion-implanting only the region A twice so that the carrier concentration in the region A is higher than the carrier concentration in the region B. It becomes possible. As a result, even when the present invention is used for a recessed FET, the current (I
ds) can be reduced, abrupt change in mutual conductance (gm) near pinch-off can be prevented, and signal distortion can be reduced.

Note that p-G described in the first embodiment is used.
Other structures such as forming the carrier concentration of the aAs layer 5 differently between the region A and the region B can be applied to the recessed FET according to the present embodiment.

Embodiment 3 A third embodiment of the present invention will be described with reference to FIG. In the first and second embodiments, the case where GaAs is used for the substrate has been described. However, as shown in FIG. 5, the present invention can also be applied to a high-frequency MOSFET using a Si substrate.
In FIG. 5, the same reference numerals as those in FIG.
3 is a gate oxide layer (SiO _2), 14 is p ⁺ -Si substrate, 15 ^p - -Si layer 16 is p-Si layer, 17 the n ^-
A -Si layer 18 is an n ⁺ -Si layer.

In the present embodiment, the carrier concentration of the n ⁻ -Si layer 17 is set to be higher than that of the region A by performing ion implantation twice only in the region B, for example.
As in the case of the sFET, the change in the current (Ids) near the pinch-off can be reduced, and the abrupt change in the mutual conductance (gm) near the pinch-off can be prevented.
Signal distortion can be reduced.

The carrier concentration of the p-Si layer 16 is
For example, it is formed to be higher than the area A in the area B,
Other structures applied to the GaAs FET can also be applied to the SiMOSFET according to the present embodiment.

Embodiment 4 FIG. A fourth embodiment of the present invention will be described with reference to FIG. In the first, second, and third embodiments, the case where the active region is formed by ion implantation has been described. In the present embodiment, the case where the active region is formed by an epitaxial growth layer will be described.

FIG. 6 shows a manufacturing process of the FET according to the present embodiment. In each of the process drawings, a left view shows a sectional view of the region A, and a right view shows a sectional view of the region B.

First, as shown in FIG. 6A, an Andob G is formed on a semi-insulating GaAs substrate 4 by using, for example, molecular beam epitaxy (MBE), MOCVD, or the like.
aAs layer 55, n-GaAs layer 8, n ⁺ -GaAs layer 6
Are sequentially grown. Next, normal photoengraving and evaporation,
Using a lift-off process, for example, AuGe / Ni / A
A source electrode 1 and a drain electrode 2 made of u are formed.

Next, as shown in FIGS. 6 (b1) and 6 (b2), A is obtained by ordinary photolithography and wet etching.
The first recess groove 20 having a depth d2 only in the region is formed.

Next, as shown in FIGS. 6 (c1) and 6 (c2), a second recess groove having a depth d1 is formed by ordinary photolithography and wet etching over the entire gate forming region. Therefore, as shown in (c1), in the region A, the second recess groove is formed so as to overlap the first recess groove.

Next, as shown in FIGS. 6 (d1) and 6 (d2), for example, a gate metal made of Ti / Al is deposited,
After that, the gate electrode 3 is formed by a lift-off process. Further, the source electrode 1 and the drain electrode 2 made of, for example, AuGe / Ni / Au are respectively formed by using the same deposition and lift-off processes.

In the FET thus formed, the recess depth is (d1 + d2) in the region A, while
In the area, it is d1. As a result, two types of FETs having different Vp equivalently can be formed in the gate finger direction.
As in the case of the FET formed by using the ion implantation technique described in Embodiment 1 or the like, signal distortion can be reduced.

In the first to fourth embodiments, the regions having different carrier concentrations and effective film thicknesses are two regions A and B. However, the three regions are arranged along the gate finger direction.
It may be formed from the above regions. Further, a structure in which pinch-off occurs first in either the region a or the region b may be employed. In the regions A and B,
It may be formed so that both the carrier concentration and the effective film thickness are different.

[0045]

As is apparent from the above description, according to the present invention, the pinch-off voltage (Vp) at the gate finger portion of the gate electrode differs depending on the region, and the change in the current (Ids) near the pinch-off becomes small. As a result, the transconductance (g) near the pinch-off
m) can be prevented from changing suddenly, and signal distortion can be reduced.

In particular, since the present invention reduces signal distortion by using a film thickness and a carrier concentration with good controllability, it can be applied to a high-frequency FET having a short gate length.

[Brief description of the drawings]

FIG. 1 is a top view of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the field-effect transistor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating the manufacturing process of the field-effect transistor according to the first embodiment of the present invention;

FIG. 4 is a sectional view of a field-effect transistor according to a second embodiment of the present invention;

FIG. 5 is a sectional view of a field-effect transistor according to a third embodiment of the present invention;

FIG. 6 is a cross-sectional view illustrating a manufacturing step of the field-effect transistor according to the fourth embodiment of the present invention.

FIG. 7 is a top view of a field-effect transistor according to a conventional structure.

[Explanation of symbols]

1 source electrode, 2 drain electrode, 3 gate electrode,
4 semi-insulating GaAs substrate, 5 p-GaAs layer, 6
n ⁺ -GaAs layer, 7 n'-GaAs layer, 8 n-Ga
As layer, 11 resist, 13 gate oxide film layer (Si
O ₂ ), 14p ⁺ -Si substrate, 15 p ^-- Si layer, 16
p-Si layer, 17 n ⁻ -Si layer, 18 n ⁺ -Si
Layer, 55 undoped GaAs layer.

Continued on front page F-term (reference) 4M104 AA05 BB02 BB09 BB11 BB14 BB28 CC01 CC03 DD09 DD34 DD37 DD65 DD68 FF27 5F102 GB01 GC01 GD01 GJ05 GL05 GL15 GL17 GR04 GR13 GR16 GT03 GT05 HA02 HC01 HC07 HC11 HC15 HC19 HC21

Claims (11)

[Claims] A source region, a drain region, and an active region sandwiched between the source region and the drain region; a source electrode on the source region; a drain electrode on the drain region; A field effect transistor provided with a gate electrode having a gate finger extending over the active region so as to be sandwiched between the gate electrode and the drain electrode. The active region has at least one of a carrier concentration and an effective film thickness that is different along the gate finger portion so that a pinch-off voltage required for the active region has a different region in the gate finger portion. High frequency field effect transistor. 2. The method according to claim 1, wherein the active region has at least two carriers having different carrier concentrations stepwise along the gate finger portion.
2. The high frequency field effect transistor according to claim 1, wherein the high frequency field effect transistor is formed of two regions. 3. The high-frequency field effect transistor according to claim 2, wherein the carrier concentration of the active region varies stepwise in a region below the gate finger portion. 4. The high-frequency field-effect transistor according to claim 2, wherein the carrier concentration of the active region varies stepwise in a region other than a portion below the gate finger portion. 5. The high-frequency field-effect transistor according to claim 3, wherein the carrier concentration in the active region is formed so as to be changed stepwise by selective ion implantation with different implantation amounts. 6. The high-frequency field effect transistor according to claim 1, wherein said active region is formed of at least two regions having different effective film thickness stepwise along said gate finger portion. . 7. An active region in which an effective film thickness is provided below the active region, a lower region of a conductivity type opposite to that of the active region is provided, and a carrier concentration of the lower region is adjusted along the gate finger portion. 7. The semiconductor device according to claim 6, wherein the thickness of the depletion layer extending from the junction between the lower layer region and the active region into the active region is changed to change the thickness of the depletion layer. High frequency field effect transistor. 8. The active film according to claim 6, wherein the effective film thickness of the active region is made different by changing the depth of the active region by performing selective ion implantation at a different implantation energy. 3. The high-frequency field effect transistor according to claim 1. 9. The active region according to claim 8, wherein the effective film thickness of the active region is changed by changing the depth of the active region in a region other than the lower portion of the gate finger portion. High frequency field effect transistor. 10. The high frequency field effect transistor according to claim 6, wherein the effective film thickness of the active region is changed by changing the film thickness of the active region by etching. 11. The high frequency field effect transistor according to claim 10, wherein the etching is recess etching.