JPH0758716B2 - Method for manufacturing field effect transistor - Google Patents

Description

The present invention relates to a self-aligned Schottky field effect transistor (hereinafter referred to as ME) by selective epitaxial crystal growth.
The present invention relates to a method for manufacturing a field-effect transistor that can be used in high-frequency communication and high-speed computers by forming a source and a drain (abbreviated as SFET).

2. Description of the Related Art In recent years, in the field of analog high frequency communication using a few to several tens of GHz band found in satellite communication, etc., and in the field of digital circuits such as high-speed computers requiring high-speed arithmetic processing, semiconductor devices have achieved high speed and low noise. Development for improving performance such as conversion is being actively conducted. In particular, compared with silicon, which has been the mainstream of conventional semiconductors, III-V group compound semiconductors represented by gallium arsenide (hereinafter abbreviated as GaAs) have a higher mobility of charge carriers than silicon and are faster semiconductor devices. As a matter of course, not only in the field of analog but also in the field of digital, it has just reached the stage of practical application. And aiming at further improvement in high-speed performance, shortening the gate length and
In order to reduce the parasitic resistance and the parasitic capacitance, MESFETs made of various III-V group compound semiconductors have been proposed.

Hereinafter, an example of a conventional method for manufacturing a field effect transistor using the III-V group compound semiconductor described above will be described with reference to the drawings.

2A, 2B, 2C, 2D, 2E, 2F, 2E, 3F, 3E, 3F, 3F, 3E, 3F, 3F, 3E, 3F, 3F, 3F, 3E, 3F, 3F, 3E, 3F, and 3E are structural cross-sectional views of a process of manufacturing a conventional MESFET. In FIG. 2, 1 is a GaAs semi-insulating substrate, 2 is an active layer which becomes a channel of GaAs MESFET, 3 is an ion implantation mask for forming the active layer 2 by selective ion implantation, and 4 is silicon nitride (hereinafter referred to as SiN). Abbreviated) membrane, 5
Is a silicon dioxide (hereinafter abbreviated as SiO ₂ ) pattern that serves as a mask for forming the dummy gate 6a, 6 is an organic film that becomes the dummy gate 6a in a later step, and 7 is the SiO ₂ pattern 5 formed by fluorine-based plasma 8 Photoresist for forming, 9 is oxygen plasma for forming the dummy gate 6a by plasma etching using the SiO ₂ pattern 5 as a mask, 1 is overetch length by plasma etching using the oxygen plasma 9, and 10 is the above An n ⁺ implantation portion formed by selective ion implantation of a silicon ion beam 11 using the SiO ₂ pattern 5 and the dummy gate 6a as a mask, 12 an SiO ₂ inversion pattern formed as an inversion pattern of the dummy gate 6a, 13, 14 Is the GaAs ME
These are the gate and source / drain electrodes of the SFET.

A method of manufacturing the MESFET configured as above will be described below.

First, the active layer 2 is formed on the GaAs semi-insulating substrate 1 by selective ion implantation using the ion implantation mask 3 (FIG. 2A). Next, after removing the ion implantation mask 3, plasma-enhanced chemical vapor deposition is performed.
A SiN film 4 is formed by a position (hereinafter abbreviated as P-CVD) method, and subsequently, a three-layer film including an organic film 6, an SiO ₂ film and a photoresist film is formed on the SiN film 4, and the photoresist is formed. The film is patterned by photolithography to form a photoresist 7, and the SiO 2 is formed by reactive ion etching (Reactive Ion Etching, hereinafter abbreviated as RIE) with a fluorine-based plasma 8 using the photoresist 7 as a mask.
_{The two} films are patterned to form a SiO ₂ pattern 5 (second
Figure b).

Next, the organic film 6 is formed perpendicularly to the GaAs semi-insulating substrate 1 by RIE using oxygen plasma 9 with the photoresist 7 and the SiO ₂ pattern 5 as a mask, and then overetching is performed to obtain an overetch length. A dummy gate 6a having 1 is formed. The oxygen plasma 9
The photoresist 7 disappears by the RIE by (FIG. 2c). Next, using the SiO ₂ pattern 5 and the dummy gate 6a as a mask, selective ion implantation of the silicon ion beam 11 is performed to form an n ⁺ implantation portion 10 (FIG. 2d).

In FIG. 2d, the n ⁺ implant portion 10 is formed apart from the dummy gate 6a by the overetch length l. Next, after forming a SiO ₂ film by a sputtering method, a SiO ₂ inversion pattern 12 is formed by a lift-off method using the dummy gate 6a and the organic film 6 (FIG. 2e). Further, after annealing at 800 ° C. for about 20 minutes in order to activate the ions implanted in the active layer 2 and the n ⁺ implantation part 10, a part of the SiO ₂ inversion pattern 12 and the SiN film 4 are formed.
Is removed to form the source / drain electrodes 14 of the MESFET, and the source / drain electrodes 14 and the n ⁺ implantation portion 10 are formed.
Alloying is performed at 460 ° C for about 30 seconds so that and become ohmic contact. Finally, after removing the SiN film 4 in the opening of the SiO ₂ inversion pattern 12 on the active layer 2, the gate 1 is removed.
The formation of 3 completes the GaAs MESFET (FIG. 2f). (For example, Yamazaki et al., Association of Electrical and Electronic Engineers, Meeting on Electronic Devices, Vol. 29, No. 11, 1772
Page ~ 1777, 1982 (IEEE Transactions on Electron
Devices, VOL.ED-29, NO.11, PP1772-1777 (1982)). As described above, the dummy gate 6a is replaced with the SiO ₂ pattern 5
The gate 13 and the n ⁺ implantation portion 10 are formed by self-alignment separated by the overetch length l by forming the GaAs MESFE with the overetch length l.
The gate resistance of the gate and source of T (abbreviated as Rs hereafter) is reduced, and the gate breakdown voltage is maintained by the overetch length l, which improves the characteristics of the GaAs MESFET.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the structure as described above, in the annealing for activating the selectively ion-implanted ions, the n ⁺ -implanted portion 10 is made to be the GaAs semi-insulating substrate by thermal diffusion of the implanted ions. 1 spreads in a direction parallel to the surface of the MESFET, that is, in the direction of the channel of the MESFET, and the pinch-off voltage of the MESFET changes in the negative direction as the gate length becomes shorter. The short channel effect makes it difficult to control the drain current by the Gate of the MESFET.
g _d ) is increased, mutual conductance (hereinafter abbreviated as g _m ) is decreased, and shortening the gate length rather deteriorates the characteristics. (For example, Matsumoto et al., Technical Report of IEICE, Fig. 82, No. 131, pp. 89-94, (SSD82-
69)), and also the n ⁺ implant 10 is a source Sorein the MESFET, with the short gate length of the MESFET, the source-drain interval is shortened, the through GaAs semi-insulating substrate 1 n ⁺ The leakage current flowing between the injection portion 10, that is, between the source and the drain also increases the g _d ,
Since g _m is lowered, there is a problem that it hinders the improvement of characteristics.

In view of the above problems, the present invention provides MESF after forming a dummy gate.
The source and drain of ET are formed by self-alignment by an epitaxial method, the short channel effect is reduced, and Rs is also reduced, thereby providing a high-speed and high-performance field effect transistor manufacturing method.

Means for Solving the Problems In order to solve the above problems, a method for manufacturing a field effect transistor according to the present invention is a group III-V group having an active layer in manufacturing a Schottky field effect transistor by pattern inversion of a gate. A dummy gate is formed on the compound semi-insulating substrate to form a gate by pattern inversion in a later step, and on the active layer on both sides of the dummy gate,
A low resistance epitaxial layer is grown, a source and a drain of the Schottky field effect transistor are formed by self-alignment, and at the same time, a polycrystalline layer or an amorphous layer is grown on the dummy gate, and further on the substrate. After forming the first flattening film, etch back is performed to remove the exposed polycrystalline layer or the amorphous layer, and then, after forming the second flattening film on the substrate, etch back is performed. The exposed dummy gate is removed and the gate is formed by pattern inversion.

According to the present invention, the source / drain of the MESFET is formed as an epitaxial layer on the upper surface of the active layer by the above-mentioned steps, so that it is possible to prevent the source / drain interval from being shortened by the thermal diffusion of implanted ions without the need for annealing. By forming the source / drain with lower resistance on the GaAs semi-insulating substrate through the active layer, the leak current from the source / drain to the GaAs semi-insulating substrate is suppressed, and the short channel effect is achieved. Is reduced. In addition, since the source and drain are formed in self-alignment with the gate, there is little parasitic resistance that contributes to Rs, and MESFET
Will result in higher g _m and higher speed performance.

Example A method for manufacturing a field effect transistor according to an example of the present invention will be described below with reference to the drawings.

1 a, b, c, d, e, f, g, h, i, j are structural sectional views showing a method for manufacturing a field effect transistor according to an embodiment of the present invention.

In FIG. 1 a, b, c, d, e, f, g, h, i, j, 21 is a GaAs semi-insulating substrate, 22 is a selective ion implantation of a silicon ion beam 24 using an ion implantation mask 23. Formed GaAa MESFE
T is an active layer, 25 is a gate pattern, 26 is an insulating film that forms a dummy gate 26a by etching with fluorine-based plasma 27 using the gate pattern 25 as a mask, and 28 is formed as a low resistance epitaxial layer on the active layer 22. The source / drain layer of the GaAs MESFET, 29 is a deposition layer formed as an amorphous or polycrystalline film on the dummy gate 26a and the insulating film 26, and 30 is the deposition layer 29.
, 31 is a source / drain electrode in ohmic contact with the source / drain layer 28, 32 is a gate inversion resist which is an inversion pattern of the dummy gate 26a, 33 is a gate 34 with the gate The lift-off resist is formed together with the reverse resist 32 by the lift-off method.

A method of manufacturing the field effect transistor configured as described above will be described below with reference to FIG.

Fig. 1 shows the manufacturing process.
On a GaAs semi-insulating substrate 21 of 10 ⁷ Ωcm or more, a silicon ion beam 24 with an accelerating voltage of 100 KeV and a dose of 6.0 × 10 ¹² dose / cm ² using an ion implantation mask 23 patterned with a photoresist. Selective ion implantation is performed to form the active layer 22 (FIG. 1A). Next, after removing the ion implantation mask 23 with an organic solvent, the SiO ₂ film is deposited under low pressure chemical vapor deposition (LPCVD).
A thickness of about 0.2 μm, and the active layer 22 is activated by cap annealing at 850 ° C. for 20 minutes. The SiO ₂ film is formed with a thickness of approximately 0.8μm by then removed again after the LPCVD method the SiO ₂ film, after the insulating film 26 serving as a dummy gate 26a in a later step, referred to as aluminum (hereinafter Al by a lift-off method The gate pattern 25 having a thickness of 0.1 μm is formed (FIG. 1b).

Next, using the gate pattern 25 as a mask, the insulating film 26 is anisotropically etched substantially perpendicular to the GaAs semi-insulating substrate 21 by RIE using a fluorine-based plasma 27 to form a dummy gate 26a (FIG. 1). c). Next, the gate pattern 25 made of Al was removed with hydrochloric acid, and then the substrate density was set to about 3 × 10 ¹⁸ cm ⁻¹ at a substrate temperature of 600 ° C. by a molecular beam epitaxy (MBE) method. By depositing low-resistance GaAs, the source / drain layer 28 made of low-resistance GaAs epitaxially grown on the active layer 22 and simultaneously on the dummy gate 26a and the insulating film 26 are polycrystallized and high A deposited layer 29 of GaAs is formed which becomes a resistance (FIG. 1d).

Then, after spin coating a photoresist, the photoresist is etched by oxygen plasma to form the organic film 30 with the deposited layer 29 exposed (FIG. 1e). Next, the deposited layer 29, which has been cued up, is replaced with tartaric acid / hydrogen peroxide GaAs.
It is removed with an etchant (Fig. 1f). Next, the organic film
After removing 30 with an organic solvent, an ohmic electrode made of a gold-germanium alloy is formed to form a source / drain electrode 31 (Fig. 1g). Next, after spin-coating the negative resist, the negative resist is etched again by oxygen plasma to form a gate inversion resist 32 and the dummy gate 26a is cued (FIG. 1h). Next, the positive gate is patterned so that the exposed portion of the dummy gate 26a is sufficiently exposed to form a lift-off resist 33, and then the dummy gate 26a is removed with a hydrofluoric acid-based etchant (see FIG. 1i). ). Next, Al is vacuum-deposited, and the lift-off resist 33 and the gate inversion resist 32 are removed to remove the gate by a lift-off method.
To form 34 (FIG. 1j).

As described above, according to this embodiment, since the source / drain layer 28 of the GaAs FET is formed by epitaxial growth,
The heat treatment for activating the source / drain layer 28 is not required, and the distribution of impurity ions (silicon in this embodiment) that provides carriers is not changed by thermal diffusion. But the active layer
It is formed on the upper part of 22 and does not come into direct contact with the GaAs semi-insulating substrate.
Leakage current to the semi-insulating substrate 21 is small and will reduce the short channel effect, a significant improvement in high g _m of and high frequency characteristics.

Although the dummy gate 26a is formed of the insulating film 26 made of a SiO ₂ film in this embodiment, the dummy gate 26a may be made of any material that does not react with the active layer 22 of GaAs, such as silicon nitride (SiN) or nitride. An insulating film such as aluminum (AlN), a refractory metal such as tungsten (W), rhenium (Re), molybdenum (Mo), an alloy thereof, or a silicide may be used. Source / drain layer 28
The source / drain layer 28 may be formed by any method as long as it is epitaxially grown on the GaAs active layer 22, for example, liquid phase epitaxial (Liqu.
id phase Epitaxial (LPE) method, Vapor Phase Epitaxial (VPE) method, or Metal Organic Chemical Vaper Depositio
It may be formed by the n (Mo-CVD) method.

Effects of the Invention As described above, the present invention has the following effects.

(1) The heat treatment for activating the source and drain is unnecessary, and the carrier distribution does not change.

(2) The source and drain are easily formed in the immediate vicinity of the dummy gate, and the parasitic resistance is greatly reduced.

(3) Since the gate electrode is formed by reversing the pattern of the dummy gate, it is possible to easily form the gate electrode having a significantly reduced resistance.

(4) As a result, the high frequency characteristics of the element are significantly improved and the element is easy to manufacture.

[Brief description of drawings]

1 a, b, c, d, e, f, g, h, i, j are structural cross-sectional views showing a method for manufacturing a field effect transistor in one embodiment of the present invention,
2A, 2B, 2C, 2D, 2E, 2F, 2E, 3F, 3E, 3F, 3E, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, and 3F are structural cross-sectional views showing a conventional method for manufacturing a field effect transistor. 1,21 …… GaAs semi-insulating substrate, 2,22 …… Active layer, 3,23 ……
Ion implantation mask, 4 …… Silicon nitride film, 6a, 26a ……
Dummy gate, 11,24 ... Silicon ion beam, 10 ...
… N ⁺ implant, 12 …… SiO ₂ inversion pattern, 13,34 …… gate, 14,31 …… source / drain electrode, 28 …… source ・
Drain layer, 29 ... Deposited layer, 6,30 ... Organic film, 32 ... Gate inversion resist, 33 ... Lift-off resist.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-49-5582 (JP, A) JP-A-59-165461 (JP, A) JP-A-59-161076 (JP, A) JP-A-59- 222965 (JP, A) JP 59-229875 (JP, A) JP 58-85570 (JP, A)

Claims (2)

[Claims] 1. When manufacturing a Schottky field effect transistor by reversing a gate pattern, an active layer is provided.
Forming a dummy gate for forming a gate by pattern reversal in a later step on a III-V compound semi-insulating substrate, and growing a low resistance epitaxial layer on the active layer on both sides of the dummy gate, A source and a drain of the Schottky field effect transistor are formed by self-alignment, and at the same time, a polycrystalline layer or an amorphous layer is grown on the dummy gate, and a first flattening film is formed on the substrate. Then, etch back is performed to remove the exposed polycrystalline layer or amorphous layer, and then a second planarization film is formed on the substrate, and then etch back is performed to expose the exposed dummy gate. Is removed, and a gate is formed by pattern inversion, and a method for manufacturing a field effect transistor. 2. The method for manufacturing a field effect transistor according to claim 1, wherein the dummy gate is made of silicon oxide, silicon nitride, a refractory metal or a refractory metal alloy.