JPH0410549A - Manufacture of field-effect transistor - Google Patents

Manufacture of field-effect transistor

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Publication number
JPH0410549A
JPH0410549A JP11056890A JP11056890A JPH0410549A JP H0410549 A JPH0410549 A JP H0410549A JP 11056890 A JP11056890 A JP 11056890A JP 11056890 A JP11056890 A JP 11056890A JP H0410549 A JPH0410549 A JP H0410549A
Authority
JP
Japan
Prior art keywords
layer
film
electrodes
forming
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11056890A
Other languages
Japanese (ja)
Inventor
Takashi Murakawa
村川 隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Nippon Mining Co Ltd
Nikko Kyodo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining Co Ltd, Nikko Kyodo Co Ltd filed Critical Nippon Mining Co Ltd
Priority to JP11056890A priority Critical patent/JPH0410549A/en
Publication of JPH0410549A publication Critical patent/JPH0410549A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To contrive to prevent the deterioration of a breakdown voltage by a method wherein source, drain and gate electrodes are formed, an oxide layer is formed on the surface of a semiconductor layer exposed between the source and drain electrodes by a heating treatment under an oxidizing atmosphere and a dielectric film is formed on the surface of the oxide layer. CONSTITUTION:An active layer 2 consisting of a conductive GaAs epitaxial layer is formed on a semi-insulative substrate 1 consisting of a GaAs semiconductor single crystal and source and drain electrodes 3 and 4, which are ohmic- junctioned to the layer 2, are formed. Then, a P-type resist film 5 is formed on the whole surface of the substrate 1. A metal layer 6 is formed on the film 5 and on an opening part 5', through which the layer 2 is exposed. The film 5 is dissolved are removed, the layer 6 other than the layer 6 on the opening part 5' is removed and a gate electrode 7 equivalent to the region of the opening part 5' is formed. Then, a heat treatment is performed on the electrodes 7, 3 and 4 and on the surface of the substrate 1 including the region of the layer 2 exposed between the electrodes 3 and 4 in an oxygen atmosphere. After that, a silicon nitride film 8 is formed on the whole surface of the layer 2 as a dielectric film for protection use by a plasma CVD method.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、ショットキー接合を形成するゲート電極を備
えた電界効果型トランジスタの製造方法に関し、特に、
化合物半導体上に保護用誘電体膜(パッシベーション膜
)を形成する方法に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a field effect transistor having a gate electrode forming a Schottky junction, and in particular,
The present invention relates to a method of forming a protective dielectric film (passivation film) on a compound semiconductor.

〔従来の技術] GaAsなどの化合物半導体上にショットキー接合を形
成するゲート電極を備えた電界効果型トランジスタ(以
下、FETという)は、高速動作に優れ、マイクロ波帯
の増幅素子として多く用いられている。このFETの表
面には、半導体表面および電極の保護のため、酸化シリ
コン、窒化シリコンなどからなる保護用の誘電体膜を形
成する必要がある。
[Prior Art] Field-effect transistors (hereinafter referred to as FETs), which have a gate electrode that forms a Schottky junction on a compound semiconductor such as GaAs, have excellent high-speed operation and are often used as amplification elements in the microwave band. ing. It is necessary to form a protective dielectric film made of silicon oxide, silicon nitride, etc. on the surface of this FET in order to protect the semiconductor surface and electrodes.

従来、これらのFETのゲート電極は、半導体゛表面に
ゲート電極に対応する開口部を持ったマスク(レジスト
膜、または酸化シリコンなどの絶縁膜からなる)を形成
し、開口部およびマスク上に金属膜を形成し、次にマス
クを除去することでマスフ上の金属膜を取り除き、開口
部にのみ金属膜を形成するリフトオフ法により形成され
る。そして、保護用の誘電体膜は、リフトオフ法により
ゲート電極を形成した後、スパッタリング法などにより
形成される。
Conventionally, the gate electrodes of these FETs are formed by forming a mask (made of a resist film or an insulating film such as silicon oxide) on the surface of a semiconductor with an opening corresponding to the gate electrode, and then depositing metal over the opening and the mask. It is formed by a lift-off method in which a film is formed, and then the metal film on the mask is removed by removing the mask, and the metal film is formed only in the openings. Then, the protective dielectric film is formed by a sputtering method or the like after forming the gate electrode by a lift-off method.

[発明が解決しようとする課題] しかし、上記従来の方法で作成した場合、保護用の誘電
体膜を形成することによりFETのブレークダウン電圧
(ゲート・ソース電極間耐圧)が劣化することが知られ
ていたわ 本発明は、上記の欠点を解決したもので、本発明の目的
はブレークダウン電圧が劣化しない保護用誘電体膜の形
成方法を提供することにある。
[Problems to be Solved by the Invention] However, it is known that when fabricated using the above conventional method, the breakdown voltage (gate-source electrode breakdown voltage) of the FET deteriorates due to the formation of a protective dielectric film. The present invention solves the above-mentioned drawbacks, and an object of the present invention is to provide a method for forming a protective dielectric film in which the breakdown voltage does not deteriorate.

〔課題を解決するための手段および作用〕本発明は、保
護用の誘電体膜形成前にゲート電極および半導体表面に
何らかの処理をすることで、FETの特性劣化を防止で
きるとの着想に基づいたものである。
[Means and effects for solving the problem] The present invention is based on the idea that deterioration of FET characteristics can be prevented by performing some kind of treatment on the gate electrode and semiconductor surface before forming a protective dielectric film. It is something.

本発明は、半導体上にソース電極、ドレイン電iおよび
ショットキー接合を形成するゲート電極を備えた電界効
果型トランジスタの製造方法において、前記ソース電極
およびドレイン電極を形成する第1の工程、前記ゲート
電極を形成する第2の工程、酸化雰囲気下での加熱処理
またはプラズマ放電処理により、前記ソース電極および
ドレイン電極間に露出した上記半導体の表面上に酸化物
層を形成する第3の工程、該表面上に誘電体膜を形成す
る第4の工程を行なうものである。
The present invention provides a method for manufacturing a field effect transistor including a source electrode, a drain electrode, and a gate electrode forming a Schottky junction on a semiconductor, including a first step of forming the source electrode and the drain electrode; a second step of forming an electrode; a third step of forming an oxide layer on the surface of the semiconductor exposed between the source electrode and the drain electrode by heat treatment or plasma discharge treatment in an oxidizing atmosphere; The fourth step is to form a dielectric film on the surface.

望ましくは、前記第3の工程において、前記酸化物層の
膜厚が飽和するまで前記プラズマ放電処理または加熱処
理を行なうものである。また、プラズマ放電処理は酸素
、または、酸化雰囲気を形成する化合物ガス雰囲気中で
行なわれる。
Desirably, in the third step, the plasma discharge treatment or heat treatment is performed until the thickness of the oxide layer is saturated. Further, the plasma discharge treatment is performed in an atmosphere of oxygen or a compound gas forming an oxidizing atmosphere.

本発明による作用は明らかではないが、FETの露出し
た半導体表面が安定な酸化物により被覆されるため、そ
の後に誘電体膜を形成すれば安定な動作が可能になるも
のと考えられる。
Although the effect of the present invention is not clear, it is thought that since the exposed semiconductor surface of the FET is covered with a stable oxide, stable operation is possible if a dielectric film is subsequently formed.

〔実施例] 本発明の一実施例であるFETの製造工程を、・、第1
図(a)〜(c)を用いて以下に説明する。
[Example] The manufacturing process of an FET which is an example of the present invention is as follows:
This will be explained below using Figures (a) to (c).

半絶縁性のGaAs半導体単結晶からなる基板1上に0
.3μm程度の膜厚を有する導電性のGaAsエピタキ
シャル層からなる活性層2が形成されている。この活性
層2にオーミック接合するソース電極3およびドレイン
電極4が形成される。次に、基板lの全面に有機高分子
からなるポジ型のレジスト膜5を形成する。通常のフォ
トリソグラフィにより幅1μmの開口部5′が、このレ
ジスト膜5のソース電極3・ドレイン電極4間に形成さ
れる。そして、レジスト膜5上および活性層2が露出し
た開口部5′上に金属層6を形成する。(第1図(a)
) レジスト膜5を溶解除去し、開口部5′以外の金属層6
を取り去ることにより、開口部5”の領域に相当するゲ
ート電極7が形成される。(リフトオフ法) 次に、ゲート電極7、ソース電極3およびドレイン電極
4上、かつ、ソース電極3・ドレイン電極4間の露出し
た活性層2領域を含む基板1の表面を酸素雰囲気での加
熱処理を行う。(第1図基板1をヒータ(ホットプレー
トなど)により3OO℃程度の温度に約1時間保持する
ことで行われる。加熱処理時間と酸化物層の膜厚(エリ
プソメトリ−による測定)の関係を第2図に示す。同図
から明らかなように、酸化物層の膜厚は、加熱処理前に
1.5nmであるが、1時間以上加熱処理することで1
.6nm程度の膜厚に形成さる。
0 on a substrate 1 made of a semi-insulating GaAs semiconductor single crystal.
.. An active layer 2 is formed of a conductive GaAs epitaxial layer having a thickness of about 3 μm. A source electrode 3 and a drain electrode 4 are formed in ohmic contact with this active layer 2. Next, a positive resist film 5 made of an organic polymer is formed on the entire surface of the substrate l. An opening 5' having a width of 1 μm is formed between the source electrode 3 and the drain electrode 4 of this resist film 5 by ordinary photolithography. Then, a metal layer 6 is formed on the resist film 5 and on the opening 5' where the active layer 2 is exposed. (Figure 1(a)
) The resist film 5 is dissolved and removed, and the metal layer 6 other than the opening 5' is removed.
By removing the gate electrode 7, the gate electrode 7 corresponding to the area of the opening 5'' is formed. (Lift-off method) Heat treatment is performed on the surface of the substrate 1 including the exposed active layer 2 region between 4 and 4 in an oxygen atmosphere. The relationship between the heat treatment time and the thickness of the oxide layer (measured by ellipsometry) is shown in Figure 2.As is clear from the figure, the thickness of the oxide layer is 1.5nm, but by heat treatment for more than 1 hour, it becomes 1.5nm.
.. The film thickness is approximately 6 nm.

それ以上の時間、加熱処理しても膜厚は飽和しており、
増加しないことがわかる。なお、この時の雰囲気は、大
気に限らず酸素を含む酸化性の雰囲気で・あれば良い。
Even if the heat treatment is continued for a longer time, the film thickness remains saturated.
It can be seen that there is no increase. Note that the atmosphere at this time is not limited to the air, but may be any oxidizing atmosphere containing oxygen.

その後、活性層2上の全面に厚さ1100nの窒化シリ
コン膜8(SiN)をプラズマCVD法により形成する
。このプラズマCVD法は、基板1を230℃に加熱し
、シラン(S i H,)ガスと窒素ガスとの反応によ
り約8分間行なわれる。
Thereafter, a silicon nitride film 8 (SiN) having a thickness of 1100 nm is formed on the entire surface of the active layer 2 by plasma CVD. This plasma CVD method is performed by heating the substrate 1 to 230° C. and reacting silane (S i H,) gas and nitrogen gas for about 8 minutes.

なお、保護用誘電体膜としては、窒化シリコン膜以外に
、酸化シリコン膜なとの緻密な絶縁膜を用いることがで
きる。
Note that as the protective dielectric film, in addition to the silicon nitride film, a dense insulating film such as a silicon oxide film can be used.

ソース電極3およびドレイン11t’M4上の窒化シリ
コン膜8を部分的に除去し、配線用金属9.9′を形成
する。(第1図(C)) 以上の実施例1の工程で作成したFETのゲート・ドレ
イン電極間の電圧・電流特性を実施例1として第3図に
示す。また、加熱処理を行なわず他の工程は上記実施例
1と同一の場合を比較例として記載した。
Silicon nitride film 8 on source electrode 3 and drain 11t'M4 is partially removed to form wiring metal 9.9'. (FIG. 1(C)) FIG. 3 shows the voltage/current characteristics between the gate and drain electrodes of the FET manufactured by the process of Example 1 as Example 1. In addition, a case where the heat treatment was not performed and the other steps were the same as in Example 1 was described as a comparative example.

第3図から明らかなように、比較例では一16Vの電圧
を印加し、50μAの電流が流れた状態でFETの破壊
が生じた。しかし、実施例1では−19v以上の電圧を
印加し1mA以上の電流を繰返し流してもFETの破壊
は生じなかった。
As is clear from FIG. 3, in the comparative example, the FET was destroyed when a voltage of -16 V was applied and a current of 50 μA flowed. However, in Example 1, even if a voltage of -19 V or more was applied and a current of 1 mA or more was repeatedly passed, the FET was not destroyed.

なお、上記の実施例1ではリフトオフによるゲート電極
の形成後に加熱処理を行っているが、他の実施例(実施
例2)として、この加熱処理の替わりに酸素雰囲気でプ
ラズマ処理を行うことも可能である。
Note that in Example 1 above, heat treatment is performed after forming the gate electrode by lift-off, but in another example (Example 2), plasma treatment can be performed in an oxygen atmosphere instead of this heat treatment. It is.

プラズマ処理は、酸素ガス中でバレル型プラズマ装置を
用いて行なう。この酸素ガス中のプラズマ処理は、ガス
圧:0.5torr、基板温度:50℃で、20分間行
なう。また、酸素ガスと四ふっ化炭素(CF、)ガスの
混合ガス中のプラズマ処理は、ガス比(酸素ガス/四ふ
っ化炭素ガス)を5/1、混合ガス圧:0.5torr
、基板温度は室温で、5分間行なう。プラズマ処理時間
と酸化物層の膜厚(エリプソメトリ−のによる測定)の
関係を第4図に示す。同図から明らかなように、酸化物
層の膜厚はプラズマ処理前に2nm以下であるが、酸素
ガス中で20分以上、混合ガス中で5分以上でプラズマ
処理することで7nm程度の膜厚に形成される。それ以
上の時間、プラズマ処理しても膜厚は飽和しており、増
加しないことがわかる。なお、プラズマ処理の雰囲気は
、酸素ガス、亜酸化窒素(N、O)などの酸化雰囲気ガ
スを用いることができる。
The plasma treatment is performed in oxygen gas using a barrel plasma device. This plasma treatment in oxygen gas is performed at a gas pressure of 0.5 torr and a substrate temperature of 50° C. for 20 minutes. In addition, for plasma treatment in a mixed gas of oxygen gas and carbon tetrafluoride (CF) gas, the gas ratio (oxygen gas/carbon tetrafluoride gas) is 5/1, and the mixed gas pressure is 0.5 torr.
, and the substrate temperature is room temperature for 5 minutes. FIG. 4 shows the relationship between the plasma treatment time and the thickness of the oxide layer (as measured by ellipsometry). As is clear from the figure, the film thickness of the oxide layer is 2 nm or less before plasma treatment, but by plasma treatment for 20 minutes or more in oxygen gas and 5 minutes or more in mixed gas, the thickness of the oxide layer is about 7 nm. Formed thickly. It can be seen that even if the plasma treatment is performed for a longer period of time, the film thickness is saturated and does not increase. Note that an oxidizing atmosphere gas such as oxygen gas or nitrous oxide (N, O) can be used as the atmosphere for the plasma treatment.

以上の実施例2の工程で作成したFETのゲート・ドレ
イン電極間の電圧・電流特性を実施例2として第5図に
示す。また、プラズマ処理を行なわず他の工程は上記実
施例1と同一の場合を比較例として記載した。
FIG. 5 shows the voltage/current characteristics between the gate and drain electrodes of the FET produced through the steps of Example 2 as Example 2. Further, a case where the plasma treatment was not performed and the other steps were the same as in Example 1 was described as a comparative example.

第5図から明らかなように、比較例では、−15Vの電
圧を印加し約200μAの電流が流れた状態でFETの
破壊が生じた。しかし、実施例2では一17V以上の電
圧を印加し1mA以上の電流を繰返し流してもFETの
破壊は生じなかった。
As is clear from FIG. 5, in the comparative example, the FET was destroyed when a voltage of -15V was applied and a current of about 200 μA flowed. However, in Example 2, the FET was not destroyed even when a voltage of -17 V or more was applied and a current of 1 mA or more was repeatedly passed.

なお、以上の実施例ではレジスト膜によるリフトオフ法
を用いているが、レジスト膜の替わりに酸化シリコン膜
などの絶縁膜を用いることも可能である。
Note that although the above embodiment uses a lift-off method using a resist film, it is also possible to use an insulating film such as a silicon oxide film instead of the resist film.

[発明の効果] 以上説明したように、本発明は、半導体上にソース電極
、ドレイン電極およびショットキー接合を形成するゲー
ト電極を備えた電界効果型トランジスタの製造方法にお
いて、前記ソース電極およびドレイン電極を形成する第
1の工程、前記ゲート電極を形成する第2の工程、酸化
雰囲気下での加熱処理またはプラズマ放電処理により、
前記ソース電極およびドレイン電極間に露出した上記半
導体の表面上に酸化物層を形成する第3の工程、該表面
上に誘電体膜を形成する第4の工程を行なうものである
[Effects of the Invention] As described above, the present invention provides a method for manufacturing a field effect transistor including a source electrode, a drain electrode, and a gate electrode forming a Schottky junction on a semiconductor. A first step of forming the gate electrode, a second step of forming the gate electrode, heat treatment in an oxidizing atmosphere or plasma discharge treatment,
A third step of forming an oxide layer on the surface of the semiconductor exposed between the source electrode and the drain electrode, and a fourth step of forming a dielectric film on the surface are performed.

したがって、本発明による電界効果型トランジスタは半
導体表面およびゲート電極表面が安定な酸化物により被
覆されるため、ブレークダウン電圧を劣化させない保護
用誘電体膜の形成が可能となる。
Therefore, in the field effect transistor according to the present invention, since the semiconductor surface and the gate electrode surface are coated with a stable oxide, it is possible to form a protective dielectric film that does not deteriorate the breakdown voltage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(c)は、本発明の一実施例を説明する
ための断面図、 第2図は、加熱処理時間と酸化膜の膜厚の関係を示した
図、 第3図は、実施例1および比較例により作成したFET
のゲート・ドレイン電極間の電圧・電流特性を示す図、 第4図は、加熱処理時間と酸化膜の膜厚の関係を示した
図、 第5図は、実施例2および比較例により作成したFET
のゲート・ドレイン電極間の電圧・電流特性を示す図で
ある。 図において、 1・・・基板、2・・・活性層、3・・・ソース電極、
4・・・ドレイン電極、5・・・レジスト膜、5′・・
・開口部、6・・・金属層、7・・・ゲート電極、8・
・・窒化シリコン膜、9.9′・・・配線用金属。 第 図 箪 図 ′°閣−−−−−−−−−■ 加熱処理時間(hr) 箪 図
Figures 1 (a) to (c) are cross-sectional views for explaining one embodiment of the present invention; Figure 2 is a diagram showing the relationship between heat treatment time and oxide film thickness; Figure 3; is the FET made according to Example 1 and Comparative Example
Figure 4 is a diagram showing the relationship between heat treatment time and oxide film thickness, Figure 5 is a diagram showing the voltage and current characteristics between the gate and drain electrodes of FET
FIG. 3 is a diagram showing the voltage/current characteristics between the gate and drain electrodes of FIG. In the figure, 1...substrate, 2...active layer, 3...source electrode,
4...Drain electrode, 5...Resist film, 5'...
・Opening portion, 6... Metal layer, 7... Gate electrode, 8.
...Silicon nitride film, 9.9'...Metal for wiring. Diagram: Tanzu'°Kaku---■ Heat treatment time (hr) Tanzu

Claims (2)

【特許請求の範囲】[Claims] (1)半導体上にソース電極、ドレイン電極およびショ
ットキー接合を形成するゲート電極を備えた電界効果型
トランジスタの製造方法において、前記ソース電極およ
びドレイン電極を形成する第1の工程、前記ゲート電極
を形成する第2の工程、酸化雰囲気下での加熱処理また
はプラズマ放電処理により、前記ソース電極およびドレ
イン電極間に露出した上記半導体の表面上に酸化物層を
形成する第3の工程、該表面上に誘電体膜を形成する第
4の工程を行なうことを特徴とした電界効果型トランジ
スタの製造方法。
(1) In a method for manufacturing a field effect transistor including a source electrode, a drain electrode, and a gate electrode forming a Schottky junction on a semiconductor, a first step of forming the source electrode and the drain electrode, a second step of forming an oxide layer on the surface of the semiconductor exposed between the source electrode and the drain electrode by heat treatment or plasma discharge treatment in an oxidizing atmosphere; 1. A method for manufacturing a field effect transistor, comprising performing a fourth step of forming a dielectric film.
(2)前記第3の工程において、前記酸化物層の膜厚が
飽和するまで前記プラズマ放電処理または加熱処理を行
うことを特徴とした第1項記載の電界効果型トランジス
タの製造方法。
(2) The method for manufacturing a field effect transistor according to item 1, wherein in the third step, the plasma discharge treatment or heat treatment is performed until the thickness of the oxide layer is saturated.
JP11056890A 1990-04-27 1990-04-27 Manufacture of field-effect transistor Pending JPH0410549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11056890A JPH0410549A (en) 1990-04-27 1990-04-27 Manufacture of field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11056890A JPH0410549A (en) 1990-04-27 1990-04-27 Manufacture of field-effect transistor

Publications (1)

Publication Number Publication Date
JPH0410549A true JPH0410549A (en) 1992-01-14

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0642175A1 (en) * 1993-09-07 1995-03-08 Murata Manufacturing Co., Ltd. Semiconductor element with Schottky electrode and process for producing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0642175A1 (en) * 1993-09-07 1995-03-08 Murata Manufacturing Co., Ltd. Semiconductor element with Schottky electrode and process for producing the same
US5578844A (en) * 1993-09-07 1996-11-26 Murata Manufacturing Co., Ltd. Semiconductor element and process for production for the same

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