JPS6360566A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a short channel effect by forming two semiconductor regions having impurity concentration higher than a semiconductor substrate onto an insulating film shaped onto the substrate at a regular interval and a control electrode between both regions. CONSTITUTION:An excellent insulating film 14 having an extremely small interface level is shaped onto an Si substrate 16 exceedingly thinly, an N<+> region 15 is formed, and a gate electrode 11 and source-drain electrodes 12, 13 are shaped. Accordingly, when gate voltage is applied and an inversion layer is formed under the gate electrode 11, the insulating film 14 can be thinned, thus taking an ohmic contact by tunnel currents the N<+> region 15 and a channel layer (the inversion layer) while between extremely reducing a short channel effect.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is based on M r S (Metol-Insulat
or -Semico (Iductor) type F E'
T (1;'1eld EffectTra(Isist
ar), and relates to a semiconductor device suitable for suppressing short channel effects sometimes in submicron gate lengths.

[Conventional technology]

Conventionally, S i -MO8F'ET (Metal-Qxi
de -8elniCOQauCter-, @1cld
gffet'l'transistor] is a transistor that is formed by thermally oxidizing a Si substrate, depositing a highly heat-resistant gate electrode memory, processing the gate using photolithography, and forming source and drain regions using ion implantation. Ta.

Regarding the structure of the conventional n-chiginnel MO8-FET,
For example, Physics of Semiconductor Devices, Niss M Niss CII.

2nd edition John Wiley and Tens, page 434 Figure 3 (physics of Sem1conduct
or j)evi ces.

5-M-8ze 2nd edition John
Wiley & 5onspp, 434. Fig・3
) is shown. A conventional groove is shown in FIG. 2(a). p-type substrate 6 is fi-oxidized sio, z4 is Ir1sula
As tr, gate meta kl, source/drain region 5
is formed by n'' ion implantation technology, and 2.3 indicates a source/drain electrode.It is widely known that when such an FET is implanted as it is, the threshold voltage Vsh becomes deeper as the gate length becomes finer.

A specific example is shown in FIG. 2(b). White circles are experimental values. Such short channel effects are noticeable at submicron gate lengths, and are difficult to detect in actual DRAMs (1) yHamic processing.
This has become an obstacle to soil removal when applied to dom access memory.

[Problem that the invention seeks to solve]

51-M08FET in a wide sense
4etal-Insulator-8emicondu
ctr) mainly uses ion implantation technology, so the n0 region of the source/drain is the f of the key 1 rear inversion layer.
Because of the side effects, such pronounced short channel effects were unavoidable.

An object of the present invention is to provide an element structure suitable for preventing the short tiginel effect described above.

[Means for solving problems]

Means for achieving the above object are shown in FIG. 1 for the case of a silicon MISFET.

A 3i substrate 16 is coated with a conductive insulating film 1 with extremely few interface states.
4 is formed extremely thin (approximately 50 Å or less), and is similar to n9 type Si (impurity concentration of about 10'' cm-3).
After forming the region 15 for about 3000 people, each gate electrode 11
, forming the source/drain electrodes 12 and 13. [Operation] When an inversion layer is formed under the gate 1 by applying a gate voltage, the insulating film can be made thinner, so that the N9 region 15 and the channel layer (inversion layer) are formed. It is possible to make ohmic contact between the two through the tunnel flow.

Also, since the n0 region is formed above the channel layer,
Short channel effects become extremely small.

The n0 region 15 and the insulating film 14 are selectively made of Si in the n0 region.
Since it is possible to remove only the wafer, it is possible to easily form the gate electrode, and the threshold voltage in the wafer plane can be made uniform, making it suitable for LSI integration.

〔Example〕

Hereinafter, the present invention will be explained in more detail through Examples.

[Real = column l]

An example in which the present invention is applied to a Si-MOSFET is shown in FIGS. 3(a), (b), and (C).

Very high purity (impurity concentration lX) is placed on the p-type Si substrate 36.
10" saw-3 p type) Si layer 37 with a thickness of 1 am
M B E (Molecular Beam gpi
After forming υ by dry oxidation (taxy), dry oxidation is performed to form an insulating film 34 made of 20 thermal oxide films, and then phosphorus (P) is
3000 x 10"Ocm-" containing n0 layer 35
A gate photoresist 30 was formed, and photoresist processing with a gate length of 0.3 μm was performed by electron beam lithography (FIG. 3(a)).

Next, by dry etching, the gate portion is selectively etched.
After removing the Si layer, a SiN film 41 was deposited on the entire surface of the SOO layer by photo-CVD at room temperature (FIG. 3(b)).

Next, SiN in other parts is removed by dry etching so as to leave the SiN film 41 adhered to the side wall of the 09 layer 35.
The gate electrode 31i was formed using the 7-off method with 3000 person evaporation to form the A/ film that would become the gate metal.Furthermore, the source and drain electrodes 32 and 33 were formed using the usual method (see Fig. 3).
C)).

After this, the gate electrode 31 and the n0 region 35 are sandwiched together.
Ng41 was removed by wet etching, a passivation film was formed, and 5to2 was formed by CVDm.

In this embodiment, P (phosphorus) is used as a dopant in the mouth 0 region 35, but As (arsenic) may also be used.

In addition, although the case of an n-channel MO8FET is shown, in the case of a p-channel Mo5t"ET, all the n-type parts in this example need to be replaced with p-type, and in the case of a 0MO8 (complementary type MO8) FET, It is better to combine both.

Using the S1-MOSFET of Example 4, we formed a 64-megabyte SRAM (3Tic andom Access Memory) with a gate length of 0.2 μm, and a high-speed access time of I0On8 was achieved with a high yield. .

In this example, the case of Si MOSFET is shown, but the case of AtGaAs/GaAs heterojunction or Q
In the case of rA I S F E T in aAs, MI8FE'l' can be formed using a similar method.

In addition, in order to increase the tunnel current and improve the ohmic properties, Ta2α is used instead of 810* as the material of the insulating film 34.
It is also possible to use hAlzO3* S isN<, etc.

〔Effect of the invention〕

According to the present invention, the gate insulating film can be made extremely thin (50 Å or less), and the + (or p'') region is formed above through the gate oxide film, so: 1) the short channel effect is extremely small;

2) Since the 00 (or pl region) can be selectively removed from the gate oxide film, a highly reliable transistor element can be formed.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a transistor according to the present invention, FIG. 2 is a sectional view of a transistor having a conventional structure, and FIG. 3 is a process diagram showing an embodiment of the present invention. 1.11.31...Gate metal, 2, 3, 12゜1
3.32.33...Source/drain electrode, 4°14
．． 34...Gate insulating film, 5, 15.35... Mouth region, 41...SiN film, 30...Resist, 6°16.36...8i substrate%37...And- Pull type S1 epitaxial layer. Agent: Patent attorney Ogawa Yanagiba. No. J Mouthless 2 Figure Gate + Lri C7ya] Otsu P-type Sj Foundation Stone 5. ,/b5 Dojo Neta - Figure 13

Claims (1)

[Scope of Claims] 1. An insulating film formed on at least a predetermined semiconductor substrate, and two semiconductor regions formed on the insulating film and formed at a predetermined interval and made of a semiconductor having a higher impurity concentration than the semiconductor substrate. and a control electrode provided between the two semiconductor regions on the insulating film. 2. In the semiconductor device according to claim 1,
A semiconductor device, wherein the inversion layer formed on the semiconductor substrate and the semiconductor region are ohmically connected by a tunnel current.