JPS58114462A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an FET which operates as designed by forming an insulating film on a semi-insulating III-V Group semiconductor substrate or on the part f an n type layer in a substrate, covering it with an n<+> type layer, opening a hole at the layer, removing the insulating film, and attaching a Schottky junction metal onto the exposed layer. CONSTITUTION:A CVD SiO2 3 is formed in a strip shape on an n type epitaxial layer 2 on a semi-insulating GaAs substrate 1, is covered with an n<+> type epitaxial layer 4, AuGe/Ni electrodes 5 are deposited on both sides of the film 3, and are annealed at 400 deg.C. Then, a resist mask opened with a window narrower than the layer is formed on the layer 3, and the layer 4 and the film 3 are sequentially etched and removed. Al 7 is deposited on the exposed layer 2, the resist 6 and the aluminum 7 on the resist are removed, thereby completing an FET. According to this configuration, the etching residue of the layer 4 or the excess etching of the layer 2 of the problems in the conventional method can be completely prevented, the layer 4 for reducing a series resistance can be formed with good reproducibility, and an FET which operates as designed can be obtained.

Description

[Detailed Description of the Invention] The present invention: - Forms an n semiconductor layer with good reproducibility to reduce series resistance between the teeth and the gate and between the drain and the gate of a field effect transistor (FBT) made of an m-v group semiconductor. Regarding how to.

In order to reduce the resistance between the source and gate and the resistance between the drain and gate, an n
In the step of forming a type 1 semiconductor layer and removing the n+ type semiconductor layer at the gate portion, the n layer has conventionally been removed using Fi, chemical or reactive ion etching (recess structure). However, in the above etching method, in order to remove only the n+ type semiconductor layer, strict etching conditions (for chemical etching, the composition of the etchant, once the etching time, 9 for reactive sputter etching, the selection of the etching gas,
gas pressure, etching time, etc.), and reproducibility was poor. Therefore.

Is there an n+ type semiconductor layer left? t Since a part of the n-type semiconductor operating layer is etched, the FET operation is not as designed.
It was embarrassing to do so.

The object of the invention is to provide a method that overcomes the above-mentioned drawbacks.

The present invention provides a semi-insulating ■-v group semiconductor substrate with n
By removing the type semiconductor and the insulation and forming a Schottky gate on the surface of the n-type semiconductor layer exposed there, the remaining part of the n+ type semiconductor layer or part of the n-type semiconductor layer, which was a problem with the conventional method, can be removed. It is designed to solve problems such as etch-off.

A GaAs FET according to an embodiment of the present invention will be described below.

(n=IX1017CIL-', j:QJPB
) as shown in Figure 1).

Next, a 5i02 film (30
00~6oooX)? Attachment 9 ~4 using normal photolithography and etching solution (HF:NHaF=1:10)
Leave 3t of 8 i02 films with a stripe width of Pm (second
figure). Next, an n+ type GaAs layer 4 (
n=2~5X10"cyn4.t=0.2~0.5
Figure 3) 1 5i by normal glue lift-off method
10 Au Ge/Ni as n electrode material on the outside of 02
00A to 3000A, vacuum evaporated, and heat treated at 400°C for 1 minute (Fig. 4) 1) Next, a positive type resist was applied.

The Siow film 3 previously formed using the normal photo ring 2
on the stripe narrower than the previous stripe dimension (~2p
m) Open the window (Figure 5). In the figure, 5 is AuGe
/N i is an n-electrode, and 6 is a positive resist layer. Next, the n+ type GaAs layer 4t-Hz of the part where the window was opened
80a:H20z:HzO=18:1:1 etching solution for 15 to 38 seconds, then etching the 8t02 film 3 with H.
The 5i02 film was completely removed using an etching solution of F:NH4=1:10 (Figure 8). A finished FET product is completed through the above steps.

In the above embodiments, GaAs is used as the semi-insulating ■-■ group semiconductor substrate; however, similar results can be obtained with Ink, GaP, etc. instead of GaAs. Just n-type.

n-type, n-type InP or GaP instead of n+ type GaAs
9 and 0.0.
5% methanol/bromine may be used.

In addition, an example in which n-type and n+-type semiconductor layers were formed by MBE growth was explained, and 9. 'MOC instead of MBB growth.
VD growth, liquid phase growth, vapor phase growth, ion implantation.

Similar results are obtained with n-type diffusion. However, in the case of ion implantation, after the ion implantation, annealing is only required to activate the implanted ion species.

In addition, although Si02 was used as the insulating film, e5tyx
Si3N4.O instead. Similar results are obtained when using Al203t. The only difference is the etching solution. Also.

AuGe/Auk was used as the n-electrode material, but eAuG
AuGe/Au, Au8n, A instead of e/Ni0
Even if you use usie. Alt as gate electrode material
However, instead of Al, Au, Cr/Au, Ti
, Pt, Ti/W, etc. will give similar results.
However, the barrier height between the gate electrode material and the n-type semiconductor is only slightly increased.

According to the present invention, the remaining n-type semiconductor layer and the etching of the n-type semiconductor active layer, which were problems in the conventional method, are completely eliminated, so reproducibility in PET manufacturing is improved.

[Brief explanation of the drawing]

FIGS. 1 to 8 show FET Iil! according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a substrate dripping in a manufacturing process. 1... Semi-insulating GaAs substrate 2... N-type QaAs layer 3... SiO thick film 4... N+ type GaAs layer 5...・N electrode 7...Al for gate electrode

Claims (1)

[Claims] An n-type semiconductor layer is formed on or in a semi-insulating 111-V group semiconductor substrate, and an insulating film is entirely formed on a part of the n-type semiconductor layer. A method for manufacturing a semiconductor device, comprising forming a male-type semiconductor layer, removing the male-type semiconductor and the insulating film on the insulating film, and forming a metal that forms a Schottky junction with the n-type semiconductor in that portion. .