KR940016952A - Method for manufacturing gallium arsenide field effect transistor - Google Patents

Method for manufacturing gallium arsenide field effect transistor Download PDF

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Publication number
KR940016952A
KR940016952A KR1019920024462A KR920024462A KR940016952A KR 940016952 A KR940016952 A KR 940016952A KR 1019920024462 A KR1019920024462 A KR 1019920024462A KR 920024462 A KR920024462 A KR 920024462A KR 940016952 A KR940016952 A KR 940016952A
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South Korea
Prior art keywords
thin film
gallium arsenide
field effect
effect transistor
gate
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KR1019920024462A
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Korean (ko)
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KR950008264B1 (en
Inventor
양전욱
조낙희
최영구
최성우
이경호
조경익
Original Assignee
양승택
재단법인 한국전자통신연구소
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Priority to KR1019920024462A priority Critical patent/KR950008264B1/en
Publication of KR940016952A publication Critical patent/KR940016952A/en
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Publication of KR950008264B1 publication Critical patent/KR950008264B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]

Abstract

본 발명은 갈륨비소를 이용한 금속반도체 전계효과 트랜지스터의 제조방법에 관한 것으로, 반절연기판에 P형 매몰층과 형성하고 하층박막과 상층박막을 순차로 증착하고, 상층박막상에 포토레지스트막의 패턴을 형성한 후 마스크로서 사용하여 상층박막을 과식각하며, 방향성 박막을 증착하고 포토레지스터막을 리프트 - 오프하여 상층박막의 미세패턴을 형성하고, 하층박막을 식각하여 노출되는 반절연 기판 위에 게이트 금속을 증착한 후 게이트 저항의 감소를 위한 저저항 금속을 증착하며, 게이트 패턴의 형성을 위한 리프트 - 오프를 수행한 후 저저항금속을 마스크로서 사용하여 게이트 금속을 식각한 것이다.The present invention relates to a method for fabricating a metal semiconductor field effect transistor using gallium arsenide. The present invention relates to a P-type buried layer on a semi-insulating substrate, and sequentially deposits a lower thin film and an upper thin film. After forming, it is used as a mask to overetch the upper thin film, deposit a directional thin film, lift-off the photoresist film to form a fine pattern of the upper thin film, and deposit the gate metal on the semi-insulating substrate exposed by etching the lower thin film. After the low resistance metal is deposited to reduce the gate resistance, the gate metal is etched using the low resistance metal as a mask after the lift-off for the formation of the gate pattern.

Description

갈륨비소 전계효과 트랜지스터의 제조방법Method for manufacturing gallium arsenide field effect transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 내지 제 8 도는 본 발명에 따른 제조공정단면도.1 to 8 is a cross-sectional view of the manufacturing process according to the present invention.

Claims (4)

갈륨비소 전계효과 트랜지스터를 제조하는 방법에 있어서, 반절연기판(1)에 P형 매몰층(2)과 활성층(3)을 형성하고 하층박막(4)과 상층박막(5)를 순차로 증착하는 단계와, 상기 상층박막(5)상에 포토레지스트막(6)의 패턴을 형성한 후 마스크로서 사용하여 상기 상층박막(5)을 과식각하는 단계와, 방향성박막(7)을 증착하고 상기 포토레지스트막(6)을 리프트 - 오프하여 상기 상층박막(5)의 미세패턴을 형성하는 단계와, 상기 하층박막(4)을 식각하여 노출되는 상기 반절연기판(1)위에 게이트금속(8)을 증착한 후 게이트저항의 감소를 위한 저저항금속(9)을 증착하는 단계와, 게이트 패턴의 형성을 위한 리프트 - 오프를 수행한 후 상기 저저항금속(9)을 마스크로서 사용하여 상기 게이트금속(8)을 식각하는 단계를 포함하는 것을 특징으로 하는 갈륨비소 전계효과 트랜지스터의 제조방법.In the method for manufacturing a gallium arsenide field effect transistor, a P-type buried layer (2) and an active layer (3) is formed on the semi-insulating substrate (1), and the lower thin film (4) and the upper thin film (5) are sequentially deposited. Forming a pattern of the photoresist film 6 on the upper thin film 5 and overetching the upper thin film 5 using a mask, and depositing a directional thin film 7 and Lifting-off the resist film 6 to form a fine pattern of the upper thin film 5, and etching the lower thin film 4 to form a gate metal 8 on the exposed semi-insulating substrate 1. Depositing the low resistance metal 9 for the reduction of the gate resistance after deposition, and performing lift-off for the formation of the gate pattern, and then using the low resistance metal 9 as a mask. Gallium arsenide field effect comprising the step of etching 8) Method of manufacturing a transistor. 제 1 항에 있어서, 상기 하층방막(4)은 Si, SiO, SiN 또는 SiO2와 같은 절연물로 이루어지는 것을 특징으로 하는 갈륨비소 전계효과 트랜지스터의 제조방법.The method of claim 1, wherein the lower layer bangmak (4) A method of manufacturing a GaAs field-effect transistor which comprises an insulating material such as Si, SiO, SiN or SiO 2. 제 1 항에 있어서, 상기 저저항금속(9)은 AuGe/Ni/Au의 증착과 열처리공정에 의해 형성되고, 절연막 보조 리프트 - 오프공정 또는 포토레지스트막을 이용한 리프트 - 오프공정에 의해 패턴이 형성되는 것을 특징으로 하는 갈륨비소 전계효과 트랜지스터의 제조방법.The method of claim 1, wherein the low resistance metal (9) is formed by deposition and heat treatment of AuGe / Ni / Au, the pattern is formed by an insulating film assisted lift-off process or a lift-off process using a photoresist film A method of manufacturing a gallium arsenide field effect transistor, characterized in that. 제 3 항에 있어서, 상기 열처리공정은 400℃의 온도에서 수행되고, 상기 포토레지스트막은 돌출형태 또는 음의 기울기를 갖는 것을 특징으로 하는 갈륨비소 전계효과 트랜지스터의 제조방법.The method of claim 3, wherein the heat treatment is performed at a temperature of 400 ° C., and the photoresist film has a protruding shape or a negative slope. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920024462A 1992-12-16 1992-12-16 Making method of gaas fet KR950008264B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920024462A KR950008264B1 (en) 1992-12-16 1992-12-16 Making method of gaas fet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920024462A KR950008264B1 (en) 1992-12-16 1992-12-16 Making method of gaas fet

Publications (2)

Publication Number Publication Date
KR940016952A true KR940016952A (en) 1994-07-25
KR950008264B1 KR950008264B1 (en) 1995-07-26

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