KR940016939A - Method of manufacturing gallium arsenide metal field effect transistor - Google Patents

Method of manufacturing gallium arsenide metal field effect transistor Download PDF

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Publication number
KR940016939A
KR940016939A KR1019920025004A KR920025004A KR940016939A KR 940016939 A KR940016939 A KR 940016939A KR 1019920025004 A KR1019920025004 A KR 1019920025004A KR 920025004 A KR920025004 A KR 920025004A KR 940016939 A KR940016939 A KR 940016939A
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KR
South Korea
Prior art keywords
region
gallium arsenide
field effect
effect transistor
pattern
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Application number
KR1019920025004A
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Korean (ko)
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KR960001615B1 (en
Inventor
이경호
양전욱
최영규
조경익
Original Assignee
양승택
재단법인 한국전자통신연구소
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Priority to KR92025004A priority Critical patent/KR960001615B1/en
Publication of KR940016939A publication Critical patent/KR940016939A/en
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Publication of KR960001615B1 publication Critical patent/KR960001615B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

Abstract

본 발명은 갈륨비소 반도체의 표면에 절연막을 증착하고 채널부위에 절연막이 잔류하도록 패터닝과 에칭을 한 후 N+영역을 형성하기 위한 조건의 이온주입을 전극접합영역과 절연막으로 보조된 채널부위에 일회 실시하여 N+영역과 채널부위의 저농도 N 영역을 동시에 형성시키고 오옴전극과 리세스에칭(recess etching)된 영역에 게이트를 형성하는 금속반도체 전계효과 트랜지스터(Metal Semiconductor Field Effect Transistor : MESFET)의 제조방법.The present invention deposits an insulating film on the surface of a gallium arsenide semiconductor, patterning and etching so that the insulating film remains on the channel portion, and ion implantation under conditions for forming an N + region is performed once on the electrode junction region and the channel region assisted by the insulating layer A method of manufacturing a metal semiconductor field effect transistor (MESFET) which simultaneously forms an N + region and a low concentration N region of a channel region and forms a gate in an ohmic electrode and a recess etched region. .

Description

갈륨비소 금속반도체 전계효과 트랜지스터의 제조방법Method of manufacturing gallium arsenide metal field effect transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래의 내열성 게이트를 이용하는 GaAs MESFET 제조방법, 제 2 도는 본 발명에 따른 절연막 투과 이온주입에 의한 GaAs MESFET 제조방법.1 is a GaAs MESFET manufacturing method using a conventional heat-resistant gate, Figure 2 is a GaAs MESFET manufacturing method by the insulating film transmission ion implantation according to the present invention.

Claims (1)

갈륨비소 금속반도체 전계효과 트랜지스터를 제조하는 방법에 있어서, 반절연 갈륨비소 반도체 기판(201)상에 질화규소막(202)과 감광막(203)을 순차로 도포한 후 상기 감광막(203)의 N+채널영역 패턴을 형성하고 N+영역의 상기 질화규소막(202)을 식각하는 단계와, 소자영역의 상기 감광막(203)을 제거하여 N패턴(204)을 형성하고 규소이온을 주입하는 단계와, 상기 감광막(203)을 제거한 후 절연막(206)을 전표면에 증착하고 열처리하는 단계와, RIE에 의해 상기 절연막(206)을 제거하고 감광막(207)을 도포하여 오음전극용 패턴을 형성한 후 금속(208)을 증착하고 리프트오프에 의해 오옴전극을 형성하는 단계와, 감광막(209)을 도포하여 게이트의 패턴을 형성하고 RIE에 의해 상기 규소질화막(202)을 식각한 후 금속(210)을 증착하여 게이트전극을 형성하는 단계를 포함하는 것을 특징으로 하는 갈륨비소 금속반도체 전계효과 트랜지스터의 제조방법.In the method for manufacturing a gallium arsenide metal field effect transistor, after applying the silicon nitride film 202 and the photosensitive film 203 in sequence on the semi-insulating gallium arsenide semiconductor substrate 201, N + channel of the photosensitive film 203 Forming a region pattern and etching the silicon nitride film 202 in the N + region, removing the photosensitive film 203 in the device region to form an N pattern 204, and implanting silicon ions; After removing the 203, the insulating film 206 is deposited on the entire surface and heat-treated, and the insulating film 206 is removed by RIE, and the photosensitive film 207 is applied to form a pattern for the negative electrode, and then the metal 208 ) And forming an ohmic electrode by lift-off, applying a photoresist layer 209 to form a pattern of a gate, etching the silicon nitride layer 202 by RIE, and then depositing a metal 210 to form a gate. Forming an electrode Gallium arsenide process for producing a metal semiconductor field effect transistor, characterized in that the. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92025004A 1992-12-22 1992-12-22 Making method of gaas metal semiconductor fet KR960001615B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92025004A KR960001615B1 (en) 1992-12-22 1992-12-22 Making method of gaas metal semiconductor fet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92025004A KR960001615B1 (en) 1992-12-22 1992-12-22 Making method of gaas metal semiconductor fet

Publications (2)

Publication Number Publication Date
KR940016939A true KR940016939A (en) 1994-07-25
KR960001615B1 KR960001615B1 (en) 1996-02-02

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Application Number Title Priority Date Filing Date
KR92025004A KR960001615B1 (en) 1992-12-22 1992-12-22 Making method of gaas metal semiconductor fet

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KR960001615B1 (en) 1996-02-02

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