JPS5763863A - Preparatio of semiconductor device - Google Patents

Preparatio of semiconductor device

Info

Publication number
JPS5763863A
JPS5763863A JP13947880A JP13947880A JPS5763863A JP S5763863 A JPS5763863 A JP S5763863A JP 13947880 A JP13947880 A JP 13947880A JP 13947880 A JP13947880 A JP 13947880A JP S5763863 A JPS5763863 A JP S5763863A
Authority
JP
Japan
Prior art keywords
hole
layer
operation layer
resist
photoengraving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13947880A
Other languages
Japanese (ja)
Inventor
Yoshinobu Kadowaki
Osamu Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13947880A priority Critical patent/JPS5763863A/en
Publication of JPS5763863A publication Critical patent/JPS5763863A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Abstract

PURPOSE:To form a sub-micro gate by forming a V-shaped hole on a wafer of an operation layer and a half-insulating layer both of which are made to grow epitaxially on a GaAs substrate, by photoengraving technology and anisotropic etching, in the manner that the hole reaches the operation layer, and by evaporating a metal layer on the surface of the hole. CONSTITUTION:A resist 6 having a slender window 7 is formed, by photoengraving, on the wafer having the n type operation layer 9 and the half-insulating layer 10 both of which are made to grow on the GaAs substrate 8. Then, by using the resist as a mask, the etching hole 11 having a V-shaped cross section and reaching the operation layer is formed by anisotropic etching. In order to form a Schottky junction being excellent in relation to the n type operation layer, a metal layer 12 such a Al is evaporated on an area including the hole. Then, the resist being removed, a gate electrode is formed. In this manner, slender line width of sub-micronorder can be formed easily by the photoengraving technology.
JP13947880A 1980-10-03 1980-10-03 Preparatio of semiconductor device Pending JPS5763863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13947880A JPS5763863A (en) 1980-10-03 1980-10-03 Preparatio of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13947880A JPS5763863A (en) 1980-10-03 1980-10-03 Preparatio of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5763863A true JPS5763863A (en) 1982-04-17

Family

ID=15246179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13947880A Pending JPS5763863A (en) 1980-10-03 1980-10-03 Preparatio of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5763863A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0087251A2 (en) * 1982-02-22 1983-08-31 Kabushiki Kaisha Toshiba Process for manufacturing a buried gate field effect transistor
JPS6057979A (en) * 1983-09-09 1985-04-03 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397784A (en) * 1977-02-07 1978-08-26 Hughes Aircraft Co Nonnactive gate gaaas fet transistor and method of producing same
JPS5676577A (en) * 1979-11-28 1981-06-24 Sumitomo Electric Ind Ltd Gaas schottky gate field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397784A (en) * 1977-02-07 1978-08-26 Hughes Aircraft Co Nonnactive gate gaaas fet transistor and method of producing same
JPS5676577A (en) * 1979-11-28 1981-06-24 Sumitomo Electric Ind Ltd Gaas schottky gate field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0087251A2 (en) * 1982-02-22 1983-08-31 Kabushiki Kaisha Toshiba Process for manufacturing a buried gate field effect transistor
JPS6057979A (en) * 1983-09-09 1985-04-03 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

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