JPS594173A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS594173A JPS594173A JP11315782A JP11315782A JPS594173A JP S594173 A JPS594173 A JP S594173A JP 11315782 A JP11315782 A JP 11315782A JP 11315782 A JP11315782 A JP 11315782A JP S594173 A JPS594173 A JP S594173A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- gate electrode
- gate
- double layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000012212 insulator Substances 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 24
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置の製造方法に関する。特に、ＭＰＳ
ＦＥＴの製造方法において、ゲート電極抵抗の減少を
伴うことなくゲート長の短いゲート？Ｉｉ′極の製造を
可能にするための改良に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, MPS
In the FET manufacturing method, is it possible to shorten the gate length without reducing the gate electrode resistance? This invention relates to improvements to enable the production of Ii' poles.
（２）技術の背景
近年の半導体装置の高集積化に伴い、Ｆ Ｉｎ Ｔにお
いてもその微細化が要求されており、ぞの信号伝達速度
もできるだけ大きいことが望ましい。信号伝達速度の指
数である最大発振周波数ｆＭＡＸけ、（１）式に示され
ろように伝達コンダクタンスｇｍに比例しゲート容１ｉ
−ｃｇθに逆比例する。(2) Background of the Technology With the recent increase in the degree of integration of semiconductor devices, miniaturization of F In T is also required, and it is desirable that the signal transmission speed of each is also as high as possible. The maximum oscillation frequency fMAX, which is an index of signal transmission speed, is proportional to the transfer conductance gm, as shown in equation (1), and the gate capacitance 1i
- inversely proportional to cgθ.
ｆＭＡＸ−二一一１．２１．２１１８１．１３０．（１
）Ｏｇｓ
すなわち、ｆＭＡＸ を増加するためには、ｇｍ
が大きく、Ｏｇｓが小さくなるような構造となすことが
必要である。換言すれば、ゲート長Ｌｇ を短縮する
ことが、ｆＭＡＸ を増加する上でも、また上記せる
装置の微細化に対しても有効である。fMAX-2111.21.21181.130. (1
) Ogs That is, in order to increase fMAX, gm
It is necessary to create a structure in which Ogs is large and Ogs is small. In other words, shortening the gate length Lg is effective in increasing fMAX and also in miniaturizing the device described above.
（３） 従来技術と問題膚
従来技術においては、ゲート長Ｌｇ を短縮するため
に、解像度の高い電子ビームリソグラフィー法、や、ゲ
ートメタルの斜め方向からの蒸肯法が試みられているが
、前者は加工速度が極めて遅いため、非現実釣手あり、
後者は装置の諸条件の設定に困難性があり、実用化は容
易〒はｔ「い。さらに、ゲート長の短縮に伴い、ゲート
電極抵抗が増大するという欠点がある。(3) Prior art and problems In the prior art, high-resolution electron beam lithography and vaporization of the gate metal from an oblique direction have been attempted in order to shorten the gate length Lg. Because the processing speed is extremely slow, there are unrealistic fishing techniques,
The latter method has difficulty in setting the various conditions of the device, but is not easy to put into practical use.Furthermore, it has the disadvantage that the gate electrode resistance increases as the gate length is shortened.
そこで、このような欠点を伴うことなく、簡易な工程で
ゲート長の短縮を可能にしうる方法の改良が留まれてい
る。Therefore, there remains a need to improve a method that can shorten the gate length through a simple process without having such drawbacks.
（４）発明の目的
本発明の目的は、この要請に応えることにあり、ＭＥＳ
Ｆ’：ｍＴの製造方法において、ゲート電極抵抗の減
少を伴うことなくゲート長の短いゲート電極の製造を可
能にする、ＭＫＳ ＦＥＴの製造方法を提イ共すること
にある。(4) Purpose of the invention The purpose of the present invention is to meet this demand, and
An object of the present invention is to provide a method for manufacturing an MKS FET that enables manufacturing a gate electrode with a short gate length without reducing gate electrode resistance in a method for manufacturing F':mT.
（５） 発明の構成
本発明の補機的構成は半導体活性層上に化学的性質の！
ｌ、ｒｒる２種類の絶縁物よりなる二重層を形成し、該
二重層をゲート形成予定領域以外から選択的に除去し、
前Ａ「゛、二重層σ）上層をなず物穎なエツチングする
エツチング剤を使用して前＝１ゲート形成予定領域上に
残留さハた二重層の上層の一部を除去して前記二重層の
下層の上面一部領塚を臨出させ、前記ゲート形成予定領
域の一部領域を残して１１１１の領域を覆うマスクを形
成した後、前記二重層の下層をなす物質をエンチングす
るエツチング剤を使用して前記マスクによって覆われて
いない領」ＪＲから前月■７下層を除去して該領域にお
いて前Ｎ＋Ｆ活性層を露出させて前記マスクによって覆
われていない領域に前記二重層をステップオーバーする
段差部を形成し、しかる後該段差部にゲート電欅な形成
する工程を含むことを特徴とする、半導体裂開の製造方
法にある。(5) Structure of the invention The auxiliary structure of the present invention has a chemical property on the semiconductor active layer!
forming a double layer made of two types of insulators l and rr; selectively removing the double layer from areas other than the region where the gate is to be formed;
Previous A (double layer σ) A part of the upper layer of the double layer remaining on the area where the gate is to be formed is removed using an etching agent that etches the upper layer without removing the upper layer. After exposing a portion of the upper surface of the lower layer of the double layer and forming a mask covering the region 1111 leaving a portion of the region where the gate is to be formed, an etching agent is applied to etch the material forming the lower layer of the double layer. Stepping over the double layer into the areas not covered by the mask by removing the lower layer and exposing the previous N+F active layer in the areas not covered by the mask. 1. A method of manufacturing a semiconductor cleavage, comprising the steps of: forming a gate electrode on the stepped portion; and then forming a gate electrode on the stepped portion.
本発明の発明者は、上記目的を達成さセーるためには、
例えば、第１図に示す如き形状すなわち、逆メサ型のゲ
ート電極を実現すればよいとの着想を得た。図において
ｌは基板であり、１１は絶縁膜であり、１０が逆メサ型
のゲート電極！ある。この構造とすハげ、ゲート長Ｌｇ
は十分短縮さハ、しかも、ゲート市極の上部の畏さは
十分とれるため、ゲート″直棒抵抗を減少させる等の不
都合は生じない。In order to achieve the above object, the inventor of the present invention has
For example, we came up with the idea of realizing a gate electrode with a shape as shown in FIG. 1, that is, an inverted mesa type. In the figure, l is a substrate, 11 is an insulating film, and 10 is an inverted mesa type gate electrode! be. This structure and gate length Lg
is sufficiently shortened, and the upper part of the gate pole can be sufficiently secured, so there will be no inconvenience such as reducing the gate's straight rod resistance.
上記逆メサ型のゲート電イ會は実現が容易ではないため
、本発明の発明者は第２図に示すように、卑、板】上に
エツチングレートの異なる物質をもって二重Ｎ４１２．
１３を形成し、この二重層に段差を有する開口を形成し
、この開口にゲート電極１０′を形成することとして、
上記の着想を具体化して本発明を完成した。Since the above-mentioned inverted mesa type gate electrode system is not easy to realize, the inventor of the present invention developed a double N412.
13, forming an opening having a step in this double layer, and forming a gate electrode 10' in this opening.
The present invention was completed by embodying the above idea.
史に、−１−、Ｈｌ−ｊの製造工程において、活性層を
保護するためには、活性層を算出させて電榛を形成する
工程は、できる限り後で行なわれることは言うまでもな
い。It goes without saying that in the manufacturing process of -1- and Hl-j, in order to protect the active layer, the step of calculating the active layer and forming the electrodes is carried out as late as possible.
（６） 発明の実施・例
以下図面を参照しつつ、本発明の一実施例に係る半導体
装置の製造方法について説明し、本発明の構成と特有の
効果とを明らかにする。(6) Implementation/Example of the Invention A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings, and the structure and unique effects of the present invention will be clarified.
−例として、半絶縁性と化ガリウム（ＧａＡｓ）基板上
にｎ型ヒ化ガリウム（ｎＧａＡｓ）活性層と、窒化シリ
コン（Ｓｉ３Ｎ４）膜及び二酸化シリコン（Ｓ１０□）
膜よりなる二重絶縁層とを有するＭＥＦ３Ｆ１１ｊＴに
ついて述べる。- As an example, an n-type gallium arsenide (nGaAs) active layer on a semi-insulating gallium oxide (GaAs) substrate, a silicon nitride (Si3N4) film and a silicon dioxide (S10□)
A MEF3F11jT having a double insulating layer made of a film will be described.
第３図参照
厚さ４００μｍ程度の半絶縁性ヒ化ガリウム（ＧａＡｓ
）基板１土に、ｎ型不純物として硫黄（Ｓ）を１０”／
ａｍ”程度含むｎ型ヒ化ガリウム（ｎＧａＡｓ）よりな
る活性層２を公知の方法を使用［７て０．６〔μｍ〕程
度の厚さに形成する。Refer to Figure 3. Semi-insulating gallium arsenide (GaAs) with a thickness of approximately 400 μm.
) Add sulfur (S) as an n-type impurity to substrate 1 soil at 10”/
An active layer 2 made of n-type gallium arsenide (nGaAs) having a thickness of about 0.6 μm is formed using a known method [7].
続いて、基板１の全面に、淳さ０３〔μｍ〕程度の窒化
シリコン（１３１３Ｎ４）膜３と厚さ０．７〔μｍ〕程
度の二酸化シリコン（Ｓｉ、０２）膜４とをそれぞれ化
学気相成長法（ＯＶＤ法）を使用して順次形成する。Subsequently, a silicon nitride (1313N4) film 3 with a thickness of about 0.3 [μm] and a silicon dioxide (Si, 02) film 4 with a thickness of about 0.7 [μm] are deposited on the entire surface of the substrate 1 using a chemical vapor phase. They are formed sequentially using a growth method (OVD method).
しかるのち、上記基板１の全面にフォトレジスト膜５を
形成し、フォトリングラフイー法と四フッ化炭素（ａＦ
４）等を反応性ガスとしてなすりアクティブイオンエツ
チング法とを組み合わせて窒化シリコン（ｓ １ｓ Ｎ
４ ）と二酸化シリコン（Ｓ１Ｏ２）双方のエツチング
を行ないソース・Ｐレイン電極形成予定領域」二から窒
化シリコン（８１３Ｎ４）膜３と二酸化シリコン（Ｓ
ｊ、 Ｏ□）膜４とを除去する。Thereafter, a photoresist film 5 is formed on the entire surface of the substrate 1, and a photoresist film 5 is formed on the entire surface of the substrate 1 using a photophosphorography method and carbon tetrafluoride (aF).
4) etc. as a reactive gas in combination with active ion etching method, silicon nitride (s1sN
4) and silicon dioxide (S1O2), etching the silicon nitride (813N4) film 3 and silicon dioxide (S
j, O□) film 4 is removed.
第４図参照
二酸化シリコン（Ｓ１０□）のみの選択エツチングが可
能な緩衝弗酸溶液（弗酸（）ＴＦ）と弗化アンモニウム
（ＮＨ４１１Ｉ′）との混合液）を使用して二酸化シリ
コン（Ｓ ｊ、 Ｏ□）膜４のサイドエッチングを行な
い図に６をもって示す如き四部を形成する。このとき、
緩衝弗酸溶液に対する窒化シリコン（８１３Ｎ４）と二
酸化シリコン（Ｓｉｎ２）とのエツチングレートの比は
約１ ＋ １００であるから、窒化シリコン（Ｓ１０□
）膜３はほとんどエツチングされない。Refer to Figure 4. Silicon dioxide (S j , O□) Side etching of the film 4 is performed to form four parts as indicated by 6 in the figure. At this time,
Since the etching rate ratio of silicon nitride (813N4) and silicon dioxide (Sin2) to a buffered hydrofluoric acid solution is approximately 1 + 100, silicon nitride (S10□
) Film 3 is hardly etched.
第５図参照
ソース・ １？レイン電ｆｉＬ７．７′を形成する。こ
の工程は上記基板１の全面に、真空蒸着法を使用して金
ゲルマニウム（ＡｕＧｅ ）合金膜／金（Ａｕ）膜より
なる二ｉｉｊ： Ｎを形成し、ソース・ドレイン電極７
．７′を除く領域の二重層７′はリフトオフ工程により
レジストと共に一括除去することによって実行干きる。Figure 5 reference source 1? A rain electric field fiL7.7' is formed. In this step, a 2III:N layer consisting of a gold germanium (AuGe) alloy film/gold (Au) film is formed on the entire surface of the substrate 1 using a vacuum evaporation method, and the source/drain electrodes 7 are formed.
．． The double layer 7' in the area other than the area 7' is removed together with the resist by a lift-off process to dry it.
８６図参照
上言「′工程終了後部−板１の全面に再びフォトレジス
ト膜５′を形成し、上記と同様、フォトリングラフイー
法を使用して、その領域にゲート電極が形成されるステ
ップオーツクー状開ロ形成用のレジストマスクを形成す
る。Refer to Figure 86 above: ``After the end of the process - A step in which a photoresist film 5' is again formed on the entire surface of the plate 1, and a gate electrode is formed in that area using the photophosphorography method in the same manner as above. A resist mask for forming an otsuku-shaped opening is formed.
第７図参照
上献と同様、四フッ化炭素（ＯＦ４）ガスを反応性ガス
としてなすプラズマエツチング法もしくはりアクティブ
イオンエツチング法を使用して窒化シリコン（Ｓｉ３Ｎ
４）膜３のエツチングを行ない、図に８をもって示すス
テノゾオーガー状開口を形成する。このとき、二酸化シ
リコン（Ｓｉｎ２）膜４も多少エツチングされるが構造
−ヒ何ら差しつがえない１、この工程が終了するまで、
活性層２が窒化シリコン（Ｓｉ３Ｎ４）膜３によって安
全に保護されている。Refer to Figure 7. Similar to the above, silicon nitride (Si3N
4) Etching the membrane 3 to form stenozooger-like openings shown at 8 in the figure. At this time, the silicon dioxide (Sin2) film 4 is also etched to some extent, but there is no problem with the structure1.Until this process is completed,
The active layer 2 is safely protected by a silicon nitride (Si3N4) film 3.
第８図参照
上記ステップオーツ々−状開口８に、例えば電子ビーム
蒸着法を使用してアルミニウム（ＡＩりよりなるグー）
醜′Ｖｉ９を形成する。ゲート電極９以外の領域に形
成されたアルミニウム（ＡＩ）膜（図示せず）はリフト
オフ工程によりレジスト５′（第７図）と共に一括除去
し、ＭＰＳ ＦＩＩＣＴの製造工程を完了する。Refer to FIG. 8. The step oat-shaped opening 8 is coated with aluminum (Al made of aluminum) using, for example, an electron beam evaporation method.
Form ugliness'Vi9. The aluminum (AI) film (not shown) formed in the area other than the gate electrode 9 is removed together with the resist 5' (FIG. 7) by a lift-off process, thereby completing the manufacturing process of the MPS FIICT.
以上の工程によれば、ゲート電極抵抗の減少を伴わず、
通常のフォトリングラフイー法の解像限界といわれる１
〔μｍ〕を超えた微細化が可能となり、例えば、本実施
例においてゲート電極形成相フォトレジスト間ロバター
ンすなわち開口８の上辺が１〔μｍ〕であるのに対し、
実際のゲート長すなわち開口８の下辺は０．６〔μｍ〕
に短縮され、集積化に有効に寄与するとともに最大発振
周波数ｆＭＡＸが増大し、雑音指数（ＮＦ 、 Ｎｏ１
ｓｅ Ｆｉｇｕｒｅ ）は０．３（ＬＢ低沖することが
確認された。According to the above process, the gate electrode resistance is not reduced;
1, which is said to be the resolution limit of the normal photophosphorography method.
For example, in this embodiment, the pattern between the photoresists in the gate electrode formation phase, that is, the upper side of the opening 8, is 1 [μm].
The actual gate length, that is, the lower side of the opening 8 is 0.6 [μm]
This effectively contributes to integration, increases the maximum oscillation frequency fMAX, and improves the noise figure (NF).
se Figure) was confirmed to be 0.3 (LB low offshore).
（７）発明の詳細
な説明せるとおり、ＭＥｉＳ ＰＥＴの製造方法におい
て、ゲート電極抵抗の減少を伴うことなくゲート長の短
いゲート電極の製造を可能とし、伝達コンダクタンスが
大きくゲート容量は小さく、最大発振周波数等の特性が
浪好なＭＢＳ ＦＦ１Ｔの製造方法を提供することが〒
きる。(7) As described in detail of the invention, the MEiS PET manufacturing method enables the manufacturing of a gate electrode with a short gate length without reducing the gate electrode resistance, has a large transfer conductance, a small gate capacitance, and has a maximum oscillation. It is our goal to provide a method for manufacturing MBS FF1T with favorable characteristics such as frequency.
Wear.
第１図と第２図とは本発明の発明者の石川を示す図であ
り、ゲート電極の望ましい形状を模式的に表わしたもの
であり、第３図乃至第８図は本発明の一笑施例に係るＭ
ＦｉＳ ＦＥＴの製造方法の主要工程完了後の基板断面
図〒ある。
１・・・基板（半絶縁性ＧａＡｓ ）、２・・・活性層
（ｎＧａＡ８）、３・・・絶縁物膜（窒化シリコン（８
１３Ｎ４）膜）、４・・・絶縁物膜（二酸化シリコン（
ｓ１ｏ２）膜）、５．５′・・・フォトレジスト膜、６
・・・５ｉｎ２膜のサイドエッチにより形成された凹部
、７．７′・・・ソース・ドレイン電極（ＡｕＧｅ膜／
Ａ ｕ膜二重層）、７″川ＡｕＧθ膜／Ａｕ 膜二
重ノー、８・・・ステップオー・々−状開口、９８．、
ゲート電極（ＡＩ膜）、１０．１０’・−・本発明の発
明者の着想である逆メサ型の構造を有するゲート電極、
１１・・・本発明の発明者の着想である逆メサ型の開口
が設けられた絶縁膜、１２．１３・・・本発明の発明者
の着想である逆メサ型の開口が設けられた異神の絶縁膜
よりなる二重層。
１１−
＝３５８−1 and 2 are diagrams showing Ishikawa, the inventor of the present invention, and schematically represent a desirable shape of the gate electrode, and FIGS. 3 to 8 are diagrams showing the preferred embodiment of the present invention. M according to example
There is a cross-sectional view of the substrate after completing the main steps of the FiS FET manufacturing method. 1... Substrate (semi-insulating GaAs), 2... Active layer (nGaA8), 3... Insulator film (silicon nitride (8
13N4) film), 4... Insulator film (silicon dioxide (
s1o2) film), 5.5'... photoresist film, 6
...Concavity formed by side etching of 5in2 film, 7.7'...Source/drain electrode (AuGe film/
(Au film double layer), 7″ AuGθ film/Au film double layer, 8...Step-O-shaped opening, 98.,
Gate electrode (AI film), 10.10' ---Gate electrode having an inverted mesa structure, which is an idea of the inventor of the present invention,
11...An insulating film provided with an inverted mesa-type opening, which is the idea of the inventor of the present invention, 12.13...An insulating film provided with an inverted mesa-type opening, which is an idea of the inventor of the present invention. A double layer made of divine insulating film. 11- =358-
Claims (1)
りなる二重層を形成し、該二重層をゲート形成予定領域
以外から選択的に除去し、前記二重層の上層をなす物質
をエツチングするエツチング剤を使用して前記ゲート形
成予定領域上に残留された二重層の上層の一部を除去し
て前記二重層の下層の上面の一部領域を露出させ、前記
ゲート形成予定領域の一部領域を残して他の領域を覆う
マスクを形成した後、前記二重層の下層をなす物質をエ
ツチングするエツチング剤を使用して前記マスクによっ
て覆われていない領域から前記下層を除去して該領域に
おいて前記活性層を露出させて前記マスクによって覆わ
れていない領域に前記二重層をステップオー・々−する
段差部を形成し、しかる後該段差部にゲート電極を形成
する工程を含むことを特徴とする、半導体装置の製造方
法。A double layer made of two types of insulators with different chemical properties is formed on a semiconductor active layer, the double layer is selectively removed from areas other than the area where the gate is to be formed, and the material forming the upper layer of the double layer is etched. A portion of the upper layer of the double layer remaining on the region where the gate is to be formed is removed using an etching agent to expose a portion of the upper surface of the lower layer of the double layer, and a portion of the region where the gate is to be formed is removed. After forming a mask covering all but one area, the underlying layer is removed from areas not covered by the mask using an etchant that etches the underlying material of the bilayer. The method further comprises the steps of exposing the active layer and forming a stepped portion for stepping over the double layer in a region not covered by the mask, and then forming a gate electrode in the stepped portion. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11315782A JPS594173A (en) | 1982-06-30 | 1982-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11315782A JPS594173A (en) | 1982-06-30 | 1982-06-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS594173A true JPS594173A (en) | 1984-01-10 |
Family
ID=14605000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11315782A Pending JPS594173A (en) | 1982-06-30 | 1982-06-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS594173A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2694657A1 (en) * | 1992-08-06 | 1994-02-11 | Mitsubishi Electric Corp | Semiconductor device esp. FET or HEMT with T=shaped gate - has gate electrode vertical leg height at least equal to half total electrode height |
-
1982
- 1982-06-30 JP JP11315782A patent/JPS594173A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2694657A1 (en) * | 1992-08-06 | 1994-02-11 | Mitsubishi Electric Corp | Semiconductor device esp. FET or HEMT with T=shaped gate - has gate electrode vertical leg height at least equal to half total electrode height |
| US5470767A (en) * | 1992-08-06 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Method of making field effect transistor |
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