JPH04332136A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a semiconductor device having a short gate length with high controllability by using a process of SAINT. CONSTITUTION:In order to form a source region n<+> and a drain region n<+> on a substrate 2, it is ion implanted in a self-alignment manner by using a T-shaped dummy gate. Then, a head of the gate is removed, and an SiNx layer 8 in which the gate is inverted by using an ECR-CVD, is formed. Thereafter, a gate metal 18 is deposited from a direction inclined to a normal of the substrate 2. In this case, gate metal is not deposited on a shade of a part of a predetermined edge of an opening of the layer 8 in which the gate is inverted. Accordingly, if an inclining direction for depositing the metal, etc., is suitably adjusted, a semiconductor device having a short gate length can be formed with high controllability by a step similar to SAINT.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing semiconductor devices such as field effect transistors (FETs).

0002

2. Description of the Related Art FETs, particularly FETs using GaAs, generally employ a structure in which source and drain regions, which are heavily doped impurity regions for reducing source resistance, are formed in self-alignment with a gate electrode. As a method for realizing such a structure, for example, SAI is used to form a high concentration impurity region by using a T-type dummy gate.
NT (Self-aligned implant)
ion for n + -layer Techno
There is a process technology called
EEE TRANSACTIONS ON ELECT
RON DEVICES, VOL. ED-29.
No. 11 NOV 1982).

0003

[Problem to be Solved by the Invention] However, in the above process technology, if the gate length is shortened to, for example, 0.5 μm or less while the undercut amount of the T-shaped dummy gate is kept large, the T-shaped dummy gate will collapse. Problems such as these have occurred, making it extremely difficult to set process conditions, and furthermore, making precise control of the gate length difficult.

[0004] Therefore, the present invention aims to provide an FET with a short gate length.
It is an object of the present invention to provide a manufacturing method that can form semiconductor devices such as SAINT with good controllability using the same process as SAINT.

[0005]

[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes (a) using a T-shaped dummy gate to form a source region and a drain region on a substrate; (b) forming an insulating film that is an inversion of the T-type dummy gate; and (c) depositing gate metal from a direction tilted to the normal direction of the substrate. Equipped with

[0006]

According to the method for manufacturing a semiconductor device described above, the gate metal is deposited in a direction oblique to the normal direction of the substrate. Therefore, gate metal is not deposited in the shadow of the predetermined edge of the opening in the insulating film that is the inversion of the T-type dummy gate. Therefore, by appropriately adjusting the inclination direction and angle at which the gate metal is deposited, or by appropriately adjusting the thickness of the insulating film, a semiconductor device with a short gate length can be formed with good controllability. In addition, if the tilt direction when depositing the gate metal is on the drain region side, the gate region and the drain region are separated by the region in the shadow of the insulating film where the gate metal is not deposited, improving the gate-drain breakdown voltage. You can also do that.

[0007] Further, in the above method for manufacturing a semiconductor device, ion implantation is performed using the head of the T-type dummy gate as a mask, and an insulating film is formed using the portion from which the head of the T-type dummy gate is removed as a mask. Good too.

[0008] Furthermore, if the step of forming an insulating film in the above method for manufacturing a semiconductor device includes a step of stacking a SiN layer using electron cyclotron resonance vapor phase epitaxy, it is possible to use a semiconductor device with a short gate length. The device can be manufactured more precisely.

[0009]

Embodiment An embodiment of a method for manufacturing a MESFET, which is a semiconductor device, will be described below with reference to FIGS. 1 to 3.

FIG. 1(a) is a cross-sectional view showing the state after the T-type dummy gate 10 is formed. First, a GaAs (100) semiconductor substrate 2 is prepared for forming the T-type dummy gate 10. In this case, a crystal-grown GaAs semiconductor layer may be prepared on a suitable substrate. Next, a multilayer resist consisting of a lower resist layer 4, an intermediate SiO2 layer 8, and an upper resist layer is sequentially laminated, and the multilayer resist is removed according to a normal SAINT process to form a T-shaped dummy gate 10. Thereafter, an n+ layer which will become the source and drain regions is formed by Si+ ion implantation.

FIG. 1(b) is a diagram showing the next process. The head of the T-shaped dummy gate 10 shown in FIG. 1(a) is removed using a hydrofluoric acid-based etchant.

FIG. 1(c) is a diagram showing the next step. Electron cyclotron resonance vapor phase epitaxy (ECR-C)
A silicon nitride (SiNx) layer 8 is uniformly deposited using VD).

FIG. 2(a) is a diagram showing the next step. Lower resist layer 4 which is the main body of the T-shaped dummy gate
and the SiNx layer 8 deposited on top thereof are removed by a lift-off method, and the lower resist layer 4 is replaced with an inverted SiNx layer 8.
Obtain the inverted gate pattern of the x layer layer 8.

FIG. 2(b) is a diagram showing the next step. Patterning for gate metal formation is performed using photoresist 14.

FIG. 2(c) is a diagram showing the next step. Ti/P to become gate metal by oblique evaporation
A t/Au layer 18 is deposited. In this case, the semiconductor substrate 2 is arranged so that its normal line is inclined with respect to the evaporation source, and the direction of the inclination is the direction of the gate length and the direction on the drain side.

FIG. 3(a) is a diagram showing the next step. Unnecessary metal is removed by a lift-off method, leaving only the gate metal 18a.

FIG. 3(b) is a diagram showing the next step. An AuGe/Ni layer 12 to be an ohmic metal is formed using a lift-off method.

According to the embodiments described above, a MESFET with a short gate length (0.5 μm or less) can be manufactured with good controllability using SAINT. therefore,
If this manufacturing method is applied to IC manufacturing etc., it will be effective in increasing the yield and achieving a short gate length (0.5 μm or less). In addition, a region where the gate metal 18a is not deposited is provided between the drain region and the gate metal 18a due to the shadow of the inverted gate pattern of the SiNx layer 8.
Drain breakdown voltage can also be improved. Improving gate-drain breakdown voltage is effective when applied to low-noise or power FETs.

[0019]

As described above, according to the method of manufacturing a semiconductor device of the present invention, since gate metal is deposited in a direction inclined to the normal line of the substrate, a semiconductor device with a short gate length can be manufactured. It can be formed with good controllability by the same process as SAINT. Further, since the gate region and the drain region can be separated by the shadow of the insulating film, the gate-drain breakdown voltage of the semiconductor device can also be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first step of a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2 is a diagram showing a middle step of the method for manufacturing a semiconductor device according to the embodiment.

FIG. 3 is a diagram showing the latter step of the method for manufacturing a semiconductor device according to the embodiment.

[Explanation of symbols]

2...Substrate 10...T-type dummy gate 18a...Gate metal n+...source region and drain region

Claims (3)

[Claims] 1. A step of self-aligned ion implantation using a T-shaped dummy gate to form a source region and a drain region on a substrate, and a step of forming an insulating film with the T-shaped dummy gate inverted. A method of manufacturing a semiconductor device, comprising: depositing a gate metal from a direction tilted with respect to the normal direction of the substrate. 2. The ion implantation process is performed using the top of the T-shaped dummy gate as a mask, and the insulating film formation process is performed using a portion of the T-shaped dummy gate from which the top is removed as a mask. 2. The method of manufacturing a semiconductor device according to claim 1. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the insulating film includes the step of stacking a SiN layer using electron cyclotron resonance vapor phase epitaxy.