JPS6058679A - Formation of gate electrode of schottky barrier gate type fet - Google Patents
Formation of gate electrode of schottky barrier gate type fetInfo
- Publication number
- JPS6058679A JPS6058679A JP16773283A JP16773283A JPS6058679A JP S6058679 A JPS6058679 A JP S6058679A JP 16773283 A JP16773283 A JP 16773283A JP 16773283 A JP16773283 A JP 16773283A JP S6058679 A JPS6058679 A JP S6058679A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gate electrode
- schottky barrier
- forming
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004888 barrier function Effects 0.000 title claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 230000005669 field effect Effects 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 238000007740 vapor deposition Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229910017401 Au—Ge Inorganic materials 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 abstract 1
- 239000000956 alloy Substances 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体の製造方法特にショットキ障壁ゲート型
電界効果トランジスタのゲート電極の形成方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor, and particularly to a method of forming a gate electrode of a Schottky barrier gate field effect transistor.
従来例の構成とその問題点
ショットキ障壁ゲート型電界効果トランジスタ（以下Ｆ
ＥＴと略す）特にＧ ａ Ａ ｓ Ｆ Ｅ Ｔは、高速
、マイクロ波領域の半導体デバイスとして有用である。Conventional structure and its problems Schottky barrier gate field effect transistor (F
In particular, GaAs FET (abbreviated as ET) is useful as a semiconductor device in the high-speed microwave region.
このためＧａＡｓＦＥＴ１構成素子として用いた集積回
路の開発が進められている。Ｇ ａ Ａ ｓ Ｆ Ｅ
Ｔにおいてはマイクロ波領域で、高速動作させるために
はゲート電極の長さとしてサブミクロン長が要求される
。For this reason, the development of integrated circuits used as components of the GaAsFET1 is progressing. G a As F E
T is in the microwave region, and in order to operate at high speed, a submicron length is required as the gate electrode length.
第１図は従来のＧ ａ Ａ ｓ Ｆ Ｅ Ｔの構造断面
図である。FIG. 1 is a structural sectional view of a conventional GaAs FET.
１は半絶縁性Ｇ ａ Ａ ｓ基板、２は能動領域、３は
オーミック領域、４はソース電極、６はドレイン電極、
６はゲート電極である。1 is a semi-insulating GaAs substrate, 2 is an active region, 3 is an ohmic region, 4 is a source electrode, 6 is a drain electrode,
6 is a gate electrode.
このような構造のＧａＡｓＦＥＴにおいて、一般にゲー
ト電極はフォトレジスト法により形成されている。この
ためゲート長はフォトレジスト加工精度に依存する。よ
って上述の様な要求は十分達せられているとは言い難い
。In a GaAsFET having such a structure, the gate electrode is generally formed by a photoresist method. Therefore, the gate length depends on the photoresist processing accuracy. Therefore, it cannot be said that the above-mentioned requirements have been fully met.
発明の目的
本発明はＦＥＴのゲート電極を形成する際に、このよう
な従来の欠点を除去しフォトレジスト加工精度（一般的
には約２μｍ）に依存せず、さらに微細なサブミクロン
長のゲート長を得ることによシ高周波領域で高速動作す
るＦＥＴを提供するものである。Purpose of the Invention The present invention eliminates such conventional drawbacks when forming gate electrodes of FETs, does not depend on photoresist processing precision (generally about 2 μm), and forms gate electrodes with even finer submicron length. By obtaining a long length, an FET that operates at high speed in a high frequency region is provided.
発明の構成
本発明の７ヨツトキ障壁ゲート型電界効果トランジスタ
のゲート電極形成方法は、半導体基板に能動領域および
オーミック領域全形成する工程と、全面に第１の絶縁膜
を形成する工程と、ゲート電極を形成すべき部分の第１
の絶縁膜に開口部を形成する工程と、全面に第２絶縁膜
を形成し、前記開口部の側面以外の前記第２の絶縁膜を
除去する工程と、前記半導体とショットキ障壁を形成す
る金属を前記開口部のみに形成しゲート電極を形成する
工程を含むことを特徴としている。Structure of the Invention The method for forming a gate electrode of a 7-way barrier gate field effect transistor of the present invention includes a step of forming all active regions and ohmic regions on a semiconductor substrate, a step of forming a first insulating film on the entire surface, and a step of forming a gate electrode on the entire surface. The first of the parts to be formed
forming an opening in the insulating film; forming a second insulating film over the entire surface and removing the second insulating film other than the side surfaces of the opening; and metal forming a Schottky barrier with the semiconductor. The method is characterized in that it includes a step of forming a gate electrode only in the opening.
実施例の説明
本発明の実施例を主にゲート形成を中心に図面を用いて
工程順に説明する。第２図は本発明にょｐＧａＡｓＦＥ
Ｔにおいて短ゲート長を得るためのゲート電極形成方法
の各工程における素子断面全模式的に示したものである
。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be explained in order of steps with reference to the drawings, mainly focusing on gate formation. Figure 2 shows the pGaAsFE according to the present invention.
12 schematically shows the entire device cross section at each step of the gate electrode forming method for obtaining a short gate length at T.
まず第２図ａに示すように半絶縁性あるいは絶縁性Ｇａ
Ａｓ基板１にイオン注入法により能動領域２およびオー
ミック領域３を形成する。さらにオーミック領域３の上
部にオーミンクメタルとなる材料例えば金・ゲルマニウ
ム合金膜を蒸着しソース電極４およびドレイン電極５を
形成し、第２図すのような断面構造を得る。次に第２図
Ｃに示すようにゲートとなる部分にフォトレジスト７を
用いて絶縁膜８例えばＳ ｉＯ２に開口部９をあける。First, as shown in Figure 2a, semi-insulating or insulating Ga
An active region 2 and an ohmic region 3 are formed on an As substrate 1 by ion implantation. Further, a material to be an ohmic metal, such as a gold-germanium alloy film, is deposited on the upper part of the ohmic region 3 to form a source electrode 4 and a drain electrode 5, thereby obtaining a cross-sectional structure as shown in FIG. Next, as shown in FIG. 2C, an opening 9 is formed in the insulating film 8, for example SiO2, using a photoresist 7 in a portion that will become the gate.
次に第２図ｄに示すように蒸着によシ絶縁膜１゜を全面
に形成する。この絶縁膜１０例えばＳ ｉＯ２を異方性
ドライエツチング法により除去する。この際、Ｇ ａ
Ａ ｇ基板１に垂直な方向と水平な方向の膜厚の違いか
ら開口部９の側面の絶縁膜は除去されずに残り第２図ｅ
のような断面構造となり、フォトレジストによシ形成さ
れた開口部よシも狭い開口１１が形成される。Next, as shown in FIG. 2d, an insulating film 1° is formed over the entire surface by vapor deposition. This insulating film 10, for example SiO2, is removed by anisotropic dry etching. At this time, Ga
A gDue to the difference in film thickness between the vertical and horizontal directions of the substrate 1, the insulating film on the side surface of the opening 9 is not removed and remains as shown in Figure 2e.
The cross-sectional structure is as follows, and an opening 11 is formed which is narrower than the opening formed by the photoresist.
次に第２図ｆに示すよう［ＧａＡｓ１Ｃ対してショット
キ障壁を形成するような金属１２例えば白金やアルミニ
ウムを全面蒸着しリフトオフ法によシ開口１１のみの金
属を残しゲート電極６を形成する。具体的な数値例とし
て開口部９の幅が２μｍのとき絶縁膜１０’１５０００
人つければ開口部１１０幅は１μｍとなる。このように
してｑに示すゲート長のＧａＡｓＦＥＴ１製造すること
ができる。Next, as shown in FIG. 2F, a metal 12, such as platinum or aluminum, which forms a Schottky barrier with respect to the GaAs 1C is deposited on the entire surface, and a lift-off method is used to form the gate electrode 6, leaving only the metal in the opening 11. As a specific numerical example, when the width of the opening 9 is 2 μm, the insulating film 10'15000
If a person is attached, the width of the opening 110 will be 1 μm. In this way, the GaAsFET 1 having the gate length shown in q can be manufactured.
なお、本実施例ではＧ ａ Ａ ｇについて説明したが
他の半導体のＦＥＴにも応用でき、一基板として半絶縁
性基板を用いたが他の絶縁性ｎ型あるいはｐ型基板でも
よい。また能動領域およびオーミック領域をイオン注入
で形成したがエピタキシャル法によって形成してもよい
。またソース電極およびドレイン電極全ゲート電極よシ
も先に形成したが順序は逆でも可能である。Although the present embodiment has been described with respect to G a A g, it can also be applied to FETs of other semiconductors, and although a semi-insulating substrate is used as one substrate, other insulating n-type or p-type substrates may be used. Further, although the active region and the ohmic region are formed by ion implantation, they may be formed by an epitaxial method. Furthermore, although the source electrode, drain electrode, and all the gate electrodes are formed first, the order may be reversed.
発明の効果
このように本発明はフォトレジスト加工精度よシも微細
なゲート領域を形成することができ、このようにして形
成された短ゲート長のショットキ障壁ゲート型電界効果
トランジスタでは高周波領域において高速動作が可能と
なる。Effects of the Invention As described above, the present invention can form a gate region that is even finer than the photoresist processing accuracy, and the Schottky barrier gate field effect transistor with a short gate length formed in this manner can achieve high speed in a high frequency region. operation becomes possible.
第１図は従来のＦＥＴの断面図、第２図ａ −ｑは本発
明の一実施例によるＧ ａ Ａ ｇ Ｆ Ｅ Ｔの製造
工程順の素子断面図である。
１・・・・・・半絶縁性Ｇ ａ Ａ ｓ基板、２・・・
・・・能動領域、３・・・・・・オーミック領域、４・
・・・・・ソース電極、５・・・・・・ドレイン電極、
６・・・・・・ゲート電極、７・・・・・・フォトレジ
スト、８・・・・・・絶縁膜、９・・・・・・開口部、
１０・・・・・・絶縁膜、１１・・・・・・開口部、１
２・・・・・・金属膜。FIG. 1 is a cross-sectional view of a conventional FET, and FIGS. 2A-2Q are device cross-sectional views in the order of manufacturing steps of a GaAg FET according to an embodiment of the present invention. 1...Semi-insulating GaAs substrate, 2...
...Active region, 3...Ohmic region, 4.
...Source electrode, 5...Drain electrode,
6...Gate electrode, 7...Photoresist, 8...Insulating film, 9...Opening part,
10... Insulating film, 11... Opening, 1
2...Metal film.
Claims (1)
工程と、全面に第１の絶縁膜を形成しゲート電極を形成
すべき部分の前記第１の絶縁膜にフォトレジス）（ｒ用
いて開口部を形成する工程と、前記フォトレジストを含
む半導体基板全面に第２の絶縁膜を形成し、前記開口部
の側面以外の前記第２の絶縁膜を除去する工程と、前記
半導体とショットキ障壁を形成する金属を前記開口部の
みに形成しゲート電極を形成する工程とを含むことを特
徴とするショットキ障壁ゲート型電界効果トランジスタ
のゲート電極形成方法。A step of forming an active region and an ohmic region on a semiconductor substrate, forming a first insulating film over the entire surface, and forming an opening using photoresist (r) on the first insulating film in a portion where a gate electrode is to be formed. a step of forming a second insulating film over the entire surface of the semiconductor substrate including the photoresist, and removing the second insulating film other than the side surfaces of the opening, a metal forming a Schottky barrier with the semiconductor; A method for forming a gate electrode of a Schottky barrier gate type field effect transistor, comprising the step of forming a gate electrode only in the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16773283A JPS6058679A (en) | 1983-09-12 | 1983-09-12 | Formation of gate electrode of schottky barrier gate type fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16773283A JPS6058679A (en) | 1983-09-12 | 1983-09-12 | Formation of gate electrode of schottky barrier gate type fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6058679A true JPS6058679A (en) | 1985-04-04 |
Family
ID=15855119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16773283A Pending JPS6058679A (en) | 1983-09-12 | 1983-09-12 | Formation of gate electrode of schottky barrier gate type fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6058679A (en) |
-
1983
- 1983-09-12 JP JP16773283A patent/JPS6058679A/en active Pending
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