JP2822739B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a low noise field effect transistor formed on a compound semiconductor substrate and a semiconductor device centered on the transistor.

[0002]

2. Description of the Related Art Conventionally, as a device pattern of a compound semiconductor low noise field effect transistor, a gate electrode 1 having a linear gate finger 1 on a channel as shown in FIG. 2, a source electrode 3 surrounding the gate electrode 2, a drain electrode 6 on the opposite side of the source electrode 3 with the gate finger 1 interposed therebetween, and a pattern shown in FIG. Or two gate fingers 1 drawn out from the gate electrode 2 as shown in FIG. 10, and a drain electrode 6 provided in a region sandwiched between the two gate fingers 1, The pattern has two source electrodes 3 separated from the back side of the substrate by via-hole electrodes outside the two gate fingers 1. In the case of the pattern shown in FIG. 10, after the surface of the FET is formed, the thickness of the wafer is reduced to about 30 μm to 70 μm, the surface is aligned with the source on the double-side alignment exposure apparatus, and the via hole is dry-etched on the back side of the source. It is formed by wet etching, and an independent source is joined by sputtering metal on the entire back surface. Therefore, the manufacturing process for forming this pattern is:
There is a disadvantage that the patterns are complicated as compared with the patterns shown in FIGS. Therefore, the element pattern used in the low-noise field effect transistor is shown in FIG.
11 or a pattern as shown in FIG.
The pattern shown in FIG.

In general, the minimum noise figure (Fmin) representing the noise characteristic of a low-noise field-effect transistor is expressed by the following Fuk:
ui is represented by the following equation.

Fmin = 1 + 2 (ωCgs / gm) [Kg {Kr + gm (Rs + Rg)}] ^1/2 ft = gm / 2πCgs where Kg and Kr are noise coefficients obtained by noise measurement. Taking the above into consideration, the cut-off frequency (f
It is necessary to increase t), reduce Rs, and reduce Rg.

[0005] In the pattern shown in FIG. 9 and the pattern shown in FIG.
The gate length is shortened for the purpose of increasing the mutual conductance (gm) and decreasing the gate-source capacitance (Cgs) in order to increase. At present, a gate length of 0.1 μm to 0.3 μm can be formed using an electron beam lithography apparatus. At this time, since the gate resistance (Rg) increases as the gate length is shortened, a T-shaped gate is being used.

[0006] In the low-noise amplifying device for microwaves in the C band to the Ku band, the pattern shown in FIG.
(Referred to as a pattern) is widely used.

In recent years, a low-noise field-effect transistor has been disclosed that forms a pattern using aerial wiring for a π-type pattern. At the 1990 IEICE National Convention SC-2-2, Onda et al. Had a source electrode and a source electrode path completely surrounding a gate electrode and a gate finger as shown in FIG. A source finger disposed alternately in a region sandwiched between the fingers, a drain finger surrounded by the gate finger and the source finger, and a source electrode path extending in a direction opposite to the gate electrode from each drain finger; It has been reported that a pattern having an aerial wiring coupled to one drain electrode (hereinafter referred to as a completely-gate-type drain air bridge pattern) obtained better noise characteristics than a π-type pattern. A related patent is Japanese Patent Application No. 2-213891.

[0008]

In the above-mentioned conventional and widely used .pi.-type pattern, the F with a constant gate width is used.
When making an ET, the gate resistance (R
There is a limit in reducing g).

Further, in the drain air bridge pattern completely surrounding the gate, the optimum values of the unit gate finger length and the number of gate fingers are not shown.

Further, in the assembling process, when bonding is performed from a bonding pad of a chip having a π type pattern and a drain air bridge pattern with a completely gate to a chip carrier or package pattern using a gold wire,
The bonding wire (gold wire) from the gate pad must cross the source electrode without fail, so that short-circuit between the bonding wire and the source electrode is likely to occur,
There is a disadvantage that the yield of the assembly process is reduced.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
At least two or more channels formed on a compound semiconductor substrate, a gate electrode connecting the gate finger and the gate finger from one side on the channel, and a portion opposing the drain electrode sandwiching the gate finger and the gate electrode A source electrode in the form of a horseshoe and a source electrode path connecting the source electrode, a source finger disposed alternately in a region between the source electrode path and the gate finger, and the gate A drain finger sandwiched between the finger and the source finger, and an aerial wire coupled to one drain electrode from each of the drain fingers across the source electrode path in a direction opposite to the gate electrode electrode.

[0012] Preferably, the semiconductor device has eight gate fingers.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments will be described below in detail with reference to the drawings.
FIGS. 1 to 4 show element patterns of the semiconductor device of the present invention, which are referred to as an ABD8 pattern, an ABD10 pattern, an ABD6 pattern, and an ABD4 pattern, respectively. As shown in FIG. 1, the pattern of the ABD 8 is a pattern in which eight gate fingers drawn out from the gate electrode 2 are arranged in parallel with each other, and the horseshoe-shaped source electrode 3 and the electrode path 3 ′ are arranged. Every other source finger 4 drawn from the path 3 ′ is arranged in the region sandwiched by the gate fingers 1, an aerial wiring section 5 is provided from the drain electrode 6, and the source finger 4 is sandwiched between the gate fingers 1 across the source electrode path 3 ′. This is a pattern in which a drain finger 7 is arranged in a region other than the region where the source finger 4 is arranged.
(Announced at the 1991 IEICE Autumn Meeting C-347) The ABD10, ABD6 and ABD4 patterns have 10, 6, and 4 gate fingers, respectively, and the ABD8 pattern and the gate finger number are different. Only the other patterns are the same, and the description is omitted.

ABD8, ABD10, AB according to the present invention
Each pattern of D6 and ABD4 and a conventional π-type pattern were formed on the same wafer. Here, the total gate width was the same 200 μm in all the patterns.

The wafer used was an undoped GaAs layer 34 (buffer layer) grown by MBE on a semi-insulating GaAs substrate 35 as shown in FIG.
aAs layer 33 (current channel layer), n ⁺ -AlGaAs
It has a laminated structure of a layer 32 (electron supply layer) and an n ⁺ -GaAs layer 31 (contact layer). n ⁺ -AlGa
Doped structure As layer it becomes steps doped structure comprising a low density region and a high density region, n ⁺ -GaA
The low concentration region in contact with the s layer 31 is 1 × 10 ¹⁸ cm ⁻³ , and the high concentration region in contact with the undoped InGaAs layer 33 is 4 × 1
0 ¹⁸ cm ^-3 . The doping concentration of the n ⁺ -GaAs layer 31 is 3 × 10 ¹⁸ cm ⁻³ . The MBE wafer is subjected to mesa etching using an etchant obtained by mixing sulfuric acid, a hydrogen peroxide solution, and water to perform element isolation. Subsequently, an ohmic electrode is formed by vapor deposition of AuGe / Ni / Au followed by a high-temperature heat treatment alloy at about 450 degrees. Next, a gate pattern is formed with an electron beam resist, and etching is performed until a desired ohmic current is obtained while measuring the inter-ohmic current using the etchant to form a recess. After the recess is formed, a gate electrode is formed by a gate metal deposition lift-off method. Al / Ti was used for the gate metal. In order to reduce Cgs by minimizing the gate length, a gate length of 0.2 μm was formed by an electron beam exposure apparatus.

The subsequent air bridge forming step will be described with reference to FIGS. After the formation of the gate electrode, a passivation film 43 is formed (part (b) of FIG. 7), contact holes are formed in the drain electrode 41 and the drain finger 42 (part (c) of FIG. 7), and the drain electrode is formed. 4
A pattern is formed using a negative resist 44 or photosensitive polyimide to form an aerial wiring from 1 to the drain finger 42 (part (d) of FIG. 7). Thereafter, a metal film 45 such as Ti / Pt / Au is formed on the entire surface.
(Part (a) of FIG. 8), an Au plating 46 is applied to each electrode and the portion of the aerial wiring (part (b) of FIG. 8), and unnecessary sputtering is performed using the Au plating 46 as a mask. Is removed by ion milling (part (c) of FIG. 8). Thereafter, the negative resist 44 or the photosensitive polyimide under the aerial wiring is removed by using O ₂ asher treatment or the like to manufacture an FET device (FIG. 8D).

Although no pattern dependence was observed in the DC characteristics of each device pattern sample manufactured by this method, the noise characteristics at 12 GHz of each sample were evaluated. Depended on the number of gate fingers. Here, the conventional π-type pattern is plotted in the figure on the assumption that it is equivalent to the ABD4 pattern having four gate fingers. In terms of noise figure, the ABD6 pattern, the ABD8 pattern and the ABD10 pattern are superior to the conventional π-type pattern, and the AB with eight gate fingers is used.
Take the minimum value in the pattern of D8.

In general, the gate resistance can be expressed by the following equation.

[0019] ^{Rg = ρg · z 2/3} · Sg · Z where Rg is the gate resistance, Rog the gate metal resistivity,
z is the unit gate finger length, Sg is the gate cross-sectional area, Z
Indicates the total gate width.

In the above results, the π-type pattern and AB
DBD pattern, ABD6 pattern, ABD
The Rg of the pattern No. 8 and the pattern of the ABD 10 are 0.44 times, 0.25 times and 0.16 times, respectively. From the Fukui equation, the noise figure should be minimized in the ABD10 pattern with ten gate fingers. However, the pattern of the ABD 10 is not minimized because the area of the gate electrode 2 increases as the number of gate fingers increases, and the capacitance between the gate electrode and the source electrode increases.
This is because the effect of an increase in the capacitance between the source electrode and the drain electrode due to an increase in the number of lines increases.

In the device pattern of the present invention,
When bonding from a bonding pad of an FET chip to a chip carrier or a package pattern in an assembling process, a bonding wire (gold wire) can be bonded from a gate pad without a source electrode crossing over. as a result,
Approximately 10% yield in the assembly process compared to the conventional π-type pattern and the drain air bridge pattern completely surrounding the gate
Improved.

[0022]

As described above, in the element pattern according to the present invention in which the number of gate fingers is 6 to 10, the gate resistance (Rg) is 0.4 times that of the conventional π-type pattern.
There is an effect that the noise characteristic is greatly improved by a factor of about 4 to 0.16.

It has been found that an element pattern having eight gate fingers exhibits the best noise characteristics.

In the assembling process, when bonding is performed from the bonding pad of the FET chip to the chip carrier or package pattern, the bonding wire (gold wire) from the gate pad should be bonded without straddling the source electrode. And the yield of the assembly result can be improved by about 10% as compared with the π-type pattern and the drain air bridge pattern completely surrounding the gate.

[Brief description of the drawings]

FIG. 1 is a diagram showing an element pattern of the present invention.

FIG. 2 is a view showing an element pattern of the present invention.

FIG. 3 is a view showing an element pattern of the present invention.

FIG. 4 is a view showing an element pattern of the present invention.

FIG. 5 is a diagram showing noise characteristics at 12 GHz of each element pattern.

FIG. 6 is a cross-sectional view showing a structure of an epiwafer used for manufacturing an element pattern of the present invention.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing an element pattern according to the present invention.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing an element pattern according to the present invention.

FIG. 9 is a diagram showing an element pattern conventionally used.

FIG. 10 is a diagram showing an element pattern which is conventionally used and uses via holes.

FIG. 11 is a view showing an element pattern conventionally used.

FIG. 12: IEICE Autumn National Convention S
It is a figure which shows the element pattern proposed by Onda et al. In C-2-2.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Gate finger 2 Gate electrode 3 Source electrode 3 'Gate electrode path 4 Source finger 5 Aerial wiring (air bridge) part 6 Drain electrode 7 Drain finger 31 n ⁺ -GaAs layer 32 n ⁺ -AlGaAs layer 33 Undoped InGaAs layer 34 Undoped GaAs Layer 35 Semi-insulating GaAs substrate 40 Source electrode path 41 Drain electrode 42 Drain finger 43 Passivation film 44 Negative resist 45 Metal film 46 Gold plating 47 Aerial wiring section

Claims (2)

(57) [Claims] 1. A plurality of channels formed in a semiconductor substrate
And corresponding to the plurality of channels and extending in a first direction.
A plurality of gate fingers formed and the plurality of gates
A gate electrode connected to one end of the finger;
The first finger opposing one of the long sides of the gate finger.
A plurality of first fingers extending in the direction of
A first electrode connected to one end of the plurality of first fingers.
Pole and the other of the plurality of gate fingers in the long side direction.
A plurality of second fins facing each other and formed to extend in the first direction.
A finger and one end of the plurality of second fingers
And extending in a second direction orthogonal to the first direction.
Electrode path connected to one end of the electrode path and the second
A second electrode extending in one direction and the electrode path;
A third terminal connected to the other end of the third terminal and extending in the first direction.
And the gate electrode is connected to the second and third electrodes.
And formed between the electrodes of
The third electrode is connected only by the electrode path
A semiconductor device characterized by the above-mentioned . 2. A plurality of channels formed in a semiconductor substrate.
And corresponding to the plurality of channels and extending in a first direction.
A plurality of gate fingers formed and the plurality of gates
A gate electrode connected to one end of the finger;
The first finger opposing one of the long sides of the gate finger.
A plurality of first fingers extending in the direction of
A first electrode connected to one end of the plurality of first fingers.
Pole and the other of the plurality of gate fingers in the long side direction.
A plurality of second fins facing each other and formed to extend in the first direction.
A finger and one end of the plurality of second fingers
And extending in a second direction orthogonal to the first direction.
Electrode path connected to one end of the electrode path and the second
A second electrode extending in one direction and the electrode path;
A third terminal connected to the other end of the third terminal and extending in the first direction.
And the second electrode and the third electrode
The gate electrode and the bonding electrode provided outside the first direction;
And a gate pad connected by a wiring wire.
The gate electrode is sandwiched between the second and third electrodes
Together formed Te, said from the gate electrode gate Topa
The second and third electrodes are formed before the pad.
A semiconductor device, which is not provided.