JPS5860575A - Transistor - Google Patents

Abstract

PURPOSE:To obtain the FET chips for high output, the input impedance of which will decline very little and the loss due to gate width is very small, by a method wherein a gate leadout electrode and a source earth electrode are formed into microstrip line structure. CONSTITUTION:A source leadout electrode 5 is formed on the greater part of the lead-out side for use as an earth electrode, and, at the same time, an insulating layer 16 is formed on the earth electrode and a gate terminal electrode 15. A contact window 17 is formed at a part of the insulating layer 16, and in addition, a strip line electrode 18 is thickly formed by performing plating and the like. A microstrip line transmission path, having a dielectric insulating layer 16 to be placed between two electrodes, is formed using said electrode 18 and the earth electrode 5. The strip line electrode 18 is electrically connected to a gate electrode 1 through the contact window 17, and other end of the electrode 18 is connected to a gate bonding electrode 19.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor, particularly a gallium arsenide low-effect transistor for high output power in the microwave band.

As the output of field-effect transistors (hereinafter referred to as FETs) increases, the gate width increases, but as the gate electrode width increases, the resistance of the metal itself and the gate-source gap increase. Loss of the input signal due to conductance causes a reduction in power gain. Therefore, in the design of -polar patterns,
It is preferable to keep the gate length short enough to ignore the loss, and it is necessary to increase the number of gate extraction polarizations per single contact length of the gate width. On the other hand, in order to reduce the cost, the chip pattern has a structure in which the density is increased, and the drain/nose poles are drawn out in the opposite direction. For this reason, an electrode drawn out according to the source decay rule, for example, gate 4. ′,
! l! , and the north electrode, a static bending violet is formed between the gel and the source in a constant manner. F
Since the intrinsic impedance of the chip E 'i' -ff111 (between gate and source) is capacitive, if one capacitor is added here, the input impedance becomes capacitive and at the same time has a resistive component. will also become smaller. This decrease in input impedance increases the matching loss with external transmission lines, complicates the internal matching circuit formed near the chip inside the device container, and further increases the operational quality.
It is undesirable to narrow the frequency bandwidth in order to increase the frequency, which is undesirable from the viewpoint of high-frequency power characteristics.

An object of the present invention is to provide a transistor that can be easily matched with the outside without causing such a decrease in impedance, and has a gate lead electrode and a source common electrode in a microstrip line structure.

As a result, lumped capacitance generated between the gate and source can be eliminated, and each gate width can be made small and well-balanced. Therefore, the input impedance is loud and approaches resistive impedance, the loss is reduced, and the balance within the chip is improved, so that an FET chip with a wide band and high power gain can be realized. Further, by input matching the pattern of the microstrip line section, it becomes possible to simplify or omit the internal matching circuit, resulting in a structure convenient for increasing high frequency and high output.

In order to better understand the present invention, the present invention will be explained in detail below using the drawings. FIG. 1 shows the electrode structure of a conventional high-output gallium arsenide FET, in which source electrodes 2 and drain electrodes 3 are alternately arranged on both sides of a gate electrode 1. Each of the electrodes is connected to a gate lead-out electrode 4, a source lead-out electrode 5, and a drain lead-out electrode 6, respectively. Broken M7
An active layer of gallium arsenide is formed in the inner layer, and the gate electrode is bonded to the gallium arsenide surface with a barrier barrier.
The source and drain 11 poles are connected to the respective ohmic regions 8,
9 is formed in resistive contact with the gallium arsenide surface.

In the above configuration, the gate length must normally be designed to be about 0.5 μm to 2 μm in order to operate at a cut-off frequency. Therefore, the loss due to the attenuation of the input signal due to the specific resistance of the gate electrode and the inductance between the gate and source cannot be ignored, and it becomes necessary to keep the gate electrode width, that is, the length of the gate electrode 101 short. The above-mentioned loss in the X band is caused by a gate length of 0.5μ, for example.
When m1 gate electrode width is 100 am, Q is 7 dB,
In the case of a width of 200 μm, the loss is approximately 2.2 aB, and this loss also increases as the frequency becomes higher. Therefore 0.5μm
In order to keep the loss at 0.5 dB or less with a gate length of , it is necessary to design the gate electrode width to 80 μm or less. Such a design restriction on the gate electrode width means that the length of one gate electrode 1 in FIG. 1 is shortened and the number of leads is increased by that amount. However, the gate electrode 1 and the gate extraction electrode 4 are connected via the gate focusing electrode IO, and in order to focus the gate electrode 1, it is necessary to cross the source electrode 2. An overlapping portion 11 is formed with an insulating film interposed therebetween. Therefore, the above-mentioned increase in the number of drawers appears as an increase in the overlapping portion 11. The so-called intrinsic input impedance between the gate and source of the FET chip is shown by the dashed line 12 in FIG.
Since it is capacitive as shown in Fig. 3, when the capacitance 13 generated by the MJB self-clocking over portion 11 is connected in parallel to this impedance, an impedance locus as shown in the Smith diagram in Fig. 3 is obtained. 14, the input impedance becomes more capacitive, and the resistance component also has a lower value. This decrease in human input impedance not only impedes impedance matching with an external transmission line (normal 50Ω standard line), but also complicates the configuration of an internal matching circuit for ensuring this. That is, this results in an increase in mismatch loss, a more complex internal matching circuit, and a narrower frequency bandwidth, resulting in a significant deterioration of the overall output power characteristics.

FIG. 4 shows the product structure of an FET according to an embodiment of the present invention, and FIG. 5g5 shows the cross-sectional structure of its k"ET step. In FIG. In Fig. 4, unlike the conventional structure in which gate focusing electrodes 1 and 0 are used, the source extraction electrode 5 is placed over most of the extraction side, and in the figure, the entire right half of the chip. A thick insulating layer 16 of several μm, such as polyimide, is formed on the ground electrode and on the gate electrode #1A15. Contact window 17 in part
form. Further, on the insulating layer 16, an IJ tube line electrode 18 is formed thickly by plating or the like.

This electrode 18 and the ground electrode 5 have a dielectric insulating layer 1 between them.
A microstrip line transmission line with 6 is formed.

The strip line electrode 18 is connected to the collect window 17.
It is electrically connected to each gate electrode 1 through the wire, and the other end is sequentially focused in a tournament manner and connected to the gate bonding electrode 19. The width and length of the stripline electrode 18 are determined by its characteristic impedance and electrical length.

With the above structure, it is possible to eliminate the capacitance as a lumped constant caused by the overlapping 9 parts of the source and gate electrodes, which was a problem with the conventional structure, and at the same time, the length of the gate electrode stripe can be shortened, resulting in a reduction in input impedance. High output FET with extremely low loss due to gate width
chips can be realized. In addition, since all the electrical lengths from the gate electrode 1 to the gate bonding electrode 19 are exactly the same with respect to the gate 1 as a pole, the phase difference between each gate electrode caused by the conventional focusing electrode section 10 is also eliminated. The stability during RF operation of the gate is improved, and it is also expected that the output characteristics will be stabilized. Furthermore, since the microstrip line can be configured as a part of the internal matching circuit or itself, the circuit elements can be simplified.

FIG. 3 shows the impedance locus in the structure of this embodiment.If the characteristic impedance of the microstrip line electrode 18 is appropriately selected and the static capacitance is added to the gate bonding electrode 19, the locus will be 20.
It becomes possible to make the input/beadance pure resistance.

As described above, according to the present invention, it is possible to eliminate the parasitic capacitance caused by the electrical conductivity between the gate focusing electrodes, which is a drawback of the conventional structure, and it is possible to increase the impedance, while also reducing the loss caused by the long gate width. Since the balance between each gate is improved, stable, high gain, and wideband output characteristics can be achieved. Furthermore, by forming the gate and source electrodes into a microstrip line structure, the internal matching circuit can be simplified or omitted. - Also, in this embodiment, we have explained how to make the gate electrode into a microstrip line by taking the input side as an example, but it is not to say that a similar structure can be adopted for the 11-force-1 rule, but it is also possible to use the microstrip line for the drain and source electrodes. This makes it possible to easily construct surface-exposed monolithic ICs in the microwave and millimeter wave bands as shown in FIG.

Similarly, in this example, potassium arsenide Schottky barrier type FE
Although the explanation has been given using T as an example, it goes without saying that the scope of effect of the present application is not limited to the semiconductor material and the type of waiting area, but is applicable not only to lateral FETs but also to general semiconductor devices (bipolar, MOS, etc.). It is clear that this is widespread.

[Brief explanation of the drawing]

Figure 1 shows the conventional version; U aA s F 12 '1 for the blade.
Figure 1 and Figure 2 of Hirata show the ridge structure of the conventional
Is it j for the acid koshikomizozukuri? Fig. 3 is a Smith diagram showing the locus of the input impedance.
The figure shows a power GaAsFET according to an embodiment of the present invention.
5 is a plan view showing the electrode structure of G3AsFt'
FIG. 6 is a sectional view showing the chip structure of another embodiment of the present invention. 16... Gate electrode, 2... Source electrode, 3... Drain electrode, 4... Gate lead electrode, 5... Source lead electrode. pole, 6
......Drain extraction electrode, 7...Region line indicating active layer, 8...Ohmic electric field of source electrode, 9...Ohmic field of drain electrode Eicheng, 10...Gate focusing electrode, 11...
...Overlapping part, 12...Intrinsic conductive circuit part,
13... Silent flow, 14...°°° impedance locus, 15... 11 gate poles, 16
...Boat reference 1-117...Contact window, 18...Strip window, 19...
・・・Gate bonding 'ilL, 20...
... Impedance locus. Agent, Patent Attorney, Ryozuke Pa'・）Haku Figure 2, Figure 3, Figure 4

Claims (1)

[Claims] Input, output, and fixed voltage semiconductor regions formed on one main surface of the semiconductor substrate; input, output, and an identification potential electrode;
Either one of the input and output electrodes is formed on the main surface of the fixed potential X electrode via an insulating layer, and the insulating layer, the Mf fixed potential electrode, and the input or output electrode thereon are connected to each other. A transistor characterized by forming a slip line structure.