JPS6348869A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6348869A
JPS6348869A JP19421986A JP19421986A JPS6348869A JP S6348869 A JPS6348869 A JP S6348869A JP 19421986 A JP19421986 A JP 19421986A JP 19421986 A JP19421986 A JP 19421986A JP S6348869 A JPS6348869 A JP S6348869A
Authority
JP
Japan
Prior art keywords
electrode
drain
gate
substrate
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19421986A
Other languages
Japanese (ja)
Inventor
Michihiro Kobiki
小引 通博
Masahiro Yoshida
昌弘 吉田
Takahide Ishikawa
石川 高英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19421986A priority Critical patent/JPS6348869A/en
Publication of JPS6348869A publication Critical patent/JPS6348869A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To suppress a leaking current between a gate and a drain and to improve the withstanding voltage of the gate and the withstanding voltage of the drain, by forming an insulating film between a rear surface electrode and a substrate. CONSTITUTION:A high frequency signal is inputted to a source lead line 10, which is connected to a source electrode 4, by way of a gate lead line 12 having a source inductance L1. The amplified high frequency signal is outputted from a drain electrode 5 by way of a drain lead line 11 having a drain inductance L2. A gate parasitic capacitor C1 and a drain parasitic capacitor C2 are present between a rear surface electrode 7 and a gate electrode 6 and the drain electrode 5 through a semi-insulating GaAs substrate 2 and an insulating film 13. Since the insulating film 13 is formed between the lower surface of the semi- insulating substrate 2 and the rear surface electrode 7, no parasitic resistor is generated between the rear surface electrode 7 and the gate electrode 6 and between the electrode 7 and the drain electrode 5.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、主としてマイクロ波帯における増幅素子と
して用いられる半導体装置、特にGaAs電界効果トラ
ンジスタ(以下GaAsFETと略す)に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device mainly used as an amplification element in a microwave band, and particularly to a GaAs field effect transistor (hereinafter abbreviated as GaAsFET).

〔従来の技術〕[Conventional technology]

第3図は従来のGaAsFETの一例を示す断面図であ
る。この図において、1はGaAsFET。
FIG. 3 is a cross-sectional view showing an example of a conventional GaAsFET. In this figure, 1 is a GaAsFET.

2は半絶縁性GaAs基板、3は前記半絶縁性GaAs
基板2にイオン注入等により形成された動作層、4,5
は前記動作層3にオーム性接触を有するソース電極およ
びドレイン電極、6は前記動作層3にシヲッI・キー接
触を有するゲート電極、7ば前記半絶縁性GaAs基板
2の他方の主面に形成された裏面電極である。
2 is a semi-insulating GaAs substrate; 3 is the semi-insulating GaAs substrate;
Active layers 4 and 5 formed on the substrate 2 by ion implantation, etc.
6 is a gate electrode having an ohmic contact with the active layer 3; 7 is a gate electrode formed on the other main surface of the semi-insulating GaAs substrate 2; This is the back electrode.

そして、GaAsFET1はキャリア8に半田材9を用
いて半田付けされるとともに、ソース電極4はソースリ
ード線10を、ドレイン電極5はドレインリード線11
を、ゲート電極6はゲートリード線12を介して外部電
極に接続される。
Then, the GaAsFET 1 is soldered to the carrier 8 using a solder material 9, and the source electrode 4 is connected to the source lead wire 10, and the drain electrode 5 is connected to the drain lead wire 11.
The gate electrode 6 is connected to an external electrode via a gate lead wire 12.

マイクロ波帯の増幅器としてGaAsFET1を用いる
場合、GaAsFET1の裏面電極7はソースリード線
10と電気的に接続され、接地されろ。
When the GaAsFET 1 is used as a microwave band amplifier, the back electrode 7 of the GaAsFET 1 is electrically connected to the source lead wire 10 and grounded.

ドレイン電極5はドレインリード線11を介して正電位
に保たれ、ゲート電極6はゲートリード線12を介して
負電位に保たれる。ゲート電極6には高周波信号が印加
され、ドレイン電極5より増幅された高周波信号を得る
ことにより、増幅が実現される。
The drain electrode 5 is kept at a positive potential via a drain lead wire 11, and the gate electrode 6 is kept at a negative potential via a gate lead wire 12. A high frequency signal is applied to the gate electrode 6, and amplification is achieved by obtaining the high frequency signal amplified from the drain electrode 5.

第4図は第3図のGaAsFET1の高周波等価回路図
である。この図において、第3図と同−符号は同一部分
を示し、LLはソースインダクタンス、R2はドレイン
インダクタンス、R3はゲートインダクタンス、C1は
ゲート寄生容量、C2ばドレイン寄生容量、R1はゲー
ト寄生抵抗、R2はドレイン寄生抵抗である。
FIG. 4 is a high frequency equivalent circuit diagram of the GaAsFET 1 shown in FIG. In this figure, the same symbols as in FIG. 3 indicate the same parts, LL is the source inductance, R2 is the drain inductance, R3 is the gate inductance, C1 is the gate parasitic capacitance, C2 is the drain parasitic capacitance, R1 is the gate parasitic resistance, R2 is the drain parasitic resistance.

この等両回路では、ソース電極4に接続されるソースリ
ード線10はソースインダクタンスL1を介して接地さ
れ、ゲート電極6にはゲートインダクタンスし3を有す
るゲートリード線12を介して高周波信号が入力され、
ドレイン電極5からはドレインインダクタンスL2を有
するドレインリードR11を介して増幅された高周波信
号が出力される。ゲート電極6およびドレイン電極5に
は、それぞれ半絶縁性GaAs基板2を介して裏面S極
7との間にゲート寄生容量C4およびドレイン寄生容量
C2とともに、ゲート寄生抵抗R□およびドレイン寄生
抵抗R2等が存在している。
In this circuit, a source lead wire 10 connected to the source electrode 4 is grounded via a source inductance L1, and a high frequency signal is input to the gate electrode 6 via a gate lead wire 12 having a gate inductance of 3. ,
An amplified high-frequency signal is output from the drain electrode 5 via a drain lead R11 having a drain inductance L2. The gate electrode 6 and the drain electrode 5 have a gate parasitic capacitance C4, a drain parasitic capacitance C2, a gate parasitic resistance R□, a drain parasitic resistance R2, etc. between the gate electrode 6 and the drain electrode 5, respectively, with the back surface S pole 7 via the semi-insulating GaAs substrate 2. exists.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来のGaAsFET1では、ゲート寄生
抵抗R1およびドレイン寄生抵抗R2が存在しているた
め増幅器として用いた場合、リーク電流の発生要因とな
り、直流動作上はゲート耐圧やドレイン耐圧の低下を招
くうえ、消費電流の増加に結び付き、高周波動作上は入
力信号や出力信号の漏れによる利得や出力の低下を招き
、GaAsFET本来の性能を損なうという問題点があ
った。
In the conventional GaAsFET1 as described above, since there is a gate parasitic resistance R1 and a drain parasitic resistance R2, when used as an amplifier, this becomes a cause of leakage current, leading to a decrease in gate withstand voltage and drain withstand voltage in DC operation. Moreover, this leads to an increase in current consumption, and in high-frequency operation, this leads to a decrease in gain and output due to leakage of input and output signals, which impairs the original performance of the GaAsFET.

この発明は、かかる問題点を解決するためになされたも
ので、ゲートおよびドレインのリーク電流を抑制し、ゲ
ート耐圧、ドレイン耐圧の向上および利得、出力の向上
を実現できる半導体装置を1与ることを目的とする。
The present invention has been made to solve these problems, and provides a semiconductor device that can suppress gate and drain leakage currents, improve gate and drain breakdown voltages, and improve gain and output. With the goal.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、裏面電極と基板との間に
絶縁膜を形成したものである。
A semiconductor device according to the present invention has an insulating film formed between a back electrode and a substrate.

〔作用〕[Effect]

この発明においては、基板と裏面電極とが絶縁され、ゲ
ート寄生抵抗およびドレイン寄生抵抗が存在しない。
In this invention, the substrate and the back electrode are insulated, and there is no gate parasitic resistance or drain parasitic resistance.

〔実施例〕〔Example〕

第1図はこの発明の半導体装置の一実施例を示す断面図
である。この図において、第3図と同一符号は同一部分
を示し、13は前記半絶縁性G&As基板2と裏面電極
7間に形成した絶縁膜で、SiN、Sin、5iON等
カラ構成サレル。
FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention. In this figure, the same reference numerals as in FIG. 3 indicate the same parts, and 13 is an insulating film formed between the semi-insulating G&As substrate 2 and the back electrode 7, which is made of SiN, Sin, 5iON, etc.

ソース電極4に接続されるソースリード線10にはソー
スインダクタンスL1を有するゲートリード線12を介
して高周波信号が入力され、ドレイン電極5からはドレ
インインダクタンスL2を有するドレインリード線11
を介して増幅された高周波信号が出力される。デー1〜
電極6およびドレイン電極5にはそれぞれ半絶縁性Ga
As基板2および絶縁膜13を介して裏面電極7との間
にゲート寄生容量C□およびドレイン寄生容量C2が存
在する。しかし、半絶縁性GaAs基板2の下面と裏面
電極7との間に絶縁yA13が形成されているので、裏
面電極7とゲート電極6との間およびドレイン電極5と
の間に寄生抵抗が生じず、その高周波等価回路図は第2
図に示すようになる。
A high frequency signal is input to a source lead wire 10 connected to the source electrode 4 via a gate lead wire 12 having a source inductance L1, and a high frequency signal is input from the drain electrode 5 to a drain lead wire 11 having a drain inductance L2.
The amplified high-frequency signal is output through the . Day 1~
The electrode 6 and the drain electrode 5 are each made of semi-insulating Ga.
A gate parasitic capacitance C□ and a drain parasitic capacitance C2 exist between the As substrate 2 and the back electrode 7 via the insulating film 13. However, since the insulation yA13 is formed between the lower surface of the semi-insulating GaAs substrate 2 and the back electrode 7, parasitic resistance does not occur between the back electrode 7 and the gate electrode 6 and between the drain electrode 5. , its high frequency equivalent circuit diagram is shown in the second
The result will be as shown in the figure.

なお、上記実施例では、GaAsFETにおいて、半絶
縁性GaAs基板2の裏面電極7との間に絶縁膜13を
介した例について説明したが、GaAsFETの代わり
にGaAsを用いたモノリシックマイクロ波IC(MM
IC)を用いてもよく、上記実施例と同様の効果を奏す
る。
In the above embodiment, an example was explained in which the insulating film 13 was interposed between the GaAsFET and the back electrode 7 of the semi-insulating GaAs substrate 2, but a monolithic microwave IC (MM) using GaAs instead of the GaAsFET was explained.
IC) may also be used, and the same effect as in the above embodiment can be obtained.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、裏面電極と基板との間
に絶縁膜を形成したので、ゲート電極やドレイン電極と
裏面電極との間のリーク電流が防止でき、ゲート耐圧、
ドレイン耐圧の向上および利得、出力の向上を実現でき
るという効果がある。
As explained above, in this invention, since an insulating film is formed between the back electrode and the substrate, leakage current between the gate electrode or drain electrode and the back electrode can be prevented, and the gate breakdown voltage can be increased.
This has the effect of improving drain breakdown voltage and improving gain and output.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の半導体装置の一実施例を示す断面図
、第2図は第1図に示した半導体装置の高周波等価回路
図、第3図は従来のGaAsFETの一例を示す断面図
、第4図は第3図に示したGaAsFETの高周波等価
回路図である。 図において、1はGaAsFET、2は半絶縁性GaA
s基板、3は動作層、4はソース電極、5はドレイン電
極、6はゲート電極、7は裏面電極、8はキャリア、9
は半田材、10はソースリード線、11はドレインリー
ド線、12はゲートリード線、13は絶縁膜である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人 大 岩 増 雄   く外2名)第1図 示2図
FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention, FIG. 2 is a high frequency equivalent circuit diagram of the semiconductor device shown in FIG. 1, and FIG. 3 is a sectional view showing an example of a conventional GaAsFET. FIG. 4 is a high frequency equivalent circuit diagram of the GaAsFET shown in FIG. 3. In the figure, 1 is a GaAsFET, 2 is a semi-insulating GaA
s substrate, 3 is an active layer, 4 is a source electrode, 5 is a drain electrode, 6 is a gate electrode, 7 is a back electrode, 8 is a carrier, 9
1 is a solder material, 10 is a source lead wire, 11 is a drain lead wire, 12 is a gate lead wire, and 13 is an insulating film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 people) Figure 1, Figure 2

Claims (1)

【特許請求の範囲】[Claims] 基板の一方の主面に能動素子が形成され、他方の主面に
裏面電極が形成された半導体装置において、前記裏面電
極と前記基板との間に絶縁膜を形成したことを特徴とす
る半導体装置。
A semiconductor device in which an active element is formed on one main surface of a substrate and a back electrode is formed on the other main surface, characterized in that an insulating film is formed between the back electrode and the substrate. .
JP19421986A 1986-08-19 1986-08-19 Semiconductor device Pending JPS6348869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19421986A JPS6348869A (en) 1986-08-19 1986-08-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19421986A JPS6348869A (en) 1986-08-19 1986-08-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6348869A true JPS6348869A (en) 1988-03-01

Family

ID=16320934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19421986A Pending JPS6348869A (en) 1986-08-19 1986-08-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6348869A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420775B1 (en) 1996-02-29 2002-07-16 Nec Corporation Compound semiconductor device having an ion implanted defect-rich layer for improved backgate effect suppression
JP2013062298A (en) * 2011-09-12 2013-04-04 Toshiba Corp Nitride semiconductor device
WO2015040802A1 (en) * 2013-09-18 2015-03-26 株式会社デンソー Semiconductor device and method for manufacturing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420775B1 (en) 1996-02-29 2002-07-16 Nec Corporation Compound semiconductor device having an ion implanted defect-rich layer for improved backgate effect suppression
JP2013062298A (en) * 2011-09-12 2013-04-04 Toshiba Corp Nitride semiconductor device
WO2015040802A1 (en) * 2013-09-18 2015-03-26 株式会社デンソー Semiconductor device and method for manufacturing same

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