JPH06310953A - Matching circuit - Google Patents

Abstract

PURPOSE:To prevent the distortion in an output waveform and the reduction in a linear output even when a voltage applied to a drain electrode of a field effect transistor(TR) is changed. CONSTITUTION:The circuit is made up of an inductor L2 and capacitors C1, C2 giving a load impedance to a FET. In this matching circuit, a cathode electrode of the capacitor C1 is made up of a varactor diode whose cathode electrode connects to other terminal of the inductor whose one terminal connects to a drain electrode of the FET and whose anode electrode connects to ground.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output side matching circuit used in a power amplifier of a mobile phone or the like.

[0002]

2. Description of the Related Art In order to reduce the size and weight of a mobile phone, the battery itself has been downsized and the voltage has been lowered, so that various electronic parts to be used are required to operate normally at a low voltage. FIG. 4 is a circuit diagram of a monolithic integrated circuit including a field effect transistor output matching circuit used for a power amplifier in a conventional mobile phone. In FIG. 4, RFIN indicates a high frequency input terminal and RFOUT indicates a high frequency output terminal. There is. The input terminal RFIN is connected to one end of the resistor R and is also connected to the gate of a field effect transistor (hereinafter referred to as FET).

The gate bias voltage V _G is applied to the other end of the resistor R.
Is being applied. The source electrode of the FET is grounded, and the drain electrode is connected to the power supply voltage V _DD through the inductor L ₁ and is also connected to the output matching circuit that provides the load impedance. Capacitor C ₃ output matching circuit connected to the inductor L ₂ and the one electrode of which one end is connected to the drain electrode to the inductor L _2, C
₂ , the other electrode of the capacitor C ₃ is grounded, and the other electrode of the capacitor C ₂ is connected to the high frequency output terminal RFOUT.

FIG. 5 is a cross-sectional structural view showing the layout of each part constituting the output matching circuit shown in FIG.
Indicates a semi-insulating GaAs substrate. Semi-insulating GaAs substrate 21
An inductor L ₂ and capacitors C ₃ and C ₂ forming an output matching circuit are formed on the surface of the. Capacitor C
Electrodes 22 and 23 of each one of ₃ and C ₂ are semi-insulating GaAs substrate
Insulating films are formed in parallel on the surface of 21 with a slight gap between them so as to overlap these electrodes 22 and 23 and a part of them.
24 is laminated, and the electrodes 22 and 23 are respectively formed on the insulating film 24.
Electrodes 25 and 26 are stacked on top of each other to form capacitors C ₃ and C ₂ .

A part of the electrode 25 of the capacitor C ₃ is semi-insulating.
On the surface of the GaAs substrate 21, a linear portion 28 made of metal that forms the inductor L ₂ is spirally formed on the extended portion of the electrode 25 with a polyimide resin 27 therebetween.
In such a power amplifier circuit, the input terminal RFIN
The signal input from is amplified by the FET, passes through the output matching circuit, and is output from the output terminal RFOUT. By the way, the output signal waveform from the output terminal RFOUT is regulated by the load impedance determined by the output matching circuit and the static characteristics of the FET.

FIG. 6 is a static characteristic of the FET shown in FIG. 4, that is, a V _DS -I _DS characteristic diagram at different power supply voltages V _DD , where the horizontal axis represents the drain voltage V _DS and the vertical axis represents the drain current I _DS . Is shown. In the graph, the alternate long and short dash lines AA 'and BB' indicate load lines. As is apparent from FIG. 6, when the power supply voltage is V _DD1 , the output voltage and output current waveforms determined by the load line AA ′ are obtained, and when the power supply voltage V _DD2 is lower than this, the load line is obtained. The output voltage and output current waveforms determined by BB 'are obtained.

[0007]

In the conventional power amplifier circuit as described above, when the power supply voltage changes from V _DD1 to V _DD2 , the output matching circuit itself does not change as shown in FIG. The slope does not change, and the load line changes from A-A 'to BB' by the amount of decrease in the power supply voltage. Therefore, the power supply voltage is V _DD1 , that is, the load line is A-
In the case of A ', the output voltage and output current waveforms are B-
When it reaches B ', the waveform is clipped on the B'side and the output voltage,
The output current waveform is distorted as shown by B and B ',
There is a problem that the obtained linear output power also decreases.
Further, as is clear from FIG. 5, since the capacitors C ₃ and C ₂ are separately formed in parallel, the process is simplified and shortened, but there is a problem that the chip area is increased.

The present invention has been made in view of the above circumstances, and an object thereof is to prevent distortion of the output signal waveform even when the power supply voltage changes, to prevent a decrease in linear output power, and to further reduce the chip. An object of the present invention is to provide a matching circuit capable of reducing the surface area.

[0009]

A matching circuit according to the present invention includes an inductor connected to the drain electrode and a first and second inductor in a source-grounded field effect transistor in which a predetermined voltage is applied to the drain electrode. In a matching circuit that includes a capacitor and applies a load impedance to the field effect transistor, the first capacitor has a cathode electrode connected to the other end of an inductor whose one end is connected to the drain electrode and an anode electrode connected to the other end of the inductor. It is characterized by being composed of a grounded varactor diode.

[0010]

According to the present invention, the capacitance of the varactor diode changes according to the change of the voltage applied to the drain electrode of the field effect transistor, and the load impedance of the field effect transistor also changes according to the power supply voltage. It is possible to prevent distortion of the output signal and reduction of the linear output power.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a circuit diagram of a matching circuit and a monolithic integrated circuit including field effect transistors according to the present invention. In FIG. 1, RFIN is a high frequency input terminal, R
Similarly, FOUT indicates a high frequency output terminal. The input terminal RFIN is connected to one end of the resistor R, and
It is connected to the gate of the FET.

The gate bias voltage V _G is applied to the other end of the resistor R.
Is being applied. The source electrode of the FET is grounded, and the drain electrode is applied with the power supply voltage V _DD through the inductor L ₁ and is connected to the output matching circuit which provides the load impedance. The output matching circuit includes an inductor L ₂ having one end connected to the drain electrode and capacitors C ₁ and C ₂ . The capacitor C ₁ is configured as a varactor diode whose cathode electrode is connected to the inductor L ₂ and whose anode electrode is grounded, and the capacitor C ₂ has one electrode thereof connected to the inductor L ₂ ,
The other electrode is connected to the high frequency output terminal RFOUT.

FIG. 2 is a cross-sectional structural view showing the layout of each component constituting the output matching circuit in the embodiment of the present invention, in which 1 denotes a semi-insulating GaAs substrate. Semi-insulating
The GaAs substrate 1 has a variable capacitor C inside.
₁ , and a capacitor C ₂ and an inductor L ₂ are formed on the surface. Inside the semi-insulating GaAs substrate 1, an ion implantation layer 11 having a conductivity type of n ⁺ , and an ion implantation layer 12 having a conductivity type of n type are formed in contact with the ion implantation layer 11.
The ion implantation layer 12 is separated between the ion implantation layer 13 having a conductivity type of P ⁺ type and the ion implantation layer 11 of the n ⁺ type in a state of being pn-junctioned with a part of the n type ion implantation layer 12. It is formed in the state.

A common electrode 14 shared by the capacitors C ₁ and C ₂ is provided on the surface of the semi-insulating GaAs substrate 1 so as to be in contact with the surface of the n ⁺ type ion implantation layer 11, and the p
The electrode 15 of the capacitor C ₁ is formed on the surface of the semi-insulating GaAs substrate 1 in contact with the ⁺ type ion implantation layer 13. The ion-implanted layers 11, 12 and 13 are subjected to activation annealing treatment before the formation of the electrodes 14 and 15. As a result, the capacitor C ₁ formed by the pn junction capacitance generated at the interface between the n-type ion implantation layer 12 and the p ⁺ -type ion implantation layer 13 is formed in the semi-insulating GaAs substrate 1.

An insulating film made of SiN is formed on the surface of the common electrode 14.
The second electrode of the MIM (metal insulator metal) structure is formed by forming the electrode 17 on the common electrode 14 with 16 interposed therebetween.
Capacitor C ₂ is formed. Also, the common electrode
14 extends a part of it on the surface of the semi-insulating GaAs substrate 1,
Conventional with intervening polyimide resin 18 as well, a metal line portion 19 constituting the inductor L ₂ is formed in a spiral shape, it is connected to one end of the inductor L ₂ near the center of the spiral.

FIG. 3 is a static characteristic of the FET shown in FIG. 1, that is, a V _DS -I _DS characteristic diagram when the power supply voltage V _DD is different. The horizontal axis represents the drain voltage V _DS and the vertical axis represents the drain current I _DS . Is shown. In the graph, the alternate long and short dash lines AA 'and BB' indicate load lines. As is apparent from FIG. 3, when the power supply voltage is V _DD1 (for example, 4 V), the output voltage and output current waveforms A and A determined by the load line AA ′ are obtained,
When the power supply voltage V _DD2 (for example, 2 V) is lower than this, the output voltage and output current waveforms shown by B and B determined by the load line BB ′ are obtained.

For example, when the power supply voltage changes from V _DD1 (4 V) to the power supply voltage V _DD2 (2 V), the load line is AA '.
The load line BB 'has a smaller output voltage waveform than the load line A-A', but a larger output current waveform than the load line A-A '. Therefore, the output power does not change and the output waveform is not distorted.

Next, numerical examples of the matching circuit shown in the embodiment will be shown. For example, a FET having the characteristics shown below is used, and the linear output power is 22 dBm when the power supply voltage is 2V to 4V.
In order to obtain, the characteristics shown in Table 1 are required for the capacitors C ₁ and C ₂ . Pinch off voltage V _GS (OFF) =-2V Drain saturation current I _DSS = 350mA Knee voltage V _K = 0.5V

[0019]

[Table 1]

Table 2 shows the conditions when the variable capacitance capacitor C ₁ required to satisfy the requirements shown in Table 1 is produced by the ion implantation method.

[0021]

[Table 2]

A capacitor C ₁ manufactured under the conditions shown in Table 2
When the anode electrode of is connected to the ground and the power supply voltage of 4V, 3V, 2V is applied to the cathode electrode, the capacitance becomes 1.4
pF, 1.8 pF and 3.2 pF were obtained, and it was confirmed that the conditions in Table 1 could be substantially satisfied. Further, as shown in FIG. 2, one electrode of the capacitor C ₂ is shared with the cathode electrode of the capacitor C ₁ , and a SiN-made 1600-thickness electrode is provided on the shared electrode 14.
MI in which the other electrode 17 is arranged with the insulating film 16 of Å interposed
It has an M (metal insulator metal) structure, and the area of this capacitor C ₂ is 15000 μm ²
Then, it was confirmed that the required capacitance of 6 pF was obtained.

[0023]

As described above, in the matching circuit according to the present invention, even if the voltage applied to the drain electrode of the field effect transistor changes, the capacitance of the varactor diode changes in accordance with this, and the field effect transistor According to the present invention, the output waveform is not distorted by changing the load impedance of the device, a desired linear output can be obtained, and the device can be applied to a small capacity of a power supply accompanying the downsizing and weight saving of a mobile phone or the like. Has an excellent effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a matching circuit according to the present invention.

FIG. 2 is a sectional structural view showing a layout of each component in the matching circuit shown in FIG.

FIG. 3 shows V _DS -I of the field effect transistor used in FIG.
_{It is a DS} characteristic diagram.

FIG. 4 is a circuit diagram of a conventional output matching circuit.

5 is a sectional structural view of each component in the output matching circuit shown in FIG.

6 is a V _DS -I of the field effect transistor used in FIG.
_{It is a DS} characteristic diagram.

[Explanation of symbols]

1 semi-insulating GaAs substrate 11 n ⁺ type ion diffusion layer 12 n type ion diffusion layer 13 p ⁺ type ion diffusion layer 14 shared electrode 15 electrode 16 insulating film 17 electrode 18 polyimide resin RFIN input terminal R resistance L ₁ , L ₂ inductor FET field effect transistor C ₁ variable capacitance capacitor (varactor diode) C ₂ capacitor RFOUT output terminal V _DD power supply voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Yatsuo Harada, 2-18, Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd.

Claims (2)

[Claims] 1. An inductor connected to the drain electrode of a source-grounded field effect transistor adapted to apply a predetermined voltage to the drain electrode, and first and second inductors.
In a matching circuit configured to provide a load impedance to the field effect transistor, the first capacitor has a cathode electrode connected to the other end of an inductor whose one end is connected to the drain electrode, and an anode electrode. A matching circuit characterized by comprising a varactor diode grounded. 2. The operating layer of the varactor diode is formed in a semiconductor substrate, and the second capacitor is formed in a MIM structure on the cathode electrode of the varactor diode formed on the surface of the semiconductor substrate. 1. The matching circuit according to 1.