JPS6228089Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an operational amplifier using an insulated gate field effect transistor (hereinafter referred to as MOS).

More specifically, the present invention relates to an operational amplifier using a C-MOS configuration.

The first object of the present invention is to provide an operational amplifier configured using C-MOS.

The second object of the present invention is the above-mentioned operational amplifier,
Analog circuits such as differential amplifiers constituting the operational amplifier are easily manufactured monolithically using a normal MOS manufacturing process.

Recently, there has been a remarkable shift to MOS in digital parts, and if the analog part could be constructed without much change in the MOS manufacturing process, or if possible, without changing the process at all, various analog circuits and digital circuits could be integrated into the same MOS chip. aggregated, price,
This is an ideal configuration in terms of reliability, ease of design, and applicability. Since C-MOS is normally off-logic, it has an extremely low power consumption element configuration that consumes power only in the transient state.

Even the switching level is determined by the MOS threshold, so if one turns on, the other turns on.
When it is turned off, it is stable and when turned off.
Because the impedance is extremely high, logic oscillations occur up to the power supply voltage. Furthermore, the input bias current of the MOS is approximately 10 ^-12 A due to the insulated gate, achieving the ideal high input impedance of an operational amplifier.

In view of this, the present invention aims to provide an operational amplifier using C-MOS.

The current and voltage characteristics of the MOS shown in Fig. 1 are as shown in Fig. 2, and the voltage between its gate G and source S is V.
Keeping _GS constant, drain D-source S voltage V
If we change _DS and take the current I _DS between D and S, then if the MOS threshold voltage is V _GT , then V _DS = V
_GS −V Unsaturated region A, saturated region B with _GT as the boundary
is observed. B is the linear variation region of V _DS in the first approximation. For example, as shown in FIG. 3, when the load line L intersects at the point where V _GS = V _G2S and I _DS = V _D2S , V When a signal of _GS = V _G2S + (V _G1S - V _G2S ) is input, V _DS = V _D1S and V _GS = V _G2S +
When a signal of (V _G3S −V _G2S ) is input, V _DS =V _D3S , so that the signal input to the gate can be linearly amplified at the drain. From another perspective, B in FIG. 2 is the current saturation region, where the current is saturated. These two basic characteristics are used wisely to construct the desired operational amplifier.

As shown in FIG. 4, the operational amplifier of the present invention includes a reference voltage source C, a constant current bias section D receiving the voltage, an input section mirror pair differential stage E, and a differential output of F, E, and F. The output stage H is composed of a level shift amplification stage G that amplifies the output while level shifting the output, and an output stage H that further amplifies the output and outputs it at a desired low impedance. The outputs of E, F and D are connected in series to form a differential amplifier as a whole. The reason for including the reference voltage source C is to minimize power supply voltage fluctuations and temperature fluctuations in the operational amplifier. For example, fluctuations in offset voltages occurring at E and F due to power source and temperature can be greatly improved by using a stable reference voltage source C and constant current bias section D. A first example embodying such a configuration is shown in FIG.

FIG. 5 shows an operational amplifier with a dual power supply configuration of V _DD -V _g -V _SS . Let us explain Fig. 5 one by one.

A reference voltage source C generates a reference voltage relative to the intermediate voltage V _g . The voltage must be generated so that it is stable against power supply fluctuations and temperature fluctuations. Furthermore, a stable circuit configuration is established even if the intermediate voltage V _g is not exactly at a potential midway between V _DD and V _SS . In order to meet this requirement and consist of only MOS, the reference voltage is
The system is designed to generate a difference between the MOS thresholds with respect to the intermediate voltage V _g .

N-channel transistors 1 and 2 are elements with exactly the same characteristics, and if V _DD -V _SS =V _dd , then the output will be V _dd -V _g with V _SS as the reference. N-channel transistors 3 and 4 have the same conductance coefficient but different thresholds, and if the threshold of transistor 3 is V _TN , then the output V _st will be V _st =V _{TN -VGTN} +V _g . These N-channel transistors with different thresholds are manufactured by channel doping using ion implantation. Normal C-MOS
Since a P ^- layer is formed on a low-concentration N ^- substrate,
In the first place, the P ^- layer is made to have a relatively high concentration so as to obtain a desired V _TN , and in order to obtain V _GTN , for example, ³¹ P ⁺
In this case, if the gate thickness, channel length, and channel width of transistors 3 and 4 are the same, the conductance coefficients of transistors 3 and 4 are almost the same, but the thresholds are different. Also, the temperature characteristics and the threshold shift are affected by the net implantation amount.
Nnet, the elementary charge, is given by pNnet/Cox, where Cox is the unit gate capacitance, so they can be considered to be equivalent, and there is no problem in considering the conductance coefficients to be equivalent as well.

However, on the other hand, the method of obtaining a high threshold with a low concentration of P ^- layer and ¹¹ B ⁺ channel doping is very structurally sensitive, and the conductance coefficient and threshold reflect the structural sensitivity, and are 3,4 It is difficult to correct the conductance coefficients of transistors theoretically and experimentally to make them equal. Furthermore, the method of controlling the gate film thickness to be thick at 3 and thin at 4 is not good because the temperature characteristics of the threshold depend on the gate film thickness, even though the conductance coefficients can be made the same depending on the geometry. After all, the reference voltage can be obtained using the method described at the beginning. Hereinafter, such a low threshold transistor due to channel doping will be represented by a broken line at the gate as shown in FIG. Also, the reason why we adopted N-channel transistors in the C circuit is that in normal C-MOS, the substrate N ^- of P-channel transistors is common, and P ^- is the only substrate that can be floated on the power supply. . Furthermore, in order to match the characteristics of the first and second transistors, no body effect occurs. This is because common use of substrate sources is required.
Incidentally, the circuit configuration of C can be similarly implemented as shown in FIG. In this circuit, 18,2
By matching the ratio of the conductance coefficients of the N-channel transistors 0 and the conductance coefficients of the P-channel transistors 19 and 21, the difference in threshold between the P-channel transistors 19 and 21 can be generated as a reference voltage. In this case as well, in order to produce a transistor with a different threshold, a high concentration N ^- substrate is used in the first place, and in order to produce a transistor with a lower threshold, channel doping is performed, for example with ¹¹ B ⁺ . Or channel doping 19,2
Of course, it is also possible to apply doping to both 19 and 21 and change the doping amount between 19 and 21. This also applies to 3 and 4 in FIG. Also, 1
Transistors 8 and 20 may be high threshold transistors that do not have broken lines on their gates, and when V _g is V _dd /2, N-channel transistors 1 and 2 are omitted in FIG. The gate potential of the N-channel transistor can be set to V _g .

Next, receiving the reference voltage of section C, the constant current bias circuit of section D converts the reference voltage from a value based on the intermediate voltage V _g to a value based on V _SS , and regulated the differential amplifiers E and F. A good constant current bias is achieved by keeping the gate potential of the current source 9 constant.

Ratio of conductance coefficients of N-channel transistors 5 and 7 and P-channel transistors 6 and 8
By matching the ratio of the conductance coefficients of , the gate voltage of the constant current source N-channel transistor 9 becomes V _TN −V _GTN with respect to V _SS . To do this, set the threshold to V in advance.
It is necessary to choose so that _TN > 2V _GTN . V _G =
By setting V _TN -V _GTN , the gate potential of the constant current source 9 is stable against power supply fluctuations and temperature fluctuations, and its constant current property is extremely stable. In order for the constant current property of this transistor to be effectively exhibited, V _TN
It is necessary to reduce the -2V _GTN to the extent that it does not reduce the operational amplifier speed, or slew rate, below the desired value.

Next, the differential amplification stage including E, F, and transistor 9 is the most characteristic circuit of the present invention,
It is no exaggeration to say that the performance of an operational amplifier depends on this circuit. N-channel transistors 10 and 12 and P-channel transistors 11 and 13 are elements of a mirror pair having exactly the same characteristics. Therefore, 12 gate voltages or inverting inputs V _I and 10 gate voltages or non-inverting inputs V _N
For common mode inputs with equal _I , each output V _DI
and V _DNI are now equal. This is because the gate and drain of the P-channel transistor 11 are connected, which is further connected to the gate of the transistor 13, so that the mirror pair 11 and 13 are both in the region shown in FIG. 2B. Furthermore, the common mode input is not amplified as an output. This is because the current flowing into the constant current source 9 is constant, and each half of it is 11, 1
3, the effective gate voltages of 11 and 13 are constant, and therefore V _DNI and V _DI are constant.

Also, when an input that makes V _NI = V _I + α is input, V _NI = (V _I + α/2) + α/2, V _I = (V _I + α
/2) - α/2 It can be considered as α/2 in-phase and α/2 differential input,
The effective gate potential increase of 1 2 is -α/2, and the effective gate potential increase of 10 is α/2. Therefore, when the conductance coefficients of 10 and 11 are almost equal, the effective gate potential increase of 11, that is, 13 is also α/2. As a result, the voltage V _DI at the drain connection terminals 1, 2, and 13 is moved so that any current flows into the transistor 12, and no current flows from the transistor 13,
Effective differential input amplification is achieved at the matching point of the sink and source. This is essentially nothing more than drawing the transistor curve of V _GS = V _G2S symmetrically from the point of V _DS = V _dd instead of L in Fig. 3 and using it as the load curve, and the slope of L is approximately It is a configuration that is zero, and its V _GIS 〓V _G
This is because the signal _2S −α is amplified. Therefore, the common mode suppression ratio of this differential amplifier is high, and since the gate voltage of the constant current source 9 is stable against power supply fluctuations and temperature fluctuations, the common mode suppression ratio is also stable. V _SI and V _SNI are offset adjustment terminals, which can be adjusted with a 3-terminal variable resistor as shown in Figure 7, or with 22, 23 as shown in Figure 8.
The resistor of transistor 1 is constructed monolithically using a diffused resistor in a semiconductor, a polycrystalline silicon resistor, etc.
1. The connection between the resistor 22, the transistor 13, and the resistor 23 can also be adjusted externally using a two-terminal variable resistor.

Furthermore, the circuit shown in FIG. 7 may be provided between transistors 10, 12 and transistor 9 in FIG. That is, the source of transistor 10 is connected to V _SNI in FIG. 7, the source of transistor 12 is connected to V _SI in FIG. 7, and the drain of transistor 9 is connected to V SNI in FIG.
A similar effect can be obtained by connecting to V _DD in the figure.

It is also important to take measures in design to keep such offset voltages low in the first place. For example, taking the elements 10 and 12 as an example, the characteristics of the elements can be improved by arranging the elements two by two point-symmetrically as shown in Figure 9-b, which is an improved version of Figure 9-a. The determined conductance coefficient (mobility, gate film thickness, channel length, channel width), threshold, and ∂V _DS /∂I _DS V _G =
The saturation resistance, which is given as a constant, can also be made almost the same. This is because the bias in the distribution of characteristics within the wafer can be corrected. Furthermore, in addition to the problem with the element pattern, one more point is to reduce the constant current value of the differential amplifier stage within a range that does not reduce the slew rate of the operational amplifier below the desired value, that is, the effective gate voltage of the constant current source 9. V _TN -2V The goal is to keep _GTN small. In addition, by keeping the gate voltage of 9 constant and suppressing the variation in the conductance coefficient to a low level considering Figure 9-b, it is possible to improve the power supply fluctuation of the offset voltage and, by extension, the power fluctuation rejection ratio. Can be done. Temperature fluctuations can also be improved because variations in the conductance coefficient are kept low and the effective gate voltage of 9 is made small. Furthermore, since the differential input elements are N-channel transistors, inputs ranging from slightly below 2V _GTN at the bottom to almost above _VDD at the top can be input. In order to further improve the input voltage to slightly below V _GTN , if the offset fluctuations resulting from the increase/decrease of the threshold due to the body effect are not a problem, then the substrates 24 and 25 should be set to V _SS as shown in Figure 10. It can be done.

Next, upon receiving the output of the differential amplification stage, the level shift circuit G shifts the level of the differential output and further amplifies it. At the same time, the differential amplifier, constant current source,
Fluctuations in the entire system including the level shift circuit,
For example, fluctuations in temperature and power supply are not amplified. This is because the output V _L does not change because the N-channel transistor 14 and the P-channel transistor 15 fluctuate in the same direction as viewed from their sources to the drains due to these factors.
Again, the method of amplification is V _GS in Figure 3.
=V _G2S is drawn symmetrically from the point of V _DS =V _dd , and the curve of V _GS =V _G2S is used as a load curve with respect to that curve, and its amplification factor is high.

Finally, upon receiving the output of V _L , an inverter consisting of an N-channel transistor 16 and a P-channel transistor 17 forming an output buffer amplifies the input and outputs it. The reason why thresholds 16 and 17 are set high is to widen the range of linear amplification of the output _V0.If the emphasis is on lowering the output impedance, the channel length should be made smaller than that of other amplification stages, or 26,2 as shown in Figure 11
7 can be made a low threshold by channel doping. Furthermore, in order to obtain a low impedance output even if the gain of the output circuit is sacrificed, a source follower output configuration using 28 and 29N channel transistors can be used as shown in FIG. Almost the same effect can be obtained by connecting this 29 substrate to V _SS without making it common to the source.

In addition, in C-MOS, an emitter follower circuit with a common collector _NPN is simultaneously created using the P ^- layer that forms the N channel substrate. N channel as shown in Figure 28
A low impedance emitter follower output circuit is also possible by using a MOS as a load.

Using the operational amplifier shown in Figure 5 as a differential amplifier,
There is no problem if the configuration does not apply feedback between V _p and V _I and V _NI , but if feedback is applied, stability against oscillation becomes a problem. If a frequency correction capacitor is used for correction, it is corrected by adding capacitors 30 and 31 as shown in FIGS. 13a and 13b. Of course, the 30V _DD can be replaced with V _SS or V _g . Also, 31 is 30
Compared to this, with the same frequency correction, the capacitance can be reduced to approximately 1/the amplification factor of the level shift stage. moreover,
In the case where oscillation is most likely to occur, such as in a voltage follower, the gain of the output circuit is sacrificed to output V _L directly, or the channel length of the output circuit is made smaller than that of the other amplifier stages, or the 11th amplifier stage is used. If you lower the gain by narrowing the amplification range considerably as shown in the figure, or if you reduce the output circuit gain to 1, for example, as shown in Figure 12,
Furthermore, the correction capacitance can be made smaller by the gain of the output circuit. In this case, in the case of correction that takes the form shown in Figure 13b, and for example, in the case of correction such as capacitance feedback from _Vp to _VI , the correction capacitor can be monolithically built with a MOS type capacitor as shown in Figure 14. Can be done. In FIG. 14, 32 is an N ^- base, 33 is a P ⁺ high concentration region, 34 is a gate oxide film, 35 is a metal for wiring, such as aluminum,
36 is a contact with the P ⁺ region, which is an alloy forming region with aluminum and a base semiconductor such as silicon. If this capacitance distribution is expressed as a lumped constant, it will be formed as shown in Figure 15, but the capacitance 37
The unit area capacitance is given by Eox/τ, where the dielectric constant of the gate oxide film is εox and the film thickness is τ, so if τ is decreased, the capacitance increases, but
Since the film thickness suitable for channel doping is about 1000 Å or less, it can be formed at the same time as forming the gate film of other MOS ^transistor elements. Although the dielectric constant of the substrate, for example silicon, is higher than that of the gate film, the concentration of the substrate 32 is not so high, so 37>38. Therefore,
Terminals 35 and 36 in FIG. 15 are as shown in FIG.
In case b, either V _DI or V _L may be used, and 3
When 5 is V _DI and 36 is V _L , it can be made in common with 15 transistors. This is because the drain is 33 and the gate is 35. Also, when parasitic capacitor 38 becomes a problem, 35 is set to V _L and 36 is set to V _DI
In addition, in the case of capacitive feedback to the input, it is better to set 35 to V _p and 36 to V _I. In normal C-MOS, the N-channel region can also be used as a capacitor, and in Figure 14, 32 is P ^-
You can do this by changing 33 to N ⁺ .

By the way, the operational amplifiers of the present invention shown in Figs. 5 to 15 also do not suffer any damage even if the ordinary C-MOS is manufactured on an N ^- substrate instead of a P ^- substrate. isn't it. In that case, all that is required is to change the diffusion format from P to N and from N to P, and to change the conductance format from P channel to N channel, and from N channel to P channel.

Also, for E, F, G, and H, channel doping is not performed on either P or N or both P and N.
It can be constructed using MOS transistors, and even if channel doping is used, the present invention shown in FIGS. 5 to 15 can be manufactured using only either a P channel or an N channel.

For example, for ion implantation, only ¹¹ B+ and C
The circuit is constructed as shown in FIG. 6, the N-channel gate broken line is taken, and a low threshold is created in accordance with the channel doping of the P-channel.

In order to improve stability against noise, it is necessary to reduce the gate film thickness of the transistor and increase the gate area. Decreasing the gate film thickness improves the saturation resistance, which increases the gain, and increasing the gate area also increases the gain, since the saturation resistance improves as the channel length increases. In a three-stage C-MOS amplification stage configuration, the operational amplifier has a gate film thickness of 1000 Å or less, a channel length of 10 μ or more on the mask, and a substrate concentration larger than the digital logic size.
With an aluminum gate transistor configuration of 10 ¹⁴ /cm ³ or more, it is possible to obtain an open loop gain of 10 ⁴ times or more, and the power supply voltage can be adjusted to a stopper to reduce reverse leakage of the diode that electrically insulates the element. If the interval is 2μ or more, the voltage will be 5V or more.

Moreover, the above-mentioned present invention can be used as a differential amplifier, and its usage includes using only the differential stage in combination with C or D, or including only 9 with an appropriate bias circuit, or even as a level shift circuit. In addition to how to use it including the output circuit, how to use it by connecting a differential stage to the output of a level shift stage, and how to connect a differential stage to a differential stage, there are several uses. Can be used together.
It can also be used as a comparator to compare two signals, and input voltages higher than V _DD can be cut off by a voltage follower, so to speak, as a rectifier.

Next, an operational amplifier using one power supply with V _DD -V _SS is:
This is possible by replacing the reference voltage sources C and D in FIG. 5 or 6 with those shown in FIGS. 16 and 17, respectively. In FIG. 16, N-channel transistors 1 and 2 having completely identical characteristics in FIG.
By connecting the gate of 1 to the drain, an intermediate voltage is created internally, and the source of 5 is connected to this, and the increase in current due to 5 is achieved by newly connecting 39, which has exactly the same characteristics as 5, in parallel with 1. This stabilizes the intermediate voltage. This is because the effective gate voltage of 5 becomes the effective gate voltage of 39. In Fig. 17, an intermediate voltage is created using N-channel transistors 40 and 41, which have exactly the same characteristics, and the source of 5 is connected to this. By connecting them in parallel, the intermediate voltage is stabilized. The above-mentioned precautions in Figures 16 and 17 are also valid when the MOS is made from a P ^-base rather than from an N ^-base , and whether or not channel doping is applied. For example, F, E, G, H in Figures 16 and 5.
For ion implantation, for example, use only ³¹ P ⁺ , take the dashed line of the gate of the P channel transistor, match the threshold of the P channel transistor to the threshold of the N channel transistor to be channel doped, and adjust the concentration of the N ^- base. In FIG. 17, 40 and 41 are N-channel transistors without channel doping, or
In E, F, G, and H of Fig. 7 and Fig. 5, for example, only ¹¹ B ⁺ is used as ion implantation, and the gate dotted line of the N-channel transistor is taken, and it is aligned with the threshold of the P-channel transistor to be doped. , which determines the concentration of the P ^- layer of an N-channel transistor. Also, if such a single power supply can be used, a very interesting configuration can be created in which the external _GND is set to _VDD for amplification of minute signals. In addition, the differential amplifier, comparator,
Of course, it is also possible to use a rectifier or the like.

In any case, according to the present invention, C-
Analog circuits such as differential, arithmetic, comparators, and rectifiers using MOS can be fabricated monolithically on the same MOS chip as digital circuits such as logic circuits. Furthermore, in the present invention, since the gate electrodes of the transistors 11 and 13 constituting the differential amplification stage are connected to the drain electrode of one of the transistors, both transistors can be operated in the saturation region. Moreover, since the gate electrodes of both transistors are commonly connected, the drain currents of both transistors become equal due to the property that the drain current in the saturation region depends almost only on the gate voltage, and as a result, the gate electrodes of transistors 10 and 12 are Since the drain voltage is changed so that the same current flows even if the voltages are different, the output V _DI of the differential amplifier stage can obtain a large gain.

[Brief explanation of the drawing]

Figure 1 is a diagram representing MOS. Figure 2 is Figure 1
A diagram showing current-voltage characteristics of MOS. Figure 3 shows 1,
Figure 2 shows a method of amplifying MOS. FIG. 4 is an explanatory diagram of the operational amplifier of the present invention. FIG. 5 shows a specific example of the operational amplifier of the present invention. 6 to 15 are illustrations of other specific examples, variations, or illustrations of the operational amplifier of the present invention shown in FIG. FIGS. 16 and 17 show another specific example of the operational amplifier of the present invention. G...Gate, S...Source, D...Drain, I _DS ...Drain-source current, V _DS ...
Drain-source voltage, V _GS ... Gate-source voltage, V _GS - V _GT ... Drain-source voltage at the boundary between unsaturated (A) and saturated (B) regions, L ... Load line, C ...Reference voltage source, D...Low current bias section, E, F...Input mirror pair differential stage, G...
Level shift amplification stage, H...output stage, V _DD , V _SS
...Positive and negative potentials of the power supply, V _I , V _NI ...
…Inverting, non-inverting input voltage or its terminal, V _g …
... intermediate voltage potential or its terminal, V _ST ... reference voltage or its terminal, V _G ... gate voltage of constant current source or its terminal, V _DI , V _DNI ... drain voltage of inverting and non-inverting input transistor or Its terminals, V _SI , V _SNI ...E, F differential stage P channel transistor source voltage or its terminals, V _L
...Level shift stage output voltage or its terminals,
V _p ...output stage power or its terminal, S ₁₀ , G ₁₀ ,
D ₁₀ ... Each source, gate, and drain of the N-channel transistor 10, S ₁₂ , G ₁₂ , D ₁₂ ... Each source, gate, and drain of the N-channel transistor 12, 1 to 5, 7, 9, 10, 12, 14,1
6, 18, 20, 24-26, 28, 29, 3
9,40-42...N channel transistor,
6, 8, 11, 13, 15, 17, 19, 21,
27...P channel transistor, 22, 23...
... Monolithically built resistance, 30, 31...
Capacitor, 32, 33...N ^- ,P ⁺ diffusion layer,
34...Gate oxide film, 35...Metal wiring on the gate, 36...Contact with 33, 37, 38
...A monolithically formed capacitor.

Claims (1)

[Scope of utility model registration request] In an amplifier comprising at least a reference voltage source, a constant current bias section, and a differential amplification stage, the active elements constituting the reference voltage source, constant current bias section, and differential amplification stage are all formed on the same semiconductor substrate. The constant current bias section includes a constant current source transistor connected in series between the differential amplification stage and a second power supply potential, and a gate electrode of the constant current source transistor is configured of a MOS transistor. A voltage based on the output voltage of the reference voltage source is applied, and the differential amplification stage has a first
MOS transistor and a second MOS transistor of the second conductivity type
a first series circuit consisting of a transistor;
A second series circuit including a third MOS transistor of a conductivity type and a fourth MOS transistor of a second conductivity type is connected in parallel between a second power supply potential and the constant current source transistor; 1 of
The gate electrodes of the MOS transistor and the third MOS transistor are connected in common to the gate electrode of the first MOS transistor.
Connected to the drain electrode of the MOS transistor,
The gate electrodes of the second MOS transistor and the fourth MOS transistor serve as an inverting input and a non-inverting input, respectively, and are operated in a current saturation region. An operational amplifier characterized in that it is formed from source and drain gate electrodes.