JPH0410704A - Operational amplifier - Google Patents

Abstract

PURPOSE:To reduce output impedance and to drive a large load connected to the output of the operational amplifier by making the output stage of the operational amplifier into source-follower constitution with use of plural n- channel MOS transistors(TRs). CONSTITUTION:Differential amplifier stages E, F and a level shifting stage G for inputting the outputs of the stages E, F are respectively constituted of CMOS TRs, and an output stage H is constituted of a 1st n-channel MOS TR 28 and a 2nd n-channel MOS TR 29 for inputting the output of the stage G to a gate while serially connecting both the TRs between power sources. Namely, the output stage H is constituted of only the n-channel MOS TRs instead of CMOS TR, i.e., the source-follower output constitution with use of the n- channel MOS TRs 28, 29 is adopted. Consequently, the output impedance can be reduced and a large load can be driven by the output of the operational amplifier.

Description

[Detailed description of the invention]

[0001]

[Industrial application field]

The present invention relates to an insulated gate field effect transistor (hereinafter M
03). [0002] More particularly, the present invention relates to an operational amplifier using a C-MO3 configuration. [0003]

[Conventional technology]

Recently, with the rapid shift to MOS in digital parts, it is possible to configure analog parts without much change in the MO3 manufacturing process, and if possible, without changing the process at all, and various analog and digital circuits can be integrated into the same MOS chip. An ideal configuration is required in terms of price, reliability, ease of design, and applicability. [0004]

[Problem to be solved by the invention]

Since the C-MOS is normally an off logic, it has an extremely low power consumption element configuration that consumes power only in the transient state. [0005] Since the switching level is determined by the threshold of the MOS, it is stable such that when one is turned on, the other is turned off, and because the OFF impedance is extremely high, logic oscillations occur up to the power supply voltage. Furthermore, a high input impedance is achieved which is ideal for input bias currents. [0006] In view of this, the present invention provides an operational amplifier using C-MOS. [0007]

[Means to solve the problem]

The current and voltage characteristics of the MOS shown in Figure 1 are as shown in Figure 2, by keeping the gate G-source S voltage constant and changing the drain D-source S voltage VDS to obtain the D-3S open current ■. And if the threshold voltage of MOS is V, then vDs=VDS
An unsaturated region A and a saturated region B are observed with GTGS-VGT as the boundary. B is the linear variation region of VDS in the first approximation, and for example, as shown in Fig. 3, the load linearity is VGs = ■G2s
When they intersect at the point where ■Ds = ■2Ds, V = v
When the signal +(vGls-■G2G5 G25 8) is input, ■, 8=■D1s, and VGS=
When the signal of vG2S+ ("G35-vG2S) is input, vD
By setting s=VD3s, the signal entering the gate can be linearly amplified at the drain. From another perspective, B in FIG. 2 is a current saturation region where the current is saturated. These two basic characteristics are skillfully used to construct the desired operational amplifier. [0008]

【Example】

As shown in FIG. 4, the operational amplifier of the present invention includes a reference voltage source C1, a constant current bias section D that receives the voltage, an input section mirror pair differential stage E and F, and a level differential output of E and F.・Level shift amplification stage G that amplifies while shifting,
It is composed of an output stage H that further amplifies the output and outputs it at a desired low impedance. The outputs of E, F and D are connected in series to form a differential amplifier as a whole. The reason for including the reference voltage source C is to minimize power supply voltage fluctuations and temperature fluctuations in the operational amplifier. For example, variations in the offset power supply E and F due to power supply and temperature can be greatly improved by using a stable reference voltage source C and a constant current bias section. A first column embodying such a configuration is shown in FIG. [0009] FIG. 5 shows an operational amplifier having a dual power supply configuration of V, -V, and VGss. Let us explain FIG. 5 one by one. [00101 Reference voltage source C generates a reference voltage with respect to intermediate voltage ■. The voltage must be generated so that it is stable against power supply fluctuations and temperature fluctuations. Also, the intermediate voltage V2 is V
To set a stable circuit configuration even if the potential is not exactly between DD and V88. In order to meet this requirement and consist only of MOS, the reference voltage is the difference between the MOS thresholds and the intermediate voltage V.
The format is to generate for. [0011] N-channel transistors and 2 are elements with exactly the same characteristics, and if DD-vSS=vdd, their output will be vdd-v with vss as a reference. N-channel transistors 3 and 4 have the same conductance coefficient but different thresholds;
TN, its output vst is vst"" vTN
'GTN+V. N-channel transistors with different thresholds are manufactured by channel doping by ion implantation. Normal C-MO
In order to have a relatively high concentration of S and vGTN'4, for example, 31P+ can be implanted from the gate for channel doping. At that time, if the 3.4 transistors have the same gate film thickness, approximately the same channel length, and channel width, the 3.4 transistors can be transistors with approximately the same conductance coefficients and different thresholds. As for the characteristics, if the threshold shift is the net implantation amount N, the charge element is P, and the unit gate capacitance is C6X, it can be seen that they are equivalent because Nnot/CoX''r is net, and the conductance coefficients are also the same. [0012] However, on the other hand, the method of making the P layer low concentration and obtaining a high threshold by 11B+f Jarnel doping is very structurally sensitive, and the conductance coefficient and threshold are Reflecting its structural sensitivity, it is difficult to logically and experimentally correct the conductance coefficient of a transistor of 3.4 to make it equal.Also, the method of controlling the gate film thickness to be thicker in 3.4 and thinner in 4 is to reduce the conductance coefficient. Even if the coefficients can be made equivalent depending on the geometry, this will not improve because the temperature characteristics of the threshold depend on the gate film thickness.In the end, the reference voltage can be obtained using the method described at the beginning. A low threshold transistor with channel doping as shown in Figure 5
Let's represent the gate with a dashed line, like this. Also C
The reason why an N-channel transistor was adopted in this circuit is because in ordinary C-MOS, the substrate N of P-channel transistors is common, and P is the only substrate that can be floated on the power supply. 1.2 more
In order to match the characteristics of the transistors, body effects do not occur. This is because common use of substrate sources is required. Incidentally, the circuit configuration of C can be implemented in the same manner as shown in FIG. In this circuit 18.20
By matching the ratio of the conductance coefficient of the N-channel transistor of 19.21 to the ratio of the conductance coefficient of the P-channel transistor of 19.21, a difference in the threshold of the P-channel transistor of 19.21 can be generated as a reference voltage. In this case as well, in order to produce a transistor with a different threshold, a high-concentration N substrate is used in the first place, and in order to produce a transistor with a lower threshold, the channel is doped with, for example, 11B+. Alternatively, channel doping is applied to both 19 and 21,
Of course, the doping amount may be changed between 19 and 21. This also applies to 3 and 4 in FIG. Also, the transistor 18.20 may be a high threshold type without a broken line on the gate, and when ■2 is ■dd/2, it is an N-channel transistor in FIG. 5, 2 is omitted, and 3 is used. The gate potential of the N-channel transistor can be set to ■. [0013] Next, receiving the 0 part reference voltage, the D part constant current bias circuit,
The reference voltage is converted from a value based on the intermediate voltage V to a value based on v88, and the constant current source 9 of the differential amplifiers E and F is converted.
Achieve a good constant current bias by keeping the gate potential constant. [0014] By matching the ratio of the conductance coefficients of N-channel transistors 5 and 7 to the ratio of the conductance coefficients of P-channel transistors 6 and 8, the gate voltage of constant current source N-channel transistor 9 becomes vT with reference to V.
S to become N-TGTN. To do this, set the threshold in advance to vT
It is necessary to select such that N>2VGTN. VG=■
, N-vG, N, the gate potential of the constant current source 9 is largely stable against power supply fluctuations and temperature fluctuations, and its constant current property is extremely stable. In order for the constant current property of this transistor to be effectively exhibited, it is necessary that vTN-2VG,N does not reduce the speed of the operational amplifier, that is, the slew rate, below the desired value so that the constant current property is improved. It is necessary to reduce the amount within a certain range. [0015] Next, the differential amplification stage including E, F, and transistor 9 is the most characteristic circuit of the present invention. It is no exaggeration to say that the performance of an operational amplifier depends on this circuit. N-channel transistors 0 and 12 and P-channel transistors 1 and 13 are elements of a mirror pair having exactly the same characteristics. Therefore, the gate voltage of 12, i.e., the inverting input V; the gate voltage of 10, i.e., the non-inverting input, v
When N1 is the same 1'' in-phase input, the respective outputs vD1 and VDNl are equal. This is because the gate and drain of P-channel transistor 1 are connected, and it is also connected to the gate of 13, so that mirror pair 11 and 13 are both in the region shown in FIG. 2B. Furthermore, the common mode input is not amplified as an output. This is because the current flowing into the constant current source 9 is constant, and each half of it is 11.13
This is because the effective gate voltage of 11.13 is constant because it flows out from , and therefore ■DN1, ■, and 1 are constant. [0016] Also, in the case of an input input where ■=■+α, vN■=
(V1+α/2)+α/l 1 2, v■=(V1+α/2)-α/2, so α/2 is in phase, -a/2 (7) It is considered to be a differential input, and 12
The effective gate potential increase of 10 is -(α/2), and the effective gate potential increase of 10 is α/2. Therefore, when the conductance coefficients of 10.11 are almost equal, the effective gate potential increase of 11, that is, 13, is also α/2. As a result, the voltage at the drain connection terminal of 12.13, 1, flows into transistor 12 with current, and moves from transistor 13 so that it does not flow any more, and at the point where the sink and source meet, Balanced and effective differential input amplification. That is, instead of L in Figure 3, the transistor curve of ■Gs=VG2s is v
, 5=vdd is drawn symmetrically from the point and used as a load curve, and the slope of L is almost zero,

This is because the signal [001'8] is amplified. Therefore,
The common mode suppression ratio of the differential amplifier is high, and the constant current source 9
Since the gate voltage is stable against power supply fluctuations and temperature fluctuations, the common mode suppression ratio is also stable. ■80, ■8N
1 is the offset adjustment terminal, which can be adjusted with a 3-terminal variable resistor as shown in Figure 7, or the resistance 22.23 can be adjusted monolithically with a diffused resistor in a semiconductor, a polycrystalline silicon resistor, etc. as shown in Figure 8. The connection between the transistor 11 and the resistor 22 and between the transistor 13 and the resistor 23 can also be adjusted externally using a two-terminal variable resistor. [0019] Furthermore, the circuit of FIG. 7 may be provided between transistors 10 and 12 and transistor 9 in FIG. That is, the source of transistor 10 is connected to vsNl in FIG.
A similar effect can be obtained by connecting the source of transistor 2 to s1 in FIG. 7, and connecting the drain of transistor 9 to V in FIG. [00201] Also, it is important to take measures in design to keep such an offset voltage low in the first place. For example, taking element 10.12 as an example, by arranging two elements point-symmetrically as shown in FIG. 9(b), which is an improved version of FIG. 9(a), the conductance that determines the characteristics of the element is Coefficients (mobility, gate thickness, channel length, channel width), thresholds, and (αV/α■Ds)■G in the region of FIG. 2B
= constant S The saturation resistance given can also be made even. This is because the bias in the distribution of characteristics within the wafer can be corrected. Furthermore, in addition to the problem with the element pattern, one more point is to reduce the constant current value of the differential amplifier stage within a range that does not reduce the slew rate of the operational amplifier below the desired value. Gate voltage ■TN-
The goal is to keep 2vG and N small. In addition, since the gate voltage of 9 is kept constant and the variation in the conductance coefficient is kept low considering Fig. 9(b), it is possible to improve the power supply fluctuation of the offset voltage and, by extension, the power fluctuation rejection ratio. I can do it. Temperature fluctuations can also be improved because variations in the conductance coefficient are kept low and the effective gate voltage of 9 is made small. Furthermore, since the differential input element is an N-channel transistor, the voltage from slightly below GTN to above is V.
You can input almost up to the top of the DD. In order to further improve the input to slightly below ■GTN, if the fluctuation of offset caused by the increase/decrease of the threshold due to the body effect is not a big problem, the substrate of 24.25 as shown in Figure 10 can be changed to ■ss. It can be done. [0021] Next, the level shift circuit G receives the output of the differential amplifier stage.
further amplifies while shifting the level of the differential output. At the same time, fluctuations in the entire system including the differential amplifier, constant current source, and level shift circuit, such as temperature and power fluctuations, are
Not amplified. This is because the output vL does not change because the N-channel transistor 14 and the P-channel transistor 15 fluctuate in the same direction as viewed from their sources to their drains in response to these factors. Also, here as well, the method of amplification is to draw the transistor curve of v = v symmetrically from the point of v, 5 = vdd in Fig. 3, and add V to that curve for GS G2S. 8=v6°8 is essentially the load curve, and its amplification factor is high. [0022] Finally, N that receives the output of vL and configures the output buffer
Channel transistor 16, P channel transistor 1
Inverter 7 amplifies the input and outputs it. The reason why the thresholds for both 16 and 17 are high is to widen the range of linear amplification of the output Vo.If the emphasis is on lowering the output impedance, the channel length should be made smaller than that of other amplification stages, or 2 as shown in Figure 11
6.27 can be a lower threshold due to channel doping. Furthermore, in order to obtain a low impedance output even if the gain of the output circuit is sacrificed, a source/follower output configuration using a 28.29N channel transistor as shown in FIG. 12 can be used. Almost the same effect can be obtained by connecting this 29 substrate to Vss without having to make it common to the source. [0023] Also, in C-MOS, since a connector-grounded NPN emitter follower circuit is simultaneously created using the P- layer forming the N-channel substrate, diffusion or polycrystalline silicon is connected to this as a resistor. For example, Figure 1228
A low impedance emic follower output circuit is also possible by using the N-channel MO3 as a load, as shown in FIG. [0024] Using the operational amplifier in FIG. 5 as a differential amplifier, vo and ■1
If the configuration does not apply feedback between , vN1, there is no problem.In the case where feedback is applied, the problem is stability against oscillation. If a frequency correction capacitor is used for correction, the correction is made by adding a 30.31 capacitor as shown in FIGS. 13(a) and 13(b). Of course, 30V
DD can be replaced with Vss or V2. Also, 31 is 30
Compared to this, with the same frequency correction, the capacity can be reduced to approximately one of the amplification weight of the level shift stage. Furthermore, in cases where oscillation is most likely to occur, such as in a voltage follower, the gain of the output circuit may be sacrificed to directly output V, or the channel length of the output circuit may be made smaller than that of other amplification stages, or If you narrow the amplification range to lower the gain as shown in Figure 11, or reduce the output circuit gain to 1, for example, as shown in Figure 12, the correction capacitance will be reduced to 1/1 of the gain of the output circuit. Can make 1Jz. In this case, the form shown in FIG. 13(b) and, for example, Vo
In the case of correction such as capacitance feedback to vl, the correction capacitor can be monolithically built with an MO3 type capacitor as shown in FIG. In Figure 14, 3
2 is an N- base, 33 is a P high concentration region, 34 is a gate oxide film, 35 is a metal for wiring, for example, aluminum, and 36 is a contact with the P region, which is an alloy forming region with aluminum and the base semiconductor, for example, silicon. be. The distribution of this capacitance is expressed as a lumped constant and is formed as shown in FIG. 15. The capacitor 37 has a unit area capacitance of E o x where the dielectric constant of the gate oxide film is εOX and the film thickness is γ. /γ
Therefore, if γ is decreased, the capacitance increases, but the film thickness suitable for channel doping is approximately 100 OA.
Since the inside and outside are smaller than each other, it can be formed at the same time as forming the gate film of other MOS transistor elements, and the capacitance of 3
In 8, the P diffusion layer is usually 1 to several microns, and even though the dielectric constant of the substrate, for example silicon, is much smaller than that of the gate film,
Since the base concentration of 32 is not so high, 37>38. Therefore, terminals 35 and 36 in FIG.
In the case of 3(b), vv can be either one, and when 35 is ■D1 and D1ゝL, and 36 is vL, it can be made in common with transistor 15. This is because the drain is 33 and the gate is 35. Also, when parasitic capacitor 38 becomes a problem, 35 is set to V
In this case, it is better to set 36 to V and 1, and in the case of capacitive feedback to the input, it is better to set 35 to ■ and 36 to Vl. In a normal C-MOS, an N channel region can also be used as a capacitor, which can be achieved by replacing 32 with P and 33 with N in FIG. [0025] By the way, the operational amplifiers of the present invention shown in FIGS.
- There is no harm in manufacturing it in place of the base. In that case, just change the diffusion format from P to N and from N to P, and change the conductance format from P channel to N channel and from N channel to P channel [0026] Also, E, F, G, H It is also possible to configure the present invention from FIGS. 5 to 15 with only one channel doping, P channel or N channel. Can be manufactured. [0027] For example, ion implantation is carried out by constructing a C circuit as shown in FIG. 6 using 11B, taking a broken line for the N-channel gate, and creating one with a low threshold in accordance with the channel doping of the P-channel. [0028] In order to improve the stability against noise, it is necessary to reduce the gate film thickness of the transistor and increase the gate area. Decreasing the gate film thickness improves the saturation resistance, which increases the gain, and increasing the gate area also increases the gain, since the saturation resistance improves as the channel length increases. In a three-stage amplification stage configuration using C-MOS, the operational amplifier has a gate film thickness of 1000A or less, a channel length of 10μ or more on the mask, which is larger than the digital logic size, and a substrate concentration of 1014/Cm.
With an aluminum gate transistor configuration of 3 or more, an open loop gain of 104 times or more can be obtained, and the stopper spacing is set to 2μ or more to reduce the reverse leakage of the diode that electrically insulates the power supply voltage. This will result in a configuration of 5v or more. [0029] Furthermore, the above invention can be used as a differential amplifier,
It can be used in combination with C or D, or with an appropriate bias circuit and only 9, as a differential stage only, as a level shift circuit, as an output circuit, as well as as a differential stage. It can be used in several ways, such as by connecting a differential stage to the output of a shift stage, or by connecting a differential stage to a differential stage. It can also be used as a comparator to compare two signals, and input voltages higher than VDD can be cut off by a voltage follower, so to speak, as a rectifier. [0030] Next, the operational amplifier using the VDD-■SS- power supply is shown in FIG.
Alternatively, the reference voltage sources C and D in FIG.
, this is possible by doing as shown in FIG. In FIG. 16, an intermediate voltage is created internally by connecting the gate of one of the N-channel transistors 1.2 with the drain in FIG. The intermediate voltage is stabilized by newly connecting 39, which has the same characteristics as 5, in parallel with 1. This is because an effective gate of 5 results in an effective gate voltage of 39. In FIG. 17, an intermediate voltage is created using N-channel transistors 40 and 41, which have exactly the same characteristics, and the source of 5 is connected to this.
By connecting them in parallel, the intermediate voltage is stabilized. In this figure 16, figure 17, the caution mentioned earlier,
In other words, it is effective when a MOS is made from a P-base instead of from an N-base, and whether channel doping is applied or not. For example, in E, F, G, and H of FIGS. 16 and 5, use only 31P+ as ion implantation, take the broken line of the gate of the P-channel transistor, and match it to the threshold of the N-channel transistor to be channel-doped. In FIG. 17, 40 and 41 are N-channel transistors without channel doping, or in FIG. 17 and E and F in FIG.
, G, H, as ion implantation, for example, 11
In this method, the concentration of the P- layer of the N-channel transistor is determined by using the B function, taking the gate dotted line of the N-channel transistor, and matching the threshold of the P-channel transistor to be channel-doped. In addition, if such a power supply can be used, the external GN can be connected by amplifying minute signals.
A very interesting configuration is possible where D is vDD. Furthermore, it is of course possible to use the differential amplifier, comparator, rectifier, etc. mentioned above. [0031]

【Effect of the invention】

In any case, according to the above invention, analog circuits such as differential, arithmetic, comparator, rectifier, etc. using C-MOS can be monolithically fabricated on the same C-MOS chip as digital circuits such as logic circuits. Furthermore, in the present invention, the gate electrodes of the transistors 11 and 13 constituting the differential amplification width are
Since it is connected to the drain electrode of one transistor, both transistors can be operated in the saturation region. Moreover, since the gate electrodes of both transistors are commonly connected, the drain current of both transistors becomes equal due to the property that the drain current in the saturation region depends almost only on the gate voltage, and as a result, transistor 10.1
2 acts so that the same current flows even if the gate voltages are different, so the output vD1 of the differential amplifier stage can obtain a large benefit.

[BRIEF DESCRIPTION OF THE DRAWINGS] [FIG. IIMO3]. FIG. 2 is a diagram showing the current-voltage characteristics of FIG. IMO3. FIG. 3 is a diagram showing the method of amplification of FIG. 1.2MO3. FIG. 4 is an explanatory diagram of the operational amplifier of the present invention. FIG. 5 is a diagram showing a specific example of the operational amplifier of the present invention. 6 to 15 are other specific examples, variations, or explanatory diagrams of the operational amplifier of the present invention. FIG. 16 and FIG. 17 are diagrams showing another specific example of the operational amplifier of the present invention. [Explanation of symbols] G・S・D・'DS" vDS. vGS. ■GS-■GT'"
- Between source 3 Gate Source Drain Current between Drain and Source Voltage between Gate and Source Voltage at boundary of unsaturated (A) and saturated (B) region Drain voltage Load linear reference voltage source Constant current bias section input mirror pair Differential stage level shift amplifier stage output stage power supply plus/minus potential inversion, non-inversion input voltage or its terminal intermediate voltage potential or its terminal reference voltage or its terminal gate voltage of constant current source or its terminals L, C, D, E, F. The source voltage of S1 or the terminal of SNI, ・Level shift stage output voltage or its terminal vo ・Output stage power or its terminal S
10゛G10゛D10 ・Each source, gate, drain S12, G12, D12 of N-channel transistor 10 ・Each source, gate, drain 1 to 5.7.9.10.12.14.16 of N-channel transistor 12. 18
．． 20.24~26.28.29.39.40~42 °N channel transistor 6.8.11.13.15.17.19.21.27・
P-channel transistor 22.23 - Monolithically built resistor 30.3
1. - Capacitor 32.33 - N, P diffusion layer 34 - Gate oxide film 35 - Gate top metal wiring 36 -
・Contact with 33 37. 38・ ・Monolithically formed capacitor [Document author] Drawing [Fig. 1] [Fig. 2] [Fig. 3] [Fig. 6] [Fig. 7] [Fig. 8] [Fig. 9] [ [Fig. 10] [Fig. 11] [Fig. 12] [Fig. 13] [Fig. 14] [Fig. 15] [Fig. 16] [Fig. 17] [Document name] [Reference number] [Submission date] [Address] [Case display] ] [Application number] [Name of the invention] [Person making the amendment] [Relationship with the case] [Identification number] [Address or residence] [Name] [Representative] [Agent] [Identification number] [Patent attorney] [Name] Kizobe Suzuki [Working location Postal code] 163 [Working location] Seiko Epson Corporation, 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo 3348-8531 Ext. 2610-261510009
338B 1990 Patent Application No. 402454 Operational Amplifier Procedure Amendment January 11, 1991

Claims (1)

[Claims] 1. A circuit comprising a reference voltage source, a constant current bias section, a differential amplification stage, a level shift stage, or a reference voltage source, a constant current bias section, a differential amplification stage, a level shift stage, and an output stage, An operational amplifier characterized in that all active elements of the circuit are composed of monolithic insulated gate field effect transistors.