JPS6112391B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operational amplifier using an insulated gate field effect transistor (hereinafter referred to as MOS).

A first object of the present invention is to provide an operational amplifier configured using MOS.

A second object of the present invention is to provide an operational amplifier that can be manufactured monolithically by a normal MOS manufacturing process.

A third object of the present invention is to provide an operational amplifier that can be easily made monolithic together with a digital section such as a logic circuit using MOS.

A third object of the present invention is that since the differential and arithmetic analog circuits described above can be easily monolithic in a normal MOS manufacturing process, the resulting analog section can be made into a MOS logic circuit, etc. The advantage is that it can be easily made monolithic together with the digital part.

Recently, there has been a remarkable shift to MOS in digital parts, and if the analog part could be constructed without much change in the MOS manufacturing process, or if possible, without changing the process at all, various analog circuits and digital circuits could be integrated into the same MOS chip. It is integrated, making it an ideal configuration in terms of price, reliability, ease of design, and applicability. Further, since C-MOS is normally off-logic, it consumes power only in the transient state and has an extremely low power consumption element configuration.
Even the switching level is determined by the MOS threshold, so if one turns on, the other turns on.
When it is turned off, it is stable and when turned off.
Because the impedance is extremely high, the logic amplitude extends up to the power supply voltage. Furthermore, the input bias current of the MOS is approximately 10 ^-12 A due to the insulated gate, achieving the ideal high input impedance of an operational amplifier.

In view of this, the present invention aims to provide an operational amplifier using C-MOS.

The current and voltage characteristics of the MOS shown in Fig. 1 are as shown in Fig. 2, and the voltage between the gate G and the source S is V.
Keeping _GS constant, drain D-source S voltage V
If _DS is changed and the inter-DS current I _DS is taken, then if the threshold voltage of the MOS is V _GT , then V _DS = V _GS −
An unsaturated region A and a saturated region B are observed with V _GT as the boundary. B is the linear variation region of V _DS in the first approximation, and for example, as shown in Fig. 3, the load straight line L intersects the I _DS curve of V _GS = V _G2S at the point where V _DS = V _D2S . When V _GS = V _G2S + (V _G1S −
When a signal of V _G2S ) is input, V _DS = V _D1S and V _GS
When a signal of =V _G2S + (V _G3S - V _G2S ) is input, V _DS =
By setting the voltage to V _D3S , the signal entering the gate can be linearly amplified at the drain. From another perspective, B in FIG. 2 is a constant current region where the current is saturated. These two basic characteristics are used wisely to construct the desired operational amplifier.

As shown in FIG. 4, the operational amplifier of the present invention includes a reference voltage source C, a constant current bias section D receiving the voltage, and an input mirror pair differential stage E and F.
In the embodiment shown in FIG. 4, there is also a level shift amplification stage G that level-shifts and amplifies the differential output of the input mirror pair differential stages E and F; It has an output stage H that outputs impedance. D is connected to E and F in series, and the whole constitutes a differential amplifier. The reason for including the reference voltage source C is to minimize power supply voltage fluctuations and temperature fluctuations in the operational amplifier. For example, fluctuations in offset voltages occurring at E and F due to power source and temperature can be greatly improved by using a stable reference voltage source C and constant current bias section D. A first example embodying such a configuration is shown in FIG.

FIG. 5 shows an operational amplifier with a dual power supply configuration of V _DD - GND - V _SS . Let us explain Fig. 5 one by one.

A reference voltage source C generates a reference voltage with respect to GND. The voltage must be generated so that it is stable against power supply fluctuations and temperature fluctuations. or,
To set up a stable circuit configuration even if GND is not at a potential exactly between V _DD and V _SS . In order to meet this requirement and consist of only MOS, the reference voltage is of a type that generates a difference in the threshold of MOS with respect to GND.Vg. N-channel transistors 1 and 2 are elements with exactly the same characteristics, and when V _DD -V _SS =V _dd , their output becomes V _dd -Vg. N-channel transistors 3 and 4 have the same conductance coefficient but different thresholds. If the thresholds are V _TN for 3 and V _GTN for 4, the output V _ST is V _ST =V _TN -V _GTN +Vg. N-channel transistors with different thresholds are manufactured by channel doping by ion implantation. Since a normal C-MOS has a P ^- layer formed on a low concentration N ^- substrate, the P ^- layer must be made relatively highly doped to obtain the desired V _TN , and in order to obtain V _GTN , for example, ³¹ P ⁺ can be made by channel doping and driving it from the gate. At that time, 3 and 4 are the same gate film thickness,
If the channel length and channel width are approximately equal, transistors 3 and 4 can be transistors with approximately the same conductance coefficient but different thresholds, and the temperature characteristics will also be such that the threshold shift will affect the net implantation amount.
If Nnet, elementary charge q, and unit gate capacitance are Cox, they can be considered to be equivalent because they are given by qNnet/Cox, and it is safe to assume that the conductance coefficients are also equivalent. However, on the other hand, if the concentration of the P ^- layer is low,
¹¹ The method of obtaining a high threshold with B ⁺ channel doping is that the method is very structure sensitive, and the conductance coefficient, the threshold increases its structure sensitivity, and the conductance coefficient of 3 or 4 transistors can be calculated theoretically and experimentally. It is difficult to correct and make them equal. Furthermore, the method of controlling the gate film thickness to be thick at 3 and thin at 4 is not good because the temperature characteristics of the threshold depend on the gate film thickness, even though the conductance coefficients can be made the same depending on the geometry. After all, the reference voltage can be obtained using the method described at the beginning.
Hereinafter, such a low threshold transistor due to channel doping will be represented by a broken line at the gate as shown in FIG. or,
The reason why N-channel transistors were used in the C circuit is that in normal C-MOS, the substrate N ^- of P-channel transistors is common.
Substrates that can be floated on a power supply are P ^-
This is because only Furthermore, in order to match the characteristics of the first and second transistors, it is necessary to use a common substrate source that does not cause a body effect. Incidentally, the circuit configuration of C can be similarly implemented as shown in FIG. In this circuit, by matching the ratio of the conductance coefficients of the N-channel transistors 18 and 20 and the conductance coefficients of the P-channel transistors 19 and 21, the difference between the thresholds of the P-channel transistors 19 and 21 is generated as a reference voltage. can be done. In this case as well, in order to produce a transistor with a different threshold, a high concentration N ^- substrate is used in the first place, and in order to produce a transistor with a lower threshold, channel doping is performed, for example with ¹¹ B ⁺ . Alternatively, apply channel doping to both 19 and 21, and reduce the doping amount to 1.
Of course, you can change it between 9 and 21. This also applies to 3 and 4 in FIG. Also, transistors 18 and 20 may be threshold type transistors that do not have a broken line on their gates, and when GND is V _dd /2, N-channel transistors 1 and 2 are omitted in FIG. The gate potential of the N-channel transistor can be set to Vg.

Next, in response to the C part reference voltage, the D part constant current bias circuit converts the reference voltage from the GND level to a measure of the V _SS level, and keeps the gate potential of the constant current source transistors 9 of the differential amplifiers E and F constant. Keep to achieve good constant current bias. This constant current bias makes it possible to minimize the influence of the offset of the differential stage even with voltage fluctuations and temperature fluctuations, thereby achieving high precision in operational amplification.

Ratio of conductance coefficients of N-channel transistors 5 and 7 and P-channel transistors 6 and 8
By matching the ratio of the conductance coefficients of the constant current source N-channel transistor 9, the gate voltage of the constant current source N-channel transistor 9 is measured from the V _SS level, and the C section reference power supply output becomes V _TN -V _GN . In order to do this, it is necessary to select the threshold in advance so that V _TN >2V _GTN . By setting V _G =V _TN -V _GTN , the gate potential of the constant current source 9 is stable against power supply fluctuations and temperature fluctuations, and its constant current property is extremely stable. In order for the constant current property of this transistor to be effectively exhibited, it is necessary that V _TN -2V _GTN does not reduce the speed of the operational amplifier, that is, the slew rate, below the desired value in order to improve the constant current property shown in Figure 2B. It is necessary to reduce the range.

Next, the differential amplification stage including E, F, and constant current source transistor 9 is the most important circuit of an operational amplifier, and it is no exaggeration to say that the performance of an operational amplifier depends on this circuit. . N-channel transistors 10 and 12 and P-channel transistors 11 and 13 are elements of a mirror pair having exactly the same characteristics. Therefore, when the gate voltages of 12, ie, the inverting input V _I , and the gate voltages of 10, ie, the non-inverting input V _NI are equal in-phase inputs, the respective outputs V _DI and V _DNI are equal. P
Gate of channel transistor 11. This is because the drains are connected and are further connected together with the gate of 13, so that mirror pairs 11 and 13 are both in the region of FIG. 2B. Moreover, the common mode input is not amplified as an output. because,
The current flowing into constant current source 9 is constant, and half of it flows from 11 and 13, so 11,
The effective gate voltage of 13 is constant, so V
This is because _DNT and V _DI are constant.

Also, when an input that makes V _NI = V _I + α is input, V _NI = (V _I + α/2) + α/2, V _I = (V _I + α
/2) - α/2, which is considered to be an in-phase input of α/2 and a differential input of α/2, and 1
The effective gate potential increase of 2 is -α/2, and the effective gate potential increase of 10 is α/2. Therefore, when the conductance coefficients of 10 and 11 are almost equal, the effective gate potential increase of 11, that is, 13 is also α/2. As a result, the voltage V _DI at the drain connection terminals 1, 2, and 13 moves so that any current flows into the transistor 12, but does not flow from the transistor 13,
That sink. Provides effective differential input amplification that is balanced at the point where the sources match. This is essentially nothing more than drawing the transistor curve of V _GS = V _G2S symmetrically from the point of V _DS = V _dd instead of L in Fig. 3 and using it as the load curve, and the slope of L is approximately It has a configuration such that it is zero, and its V _G1S 〓V _G
This is because the signal _2S −α is amplified. Therefore, the common mode suppression ratio of this differential amplifier is high,
Furthermore, since the gate voltage of the constant current source 9 is stable against power supply fluctuations and temperature fluctuations, the common mode suppression ratio is also stable. V _SI and V _SNI are offset adjustment terminals, which can be adjusted with a 3-terminal variable resistor as shown in Figure 7, or by using resistors 22 and 23 with diffused resistors in semiconductors or polycrystalline resistors as shown in Figure 8. It is also possible to configure it monolithically using a silicon resistor or the like, and adjust the distance between the transistor 11 and the resistor 22, and between the transistor 13 and the resistor 23 externally using a two-terminal variable resistor. or,
In FIG. 7, the source of transistor 10 is connected to V
The same effect can be obtained by replacing _SNI with the source of transistor 12 as V _SI and the drain of transistor 9 with V _DD and inserting a three-terminal variable resistor between them.

It is also important to devise a design that keeps such offset voltage low in the first place. For example, element 1
0 and 12, the conductance coefficient (mobility, mobility, gate film thickness, channel length, channel width), threshold, and
The saturation resistances given by ∂V _DS /∂I _DS V _G = constant in region B of FIG. 2 can also be made almost the same. This is because the bias in the distribution of characteristics within the wafer can be corrected. Furthermore, in addition to the problem with the element pattern, one more point is to reduce the constant current value of the differential amplifier within a range that does not reduce the slew rate of the operational amplifier below the desired value, that is, the effective gate voltage V of the constant current source 9. _TN −2V The goal is to keep _GTN small. Also, the gate voltage of 9 is kept constant and the conductance coefficient is 9-
By keeping the variation low in consideration of figure b, it is possible to improve the power supply fluctuation of the offset voltage and, by extension, the power supply fluctuation rejection ratio. Temperature fluctuations can also be improved because variations in the conductance coefficient are kept low and the effective gate voltage of 9 is made small. Furthermore, since the differential input elements are N-channel transistors, it is possible to input inputs from slightly below 2V _GTN at the bottom to almost above _VDD at the top. V further down
To improve the input to slightly below _GTN ,
If the variation in offset resulting from the increase/decrease in the threshold due to the body effect is not a big problem,
As shown in Figure 10, the substrates 24 and 25 are
It can be made into _SS .

Next, upon receiving the output of the differential stage, the level shift circuit G shifts the level of the differential output and further amplifies it. At the same time, the system as a whole including the differential circuit, constant current source, and level shift circuit does not amplify these fluctuations, such as fluctuations in temperature and power supply. This is because the output V _L does not change because the N-channel transistor 14 and the P-channel transistor 15 fluctuate in the same direction as viewed from their respective sources to the drains due to these factors.
Again, the method of amplification is V _GS in Figure 3.
=V _G2S is drawn symmetrically from the point of V _DS =V _dd , and the curve of V _GS =V _G2S is used as a load curve with respect to that curve, and its amplification factor is high.

Finally, upon receiving the output of V _L , an inverter consisting of an N-channel transistor 16 and a P-channel transistor 17 forming an output buffer amplifies the input and outputs it. The reason why thresholds 16 and 17 are set high is to widen the range of linear amplification of the output V _O. If the emphasis is on lowering the output impedance, the channel length should be made smaller than that of other amplification stages, or 26,2 as shown in Figure 11
7 to a low threshold by channel doping. Furthermore, in order to obtain a low impedance output even if the gain of the output circuit is sacrificed, a source-follower output configuration using 28 and 29N channel transistors can be used as shown in FIG. Almost the same effect can be obtained by connecting this 29 substrate to V _SS without making it common to the source.

In addition, in C-MOS, since the emitter follower circuit of the collector-grounded NPN is simultaneously sent using the P ^- layer forming the N-channel substrate, it is necessary to connect diffused or polycrystalline silicon as a resistor to this, for example, as shown in Fig. 12. 28 Like N Channel
A low impedance emitter follower output circuit is also possible by using a MOS as a load.

Using the operational amplifier shown in Figure 5 as a differential amplifier,
There is no problem if the configuration does not apply feedback between V _O , V _I , and V _NI , but the problem with a configuration in which feedback is applied is stability against oscillation. If a frequency correction capacitor is used for correction, it is corrected by adding capacitors 30 and 31 as shown in FIGS. 13a and 13b. Of course, 30V _DD can be replaced with V _SS or GND. Also, 31 is 3
Compared to zero, with the same frequency correction, the capacitance can be reduced to approximately 1/the amplification factor of the level shift stage. Furthermore, in the case where oscillation is least likely to occur, such as in a voltage follower, it is necessary to directly output V _L at the expense of the gain of the output circuit, or to make the channel length of the output circuit smaller than that of other amplification stages. Alternatively, if you narrow the amplification range considerably to lower the gain as shown in Figure 11, or reduce the output circuit gain to 1, for example, as shown in Figure 12, the correction capacitance will further increase the gain of the output circuit. It can be made smaller by a factor of 1. In this case, in the case of the form shown in Fig. 13b, and in the case of correction such as capacitance feedback from V _O to V _I , the correction capacitor is
As shown in Figure 4, it can be fabricated monolithically using a MOS type capacitor. In Figure 14, 32 is
In the N ^- base, 33 is a P ⁺ high concentration region, 34 is a gate oxide film, 35 is a metal for wiring, such as aluminum, and 36 is a contact with the P ⁺ region, which is an alloy formation region with aluminum and the substrate semiconductor, such as silicon. be. If this capacitance distribution is expressed as a lumped constant, it will be formed as shown in Figure 15, but the capacitance 37
The unit area capacitance is given by ε _OX /τ, where ε _OX is the dielectric constant of the gate oxide film and τ is the film thickness, so if τ is made smaller, the capacitance increases,
Since the film thickness suitable for channel doping is about 1000 Å or less, it can be formed at the same time as forming the gate film of other MOS ^transistor elements. Although the dielectric constant of the substrate, for example silicon, is higher than that of the gate film, the concentration of the substrate 32 is not so high, so 37>38. Therefore, the first
Terminals 35 and 36 in Fig. 5 may be either V _DI or V _L in the case of Fig. 13-b, and when 35 is V _DI and 36 is V _L , they can be made in common with transistor 15. . This is because the drain is 33 and the gate is 35. Also, when parasitic capacitor 38 becomes a problem, it is better to set 35 to V _L and 36 to V _DI , and in the case of capacitive feedback to the input, 3
It is better to set 5 to V _O and 36 to V _I. normal C
-MOS can also use the N-channel region as a capacitor, and in Figure 14, 32 can be changed to P ^- 3.
You can do this by changing 3 to N ⁺ .

By the way, the operational amplifiers of the present invention shown in FIGS. 5 to 15 also have no problem even if the ordinary C-MOS is manufactured on an N ^- substrate instead of an N-substrate and a P ^- substrate. It's not something you can do. In that case, all that is required is to change the diffusion format from P to N to P, and to change the conductance format from P channel to N channel, and from N channel to P channel. or,
E, F, G, and H can be configured with MOS transistors with either P or N channel doping or without both P and N channels, or even if channel doping is used, only one of P channel or N channel is required as shown in Figure 5. The invention up to FIG. 15 can be manufactured. For example, the C circuit is constructed as shown in FIG. 6 by implanting only ¹¹ B ⁺ ions, and the broken line of the N channel gate is taken, and a low threshold is created in accordance with the channel doping of the P channel.

In order to improve stability against noise, it is necessary to reduce the gate film thickness of the transistor and increase the gate area. Decreasing the gate film thickness improves the saturation resistance, which increases the gain, and increasing the gate area also increases the gain, since the saturation resistance improves as the channel length increases. In a three-stage C-MOS amplification stage configuration, the operational amplifier has a gate film thickness of 1000 Å or less, a channel length of 10 μ or more on the mask, which is larger than the digital logic size, and the substrate concentration is
With an aluminum gate transistor configuration of 10 ¹⁴ /cm ² or more, it is possible to obtain an open loop gain of 10 ⁴ times or more, and the power supply voltage can be adjusted to a stopper to reduce reverse leakage of the diode that electrically insulates the element. If the gap is 2μ or more, the voltage will be 5V or more.

Furthermore, the present invention described above can be used as a differential amplifier, and it can be used in various ways: using only the differential stage together with C or D, including the level shift circuit, and including the output circuit. other,
It can be used in several ways, such as by connecting a differential stage to the output of a level shift stage, or by connecting a differential stage to a differential stage. It can also be used as a comparator to compare two signals, and input voltages higher than V _DD can be cut off by a voltage follower, so to speak, as a rectifier.

Next, an operational amplifier using one power supply with V _DD - V _SS is:
This is possible by replacing the reference voltage sources C and D in FIG. 5 or 6 with those shown in FIGS. 16 and 17, respectively. In FIG. 16, the N-channel transistors 1 and 1, which have exactly the same characteristics in FIG.
Create GND internally by connecting the gate of 1 of 2 to the drain, connect the source of 5 to this, and connect 39, which has exactly the same characteristics as 5, in parallel with 1 to increase the current due to 5. By doing that
GND is stabilized. This is because the effective gate voltage of 5 becomes the effective gate voltage of 39. In Figure 17, 4 with completely equal characteristics
Create a GND with an N-channel transistor of 0.41, connect the source of 5 to this, and add 42 to 40, which has exactly the same characteristics as 5, to increase the current due to 5.
By connecting it in parallel with the GND, the GND is stabilized. In these Figures 16 and 17 as well, note the above-mentioned precautions, namely, starting from the P ^- base instead of the N ^- base.
It is effective when creating a MOS using a substrate, and whether channel doping is applied or not. For example, in F, E, G, and H of FIG. 16 and FIG. 5, for example, only ³¹ P ⁺ is used as ion implantation, and the broken line of the gate of the P channel transistor is taken, and the threshold of the N channel transistor to be channel doped is taken. Adjust the threshold of the P channel transistor according to N ^-
To determine the concentration of the base, in Figure 17,
40 and 41 are N-channel transistors without channel doping, or in E, F, G, and H in FIGS. 17 and 5, for example, only "B ⁺ is used as ion implantation, and Take the broken line and adjust the threshold of the N-channel transistor to match the threshold of the P-channel transistor to be channel-doped.
This is the kind that determines the concentration of the P ^- layer. Also, if you can use a single power source like this, you can amplify a small signal to
A very interesting configuration can be made with GND as V _DD . Furthermore, it is of course possible to use the differential amplifier, comparator, rectifier, etc. mentioned above.

In any case, according to the present invention, C--
Analog circuits such as differential, arithmetic, comparators, and rectifiers using MOS can be fabricated monolithically on the same MOS chip as digital circuits such as logic circuits. Furthermore, channel doping and the like for analog circuits can be done in accordance with that for digital circuits, and there is no difference in the number of man-hours. Furthermore, silicon gate MOS does not require a metal gate, and MOS using a substrate such as sapphire, spinel, or GaAs does not require a silicon base.
Similarly, this idea can flourish because of the price,
It is comparable to bipolar in terms of reliability, variety, and performance.

As described above, the present invention uses channel doping to vary the threshold voltages of MOS transistors of the same polarity, generates this threshold voltage difference as a stable reference voltage, and controls the constant current source transistor based on this voltage. By doing so,
It is possible to prevent the influence of the offset of the operational amplifier against temperature changes and voltage changes, and to improve the accuracy of the operational amplifier.

[Brief explanation of the drawing]

Figure 1 is a diagram representing MOS. Figure 2 is Figure 1
A diagram showing the current-voltage characteristics of MOS. FIG. 3 is a diagram showing a method of amplifying the MOS shown in FIGS. 1 and 2. FIG. 4 is an explanatory diagram of the operational amplifier of the present invention. FIG. 5 shows a specific example of the operational amplifier of the present invention. Figures 6 to 15 are 5
FIG. 1 is an explanatory diagram of an operational amplifier according to the present invention. FIGS. 16 and 17 show another specific example of the operational amplifier of the present invention. G...gate, S...source, D...drain, _IDS
...Drain-source current, V _DS ...Drain-source voltage, V _GS ...Gate-source voltage, V _GS
-V _GT ...Drain-source voltage at the boundary between unsaturated A and saturated B regions, L...Load line, C...Reference voltage source, D...Low current bias section, E, F...Input mirror pair differential stage, G …Level shift amplification stage, H…Output stage, _VDD , _VSS …Plus/minus potential of the power supply, V _I , V _NI …Inverting or non-inverting input voltage or its terminal, _Vg …Ground (GND) potential or its terminal. Terminal, V _ST ...Reference voltage or its terminal, V _G ...
Gate voltage of constant current source or its terminal, V _DI , V
_DNI ...Drain voltage of inverting, non-inverting input transistor or its terminal, V _SI , V _SNI ...Source voltage of E, F differential stage P channel transistor or its terminal, _VL ...Level shift stage output voltage or its terminal , V _O ...output stage voltage or its terminal,
_S10 , _G10 , _D10 ... Each source, gate, and drain of the N-channel transistor 10, _S12 , _G12 , _D12 ...
Each source, gate, and drain of the N-channel transistor 12, 1 to 5, 7, 9, 10, 12, 1
4, 16, 18, 20, 24-26, 28, 2
9, 39, 40-42...N channel transistor, 6, 8, 11, 13, 15, 17, 19, 2
1, 27...P channel transistor, 22, 23
... Monolithically fabricated resistor, 30, 31... Capacitor, 32, 33... N ^- , P ⁺ diffusion layer, 34
...Gate oxide film, 35...Metal wiring on gate, 3
6...Contact with 33, 37, 38...Capacitor formed monolithically.

Claims (1)

[Claims] 1. In an amplifier consisting of a reference voltage source, a constant current bias section, a differential amplification stage, and a level shift stage, the active elements constituting the reference voltage source, constant current bias section, differential amplification stage, and level shift stage are all made of the same semiconductor. The constant current bias section includes an insulated gate field effect transistor formed on a substrate, and includes a constant current source transistor connected in series with the differential amplification stage, and a gate electrode of the constant current source transistor. is characterized in that a constant voltage based on a reference voltage of the reference voltage source is applied, and the reference voltage source outputs a difference in threshold voltage caused by a difference in channel doping of field effect transistors of the same polarity as a reference voltage. operational amplifier.