JP2006041232A - High frequency circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency circuit capable of simply and appropriately adjusting impedance matching after forming a semiconductor device in a substrate. <P>SOLUTION: A high frequency circuit 40 is provided with a field-effect transistor 6 and matching circuits 2, 3 and 4. The field-effect transistor 6 comprises a semiconductor substrate 8 including a channel domain 18, a source region 10 and a drain region 11 which estrange each other in-between the channel region 18 and are formed in the surface of the semiconductor substrate 8, a body region 9 constituted by semiconductor substrate 8 directly under the channel region 18, a source electrode 14 connected to the source region 10, a drain electrode 15 connected to the drain region 11, a body electrode 16 connected to the body region 9, and a gate electrode 13 arranged on the channel region 18. The matching circuits 2, 3 and 4 are connected to each of the source electrode 14, the drain electrode 15, and the gate electrode 13. For impedance matching, bias voltage is impressed to the body electrode 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a high-frequency circuit, and more particularly to a high-frequency circuit that enables matching adjustment after a semiconductor element is formed on a substrate.

  FIG. 6 is a diagram showing a circuit configuration of a conventional high-frequency circuit (high-frequency amplifier) used for mobile communication devices and wireless LAN applications.

  As shown in FIG. 6, the conventional high-frequency circuit 30 includes a field effect transistor 1 including a source terminal S, a drain terminal D, and a gate terminal G. By inputting a high-frequency signal Vin to the gate terminal G, the drain terminal A circuit configured to obtain an output signal Vout amplified from D. An input matching circuit 2 that performs impedance matching of the input signal Vin, an output matching circuit 3 that performs impedance matching of the output signal Vout, and a matching circuit 4 for improving linearity are respectively a gate terminal G and a drain terminal. D and source terminal S are connected. Further, a surge bias circuit 5 for surge countermeasures is disposed between the terminal of the power supply voltage Vdd and the drain terminal D.

  Each of the matching circuits 2, 3, 4 and the surge bias circuit 5 is an appropriate combination circuit of an inductor element, a resistance element, a capacitor element, and a diode element.

  More specifically, an example of the input matching circuit 2 includes an inductor element connected to the terminal of the input signal Vin and the ground part, a resistor element connected to the gate terminal G and the ground part, and a terminal of the input signal Vin of the inductor element. And a capacitor element connected to an end connected to the gate terminal G of the resistance element.

  An example of the output matching circuit 3 is a capacitor element disposed between the drain terminal D and the terminal of the output signal Vout, one end of the capacitor element (one end opposite to the terminal of Vout), and a terminal of the power supply voltage Vdd. And an inductor element disposed between the two.

  An example of the matching circuit 4 for improving linearity includes a resistance element and a capacitor element connected in parallel to the source terminal S, and an inductor element connected to the resistance element, the capacitor element, and the ground portion. , Is composed of.

  An example of the surge bias circuit 5 is one end of an instance element constituting the output matching circuit 3 (one end opposite to the drain terminal D and also connected to the terminal of the power supply voltage Vdd) and a grounding portion. And a resistance element and a diode element arranged in parallel with the capacitor element, the resistance element is connected to the terminal side of the power supply voltage Vdd, and the diode element is connected to the ground portion side. These elements are connected in series so as to be connected to each other.

  Here, when such a microwave monolithic integrated circuit (MMIC) configuration in which the field effect transistor 1 and the matching circuits 2, 3, 4 and the surge bias circuit 5 are incorporated in one chip is employed, these circuits are the same. The semiconductor substrate is formed by an appropriate semiconductor process.

  On the other hand, if these circuits are separately formed into modules, each of the active circuit and the passive circuit is a chip component, and these chip components are soldered and mounted on a printed circuit board.

  The range in which such circuits are integrated on one chip depends on the degree of variation in the characteristics of each circuit and the yield. For example, only the output matching circuit 3 is built in and integrated with the field effect transistor 1 in one chip, and measures for improving the yield are implemented by a module configuration in which other circuits are external chip components.

As an example of the development of such a high-frequency circuit, a circuit has been proposed in which the impedance of the protection circuit that prevents surge electrostatic breakdown does not change due to the bias voltage, thereby suppressing the occurrence of impedance matching deviation during operation of the high-frequency circuit. (See Patent Document 1).
JP 2003-274553 A

  However, when the semiconductor elements constituting the high-frequency circuit 30 shown in FIG. 6 are formed on the substrate, the capacitor elements (chip components) of the matching circuits 2, 3, and 4 and the inductor elements (chips) are used to adjust the impedance matching. Although there is a need to find an optimal combination of these while mounting components) and resistance elements (chip components), there are an infinite number of such combinations. For this reason, the adjustment work of the impedance matching of the matching circuits 2, 3, and 4 is a great burden on the manufacturing cost.

  In recent years, it has been studied to reduce the cost of the high-frequency circuit by stopping the adjustment work by adopting the MMIC configuration rather than the module configuration. A high-frequency circuit having an MMIC configuration with a large variation in matching characteristics and stably maintaining a high yield has not been obtained.

  The present invention has been made in view of the above circumstances, and is a high-frequency circuit composed of various semiconductor elements formed on a substrate. After these semiconductor elements are formed on a substrate, impedance matching is simplified. An object of the present invention is to provide a high-frequency circuit that can be appropriately adjusted.

  In order to solve the above problems, a high-frequency circuit according to the present invention includes a semiconductor substrate including a channel region, a source region and a drain region formed on the surface of the semiconductor substrate spaced apart from each other with the channel region interposed therebetween, A body region formed by the semiconductor substrate immediately below the channel region, a source electrode connected to the source region, a drain electrode connected to the drain region, a body electrode connected to the body region, and A field effect transistor having a gate electrode disposed on the channel region; and a matching circuit connected to each of the source electrode, the drain electrode, and the gate electrode, for impedance matching to the body electrode This bias voltage is applied. Here, the high frequency circuit may include a voltage generation circuit for generating the bias voltage.

  This is a high-frequency circuit composed of various semiconductor elements formed on the substrate. After these semiconductor elements are formed on the substrate, the impedance matching can be easily and easily performed by applying a bias voltage for impedance matching to the body electrode. A high-frequency circuit that can be appropriately adjusted is obtained.

  An example of the voltage generation circuit is a circuit that generates a voltage by resistance division. Thereby, a bias voltage can be easily generated.

  An example of the voltage generation circuit is a circuit that generates a voltage using a regulator. Thereby, the bias voltage can be arbitrarily changed.

  The field effect transistor may be a Schottky junction field effect transistor. The semiconductor substrate may be a GaAs substrate, and the body electrode may be disposed on the back surface of the GaAs.

  In such a configuration, when the thickness of the semiconductor substrate is 5 μm or more and 100 μm or less, an effective bias voltage can be applied to the body region immediately below the channel region.

  The field effect transistor, the matching circuit, and the voltage generation circuit may be mounted on separate substrates, and the field effect transistor and at least one matching circuit are mounted on the same substrate. The integrated circuit and the voltage generating circuit may be mounted on separate substrates, and the field effect transistor, the matching circuit, and the voltage generating circuit are integrated circuits mounted on the same substrate. There may be.

  According to the present invention, there is provided a high frequency circuit composed of various semiconductor elements formed on a substrate, wherein the impedance matching can be easily and appropriately adjusted after these semiconductor elements are formed on the substrate. can get.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of a high-frequency circuit according to an embodiment of the present invention.

  As understood from the comparison between FIG. 1 (embodiment) and FIG. 6 (conventional example), the high-frequency circuit 40 shown in FIG. 1 is different from the high-frequency circuit 30 shown in FIG. A voltage generation circuit 7 for applying a bias voltage for impedance matching is added to a body terminal B for applying a predetermined bias voltage to a body region (to be described later) by connecting to an electrode (to be described later). Is to be placed.

  That is, the high frequency amplifier 40 shown in FIG. 1 has a field effect transistor 1 including a source terminal S, a drain terminal D, a gate terminal G, and a body terminal B, and inputs a high frequency signal Vin to the gate terminal G. It is a circuit configured to obtain an amplified output signal Vout from a terminal D. An input matching circuit 2 for impedance matching of the input signal Vin, an output matching circuit 3 for impedance matching of the output signal Vout, a matching circuit 4 for improving linearity, and a voltage generation circuit 7 are respectively provided. The gate terminal G, drain terminal D, source terminal S and body terminal B are connected.

  Further, a surge bias circuit 5 for surge countermeasures is disposed between the terminal of the power supply voltage Vdd and the drain terminal D.

  Of course, as a configuration example of the high frequency circuit 40, only the body terminal B may be provided in the high frequency circuit 40, and a voltage generation circuit for applying a bias voltage to the body terminal 40 may be provided separately.

  The internal configuration of each of the matching circuits 2, 3, 4 and the surge bias circuit 5 shown in FIG. 1 is the same as that shown in FIG.

  The voltage generation circuit 7 is configured by a simple circuit that generates a voltage by resistance division. Specifically, the voltage generation circuit 7 is formed by two resistance elements 7R for voltage division arranged in series between the terminal of the power supply voltage Vdd and the ground portion. The part which is comprised and connects between both the resistance elements 7R is connected to the body terminal B. Then, by changing the resistance ratio of the resistance element 7R, the power supply voltage Vdd is divided by the resistance element 7R at an appropriate ratio, and thereby the body terminal B (more specifically, the body electrode 16 shown in FIG. 2 or FIG. 3). A bias voltage for impedance matching is applied.

  Examples of the field effect transistor 6 include a MOS field effect transistor and a Schottky junction field effect transistor, and the configuration thereof will be described below with reference to the drawings.

  First, a configuration example of a MOS field effect transistor will be described.

  FIG. 2 is a cross-sectional view schematically showing the structure of the MOS transistor in the present embodiment.

  The field effect transistor 6 shown in FIG. 2 includes a silicon substrate 8 (semiconductor substrate) including a channel region 18 and a source region 10 and a drain formed on the surface of the silicon substrate 8 so as to be spaced apart from each other with the channel region 18 interposed therebetween. Region 11, body region 9 formed in silicon substrate 8 so as to surround channel region 18, source region 10, and drain region 11, and having a conductivity type different from that of source region 10 and drain region 11, channel region 18, and source region 10 is formed on the surface of the silicon substrate 8 so as to cover a part of the drain region 11 and the drain region 11, and the source region 10 is connected to the source region 10 in order to control the voltage of the source region 10. In order to control the voltage between the source electrode 14 disposed on the surface and the drain region 11, the drain region 11, a drain electrode 15 disposed on the surface of the silicon substrate 8 and a body electrode 16 disposed on the surface of the silicon substrate 8 connected to the body region 9 to control the voltage of the body region 9; In order to control the voltage of the channel region 18, the gate electrode 13 is disposed on the gate oxide film 12 so as to face the channel region 18.

  Note that the gate electrode 13, the source electrode 14, the drain electrode 15, and the body electrode 16 are connected to the gate terminal G, the source terminal S, the drain terminal D, and the body terminal B, respectively, shown in FIG. Illustrations of G, S, D, and B are omitted.

Here, the concentration of impurity carriers in the body region 9 is about 10 ¹⁷ cm ⁻³ to 10 ¹⁸ cm ⁻³ , whereby the body region 9 (silicon) immediately below the channel region 18 is applied by the voltage applied to the body electrode 16. It is possible to generate an effective electric field for impedance matching on the surface layer portion of the substrate 8.

  Next, a configuration example of a Schottky junction field effect transistor will be described.

  FIG. 3 is a cross-sectional view schematically showing the structure of the Schottky junction field effect transistor in the present embodiment.

  The field effect transistor 6 shown in FIG. 3 includes a GaAs (gallium arsenide) substrate 17 (semiconductor substrate) including a channel region 18 and a source formed on the surface of the GaAs substrate 17 so as to be separated from each other across the channel region 18. In order to control the voltage of the source region 10 and the region 10 and the drain region 11, the body region 9 constituted by the GaAs substrate 17 other than the source region 10 and the drain region 11 and the channel region 18. A source electrode 14 connected to the surface of the GaAs substrate 17, a drain electrode 15 connected to the drain region 11 to control the voltage of the drain region 11 and a surface of the GaAs substrate 17, a body In order to control the voltage of the region 9, it is connected to the body region 9 and arranged on the back surface of the GaAs substrate 17. A body electrode 16, a, a gate electrode 13 disposed on the surface of the GaAs substrate 17 opposite to the channel region 18 to control the voltage of the channel region 18.

  Note that the gate electrode 13, the source electrode 14, the drain electrode 15, and the body electrode 16 are connected to the gate terminal G, the source terminal S, the drain terminal D, and the body terminal B, respectively, shown in FIG. Illustrations of G, S, D, and B are omitted.

  The body electrode 16 also serves as a heat radiating plate (metal plate) for radiating heat generated according to the current capacity flowing through the GaAs substrate 17.

  The GaAs substrate 17 is a semi-insulating substrate, and the GaAs substrate 17 corresponds to the body region 9 as a whole. Therefore, an effective electric field for impedance matching is applied to the body region 9 (GaAs substrate 17) immediately below the channel region 18 by the voltage applied to the body electrode 16 disposed on the back surface of the GaAs substrate 17. It is necessary to reduce the thickness of the GaAs substrate 17. It has been confirmed that an effective electric field can be obtained when the thickness of the GaAs substrate 17 is polished to about 80 μm. From this result, it can be said that the GaAs substrate 17 needs to be thinly polished so that the thickness is at least 100 μm or less, desirably 80 μm or less, and more desirably 50 μm or less. However, since it is difficult to manufacture the GaAs substrate 17 with a thickness of less than 5 μm, the thickness range of the GaAs substrate 17 is 100 μm or less, 5 μm or more, desirably 80 μm or less, 5 μm or more, and more desirably 50 μm or less, 5 μm. That's it.

  When a bias voltage is applied to the body electrode 16 of the high-frequency circuit 40, impedance matching of the high-frequency circuit 40 can be achieved as described below.

  FIG. 4 is a Smith chart for explaining that impedance matching of a high-frequency circuit can be achieved by applying a voltage to the body electrode. The impedance is measured using the Schottky junction field effect transistor shown in FIG. is there.

  Vd shown in FIG. 4 is a voltage applied to the body electrode 16, and FIG. 4 shows a comparison of impedance characteristics at Vd = 0V and Vd = −1V (negative bias applied to the back surface of the GaAs substrate). . S22 is a power reflection coefficient viewed from the output side when the input side in the S parameter is matched, and S21 is the power transmission coefficient corresponding to the power amplification factor (gain).

  As understood from FIG. 4, it has been found that the impedance of the field effect transistor 6 can be varied by applying a bias to the body electrode 16 (the GaAs substrate 17 side shown in FIG. 3) of the field effect transistor 6.

  More specifically, if a negative bias (Vd = −1V) is applied to the body electrode 16, S22 deviates from the point P indicating the characteristic impedance (50 ohms), and is on the outer side compared to zero bias (Vd = 0V). If a positive bias is applied, it approaches point P and moves inward compared to zero bias (Vd = 0V) (not shown). Thus, by applying an appropriate bias to the body electrode 16, S22 on the output side can be controlled, and consequently the impedance of the field effect transistor 6 can be controlled.

  Therefore, the conventional complicated impedance matching adjustment work of optimization of various elements in the matching circuits 2, 3, and 4 can be stopped, and the impedance matching can be adjusted only by adjusting the voltage of the body electrode 16, and the impedance matching adjustment work is simple. Can be Even a manufactured MMIC or a single transistor can be adjusted for impedance matching.

  According to FIG. 4, it can be seen that the gain S21 is increased by applying a negative bias (Vd = −1V) to the body electrode 16. This is because by applying a negative bias by reducing the thickness of the GaAs substrate 17, the AC current flowing to the GaAs substrate 17 side increases, the drain conductance decreases, and the gate capacitance decreases. is there.

  Further, the field effect transistor 6 and the matching circuits 2, 3, 4, the surge bias circuit 5 and the voltage generation circuit 7 described above are all built in one chip and configured as an integrated circuit integrated on the same substrate. Alternatively, these may be mounted on separate substrates and configured as an integrated circuit. Alternatively, the field effect transistor 6 and at least one matching circuit are built in one chip and configured as an integrated circuit integrated on the same substrate, and the integrated circuit and the voltage generation circuit 7 are mounted on separate substrates. You may comprise as follows.

[Modification]
Up to this point, as a voltage generation circuit for generating a voltage to be applied to the body terminal B in the high-frequency circuit, a circuit that generates a voltage by simple resistance division has been exemplified. As a modification of this, as shown in FIG. The circuit 7 may be a circuit that generates a voltage using the regulator 20. That is, in accordance with an input signal to the body bias control terminal BC, the regulator 20 connected to the terminal of the power supply voltage Vdd generates an appropriate bias voltage, thereby arbitrarily applying a bias voltage for impedance matching to the body terminal B. It can be applied in a variable manner.

  The configuration of the high-frequency circuit 50 shown in FIG. 5 is the same as that of the high-frequency circuit 40 shown in FIG.

  According to the high-frequency circuit of the present invention, it is possible to adjust the impedance matching of the field-effect transistor by applying a bias voltage to the body region of the high-frequency field-effect transistor, such as a mobile communication device or a wireless LAN. Applicable to high frequency circuits such as high frequency amplifiers and mixers.

It is a circuit diagram of the high frequency circuit concerning an embodiment of the invention. It is sectional drawing which shows typically the structure of the MOS type transistor in this Embodiment. It is sectional drawing which shows typically the structure of the Schottky junction type field effect transistor in this Embodiment. It is a Smith chart explaining that the impedance matching of a high frequency circuit can be taken by the voltage application with respect to a body electrode. It is a figure which shows the modification of the voltage generation circuit in a high frequency circuit. It is the figure which showed the circuit structure of the conventional high frequency circuit (high frequency amplifier).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 6 Field effect transistor 2 Input matching circuit 3 Output matching circuit 4 Matching circuit 5 Surge bias circuit 7 Voltage generating circuit 8 Silicon substrate 9 Body region 10 Source region 11 Drain region 12 Gate oxide film 13 Gate electrode 14 Source electrode 15 Drain Electrode 16 Body electrode 17 GaAs substrate 18 Channel region 20 Regulator 30, 40, 50 High frequency circuit

Claims (10)

A semiconductor substrate including a channel region; a source region and a drain region formed on a surface of the semiconductor substrate spaced apart from each other across the channel region; and a body region formed by the semiconductor substrate immediately below the channel region; An electric field having a source electrode connected to the source region, a drain electrode connected to the drain region, a body electrode connected to the body region, and a gate electrode disposed on the channel region An effect transistor;
And a matching circuit connected to each of the source electrode, the drain electrode, and the gate electrode, and a high-frequency circuit to which a bias voltage for impedance matching is applied to the body electrode.   The high-frequency circuit according to claim 1, further comprising a voltage generation circuit that generates the bias voltage.   The high-frequency circuit according to claim 2, wherein the voltage generation circuit is a circuit that generates a voltage by resistance division.   The high-frequency circuit according to claim 2, wherein the voltage generation circuit is a circuit that generates a voltage using a regulator.   2. The high frequency circuit according to claim 1, wherein the field effect transistor is a Schottky junction type field effect transistor.   The high-frequency circuit according to claim 5, wherein the semiconductor substrate is a GaAs substrate, and the body electrode is disposed on a back surface of the GaAs substrate.   The high-frequency circuit according to claim 6, wherein the semiconductor substrate has a thickness of 5 μm or more and 100 μm or less.   The high-frequency circuit according to claim 2, wherein the field effect transistor, the matching circuit, and the voltage generation circuit are each mounted on separate substrates.   3. The high-frequency circuit according to claim 2, wherein the field effect transistor and at least one matching circuit are integrated circuits mounted on the same substrate, and the integrated circuit and the voltage generation circuit are mounted on separate substrates. . 3. The high frequency circuit according to claim 2, wherein the field effect transistor, the matching circuit, and the voltage generation circuit are integrated circuits mounted on the same substrate.

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